1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn31/dcn31_init.h"
9 #include "dcn351/dcn351_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "basics/conversion.h"
14 #include "dcn351_resource.h"
15
16 #include "dcn20/dcn20_resource.h"
17 #include "dcn30/dcn30_resource.h"
18 #include "dcn31/dcn31_resource.h"
19 #include "dcn32/dcn32_resource.h"
20 #include "dcn35/dcn35_resource.h"
21
22 #include "dcn10/dcn10_ipp.h"
23 #include "dcn30/dcn30_hubbub.h"
24 #include "dcn31/dcn31_hubbub.h"
25 #include "dcn35/dcn35_hubbub.h"
26 #include "dcn32/dcn32_mpc.h"
27 #include "dcn35/dcn35_hubp.h"
28 #include "irq/dcn351/irq_service_dcn351.h"
29 #include "dcn35/dcn35_dpp.h"
30 #include "dcn35/dcn35_optc.h"
31 #include "dcn20/dcn20_hwseq.h"
32 #include "dcn30/dcn30_hwseq.h"
33 #include "dce110/dce110_hwseq.h"
34 #include "dcn35/dcn35_opp.h"
35 #include "dcn35/dcn35_dsc.h"
36 #include "dcn30/dcn30_vpg.h"
37 #include "dcn30/dcn30_afmt.h"
38
39 #include "dcn31/dcn31_dio_link_encoder.h"
40 #include "dcn35/dcn35_dio_stream_encoder.h"
41 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
42 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
43 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
44 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
45 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
46 #include "link_service.h"
47 #include "dcn31/dcn31_apg.h"
48 #include "dcn32/dcn32_dio_link_encoder.h"
49 #include "dcn31/dcn31_vpg.h"
50 #include "dcn31/dcn31_afmt.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_hwseq.h"
54 #include "clk_mgr.h"
55 #include "dio/virtual/virtual_stream_encoder.h"
56 #include "dio/dcn10/dcn10_dio.h"
57 #include "dce110/dce110_resource.h"
58 #include "dml/display_mode_vba.h"
59 #include "dcn35/dcn35_dccg.h"
60 #include "dcn35/dcn35_pg_cntl.h"
61 #include "dcn10/dcn10_resource.h"
62 #include "dcn31/dcn31_panel_cntl.h"
63 #include "dcn35/dcn35_hwseq.h"
64 #include "dcn35/dcn35_dio_link_encoder.h"
65 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
66 #include "dml/dcn35/dcn35_fpu.h"
67 #include "dml/dcn351/dcn351_fpu.h"
68 #include "dcn35/dcn35_dwb.h"
69 #include "dcn35/dcn35_mmhubbub.h"
70
71 #include "dcn/dcn_3_5_1_offset.h"
72 #include "dcn/dcn_3_5_1_sh_mask.h"
73 #include "nbio/nbio_7_11_0_offset.h"
74 #include "mmhub/mmhub_3_3_0_offset.h"
75 #include "mmhub/mmhub_3_3_0_sh_mask.h"
76
77 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
78 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
79
80 #include "reg_helper.h"
81 #include "dce/dmub_abm.h"
82 #include "dce/dmub_psr.h"
83 #include "dce/dmub_replay.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
87 #include "vm_helper.h"
88 #include "dcn20/dcn20_vmid.h"
89
90 #include "dml2_0/dml2_wrapper.h"
91
92 #include "link_enc_cfg.h"
93 #define DC_LOGGER_INIT(logger)
94
95 enum dcn351_clk_src_array_id {
96 DCN351_CLK_SRC_PLL0,
97 DCN351_CLK_SRC_PLL1,
98 DCN351_CLK_SRC_PLL2,
99 DCN351_CLK_SRC_PLL3,
100 DCN351_CLK_SRC_PLL4,
101 DCN351_CLK_SRC_TOTAL
102 };
103
104 /* begin *********************
105 * macros to expend register list macro defined in HW object header file
106 */
107
108 /* DCN */
109 /* TODO awful hack. fixup dcn20_dwb.h */
110 #undef BASE_INNER
111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
112
113 #define BASE(seg) BASE_INNER(seg)
114
115 #define SR(reg_name)\
116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
117 reg ## reg_name
118
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
121
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name = value
124
125 #define SRI(reg_name, block, id)\
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SRI_ARR(reg_name, block, id)\
130 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 reg ## block ## id ## _ ## reg_name
132
133 #define SR_ARR_I2C(reg_name, id) \
134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
135
136 #define SRI_ARR_I2C(reg_name, block, id)\
137 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI_ARR_DME(reg_name, block, id, offset)\
141 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
145 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 reg ## block ## id ## _ ## reg_name
147
148 #define SRI2(reg_name, block, id)\
149 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 reg ## reg_name
151
152 #define SRI2_ARR(reg_name, block, id)\
153 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
154 reg ## reg_name
155
156 #define SRIR(var_name, reg_name, block, id)\
157 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRII(reg_name, block, id)\
161 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII_ARR_2(reg_name, block, id, inst)\
165 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRII_MPC_RMU(reg_name, block, id)\
169 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SRII_DWB(reg_name, temp_name, block, id)\
173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## temp_name
175
176 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
177 .field_name = reg_name ## __ ## field_name ## post_fix
178
179 #define DCCG_SRII(reg_name, block, id)\
180 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
182
183 #define VUPDATE_SRII(reg_name, block, id)\
184 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
185 reg ## reg_name ## _ ## block ## id
186
187 /* NBIO */
188 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
189
190 #define NBIO_BASE(seg) \
191 NBIO_BASE_INNER(seg)
192
193 #define NBIO_SR(reg_name)\
194 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
195 regBIF_BX1_ ## reg_name
196
197 #define NBIO_SR_ARR(reg_name, id)\
198 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
199 regBIF_BX1_ ## reg_name
200
201 #define bios_regs_init() \
202 ( \
203 NBIO_SR(BIOS_SCRATCH_3),\
204 NBIO_SR(BIOS_SCRATCH_6)\
205 )
206
207 static struct bios_registers bios_regs;
208
209 #define clk_src_regs_init(index, pllid)\
210 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
211
212 static struct dce110_clk_src_regs clk_src_regs[5];
213
214 static const struct dce110_clk_src_shift cs_shift = {
215 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
216 };
217
218 static const struct dce110_clk_src_mask cs_mask = {
219 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
220 };
221
222 #define abm_regs_init(id)\
223 ABM_DCN32_REG_LIST_RI(id)
224
225 static struct dce_abm_registers abm_regs[4];
226
227 static const struct dce_abm_shift abm_shift = {
228 ABM_MASK_SH_LIST_DCN35(__SHIFT)
229 };
230
231 static const struct dce_abm_mask abm_mask = {
232 ABM_MASK_SH_LIST_DCN35(_MASK)
233 };
234
235 #define audio_regs_init(id)\
236 AUD_COMMON_REG_LIST_RI(id)
237
238 static struct dce_audio_registers audio_regs[7];
239
240
241 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
242 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
243 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
244 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
245
246 static const struct dce_audio_shift audio_shift = {
247 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
248 };
249
250 static const struct dce_audio_mask audio_mask = {
251 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
252 };
253
254 #define vpg_regs_init(id)\
255 VPG_DCN31_REG_LIST_RI(id)
256
257 static struct dcn31_vpg_registers vpg_regs[10];
258
259 static const struct dcn31_vpg_shift vpg_shift = {
260 DCN31_VPG_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dcn31_vpg_mask vpg_mask = {
264 DCN31_VPG_MASK_SH_LIST(_MASK)
265 };
266
267 #define afmt_regs_init(id)\
268 AFMT_DCN31_REG_LIST_RI(id)
269
270 static struct dcn31_afmt_registers afmt_regs[6];
271
272 static const struct dcn31_afmt_shift afmt_shift = {
273 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dcn31_afmt_mask afmt_mask = {
277 DCN31_AFMT_MASK_SH_LIST(_MASK)
278 };
279
280 #define apg_regs_init(id)\
281 APG_DCN31_REG_LIST_RI(id)
282
283 static struct dcn31_apg_registers apg_regs[4];
284
285 static const struct dcn31_apg_shift apg_shift = {
286 DCN31_APG_MASK_SH_LIST(__SHIFT)
287 };
288
289 static const struct dcn31_apg_mask apg_mask = {
290 DCN31_APG_MASK_SH_LIST(_MASK)
291 };
292
293 #define stream_enc_regs_init(id)\
294 SE_DCN35_REG_LIST_RI(id)
295
296 static struct dcn10_stream_enc_registers stream_enc_regs[5];
297
298 static const struct dcn10_stream_encoder_shift se_shift = {
299 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
300 };
301
302 static const struct dcn10_stream_encoder_mask se_mask = {
303 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
304 };
305
306 #define aux_regs_init(id)\
307 DCN2_AUX_REG_LIST_RI(id)
308
309 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
310
311 #define hpd_regs_init(id)\
312 HPD_REG_LIST_RI(id)
313
314 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
315
316
317 static const struct dce110_aux_registers_shift aux_shift = {
318 DCN_AUX_MASK_SH_LIST(__SHIFT)
319 };
320
321 static const struct dce110_aux_registers_mask aux_mask = {
322 DCN_AUX_MASK_SH_LIST(_MASK)
323 };
324
325 #define link_regs_init(id, phyid)\
326 ( \
327 LE_DCN35_REG_LIST_RI(id), \
328 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
329 )
330
331 static struct dcn10_link_enc_registers link_enc_regs[5];
332
333 static const struct dcn10_link_enc_shift le_shift = {
334 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
335 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
336 };
337
338 static const struct dcn10_link_enc_mask le_mask = {
339 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
340 //DPCS_DCN31_MASK_SH_LIST(_MASK)
341 };
342
343 #define hpo_frl_stream_encoder_dme_reg_list(id)\
344 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6)
345
346 #define hpo_frl_stream_encoder_reg_list(id)\
347 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
348
349 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
350
351 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
352 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
353 };
354
355 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
356 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
357 };
358
359 #define hpo_frl_link_encoder_reg_list(id)\
360 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
361
362 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
363
364 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
365 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
366 };
367
368 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
369 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
370 };
371
372 #define hpo_dp_stream_encoder_reg_init(id)\
373 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
374
375 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
376
377 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
378 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
379 };
380
381 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
382 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
383 };
384
385 #define hpo_dp_link_encoder_reg_init(id)\
386 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
387 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
388 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
389 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
390 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
391
392 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
393
394 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
395 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
396 };
397
398 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
399 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
400 };
401
402 #define dpp_regs_init(id)\
403 DPP_REG_LIST_DCN35_RI(id)
404
405 static struct dcn3_dpp_registers dpp_regs[4];
406
407 static const struct dcn35_dpp_shift tf_shift = {
408 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
409 };
410
411 static const struct dcn35_dpp_mask tf_mask = {
412 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
413 };
414
415 #define opp_regs_init(id)\
416 OPP_REG_LIST_DCN35_RI(id)
417
418 static struct dcn35_opp_registers opp_regs[4];
419
420 static const struct dcn35_opp_shift opp_shift = {
421 OPP_MASK_SH_LIST_DCN35(__SHIFT)
422 };
423
424 static const struct dcn35_opp_mask opp_mask = {
425 OPP_MASK_SH_LIST_DCN35(_MASK)
426 };
427
428 #define aux_engine_regs_init(id)\
429 ( \
430 AUX_COMMON_REG_LIST0_RI(id), \
431 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
432 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
433 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
434 )
435
436 static struct dce110_aux_registers aux_engine_regs[5];
437
438 #define dwbc_regs_dcn3_init(id)\
439 DWBC_COMMON_REG_LIST_DCN30_RI(id)
440
441 static struct dcn30_dwbc_registers dwbc35_regs[1];
442
443 static const struct dcn35_dwbc_shift dwbc35_shift = {
444 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
445 };
446
447 static const struct dcn35_dwbc_mask dwbc35_mask = {
448 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
449 };
450
451 #define mcif_wb_regs_dcn3_init(id)\
452 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
453
454 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
455
456 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
457 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
458 };
459
460 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
461 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
462 };
463
464 #define dsc_regsDCN35_init(id)\
465 DSC_REG_LIST_DCN20_RI(id)
466
467 static struct dcn20_dsc_registers dsc_regs[4];
468
469 static const struct dcn35_dsc_shift dsc_shift = {
470 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
471 };
472
473 static const struct dcn35_dsc_mask dsc_mask = {
474 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
475 };
476
477 static struct dcn30_mpc_registers mpc_regs;
478
479 #define dcn_mpc_regs_init() \
480 MPC_REG_LIST_DCN3_2_RI(0),\
481 MPC_REG_LIST_DCN3_2_RI(1),\
482 MPC_REG_LIST_DCN3_2_RI(2),\
483 MPC_REG_LIST_DCN3_2_RI(3),\
484 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
485 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
486 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
487 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
488 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
489
490 static const struct dcn30_mpc_shift mpc_shift = {
491 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
492 };
493
494 static const struct dcn30_mpc_mask mpc_mask = {
495 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
496 };
497
498 #define optc_regs_init(id)\
499 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
500
501 static struct dcn_optc_registers optc_regs[4];
502
503 static const struct dcn_optc_shift optc_shift = {
504 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
505 };
506
507 static const struct dcn_optc_mask optc_mask = {
508 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
509 };
510
511 #define hubp_regs_init(id)\
512 HUBP_REG_LIST_DCN30_RI(id)
513
514 static struct dcn_hubp2_registers hubp_regs[4];
515
516
517 static const struct dcn35_hubp2_shift hubp_shift = {
518 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
519 };
520
521 static const struct dcn35_hubp2_mask hubp_mask = {
522 HUBP_MASK_SH_LIST_DCN35(_MASK)
523 };
524
525 static struct dcn_hubbub_registers hubbub_reg;
526
527 #define hubbub_reg_init()\
528 HUBBUB_REG_LIST_DCN35(0)
529
530 static const struct dcn_hubbub_shift hubbub_shift = {
531 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
532 };
533
534 static const struct dcn_hubbub_mask hubbub_mask = {
535 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
536 };
537
538 static struct dccg_registers dccg_regs;
539
540 #define dccg_regs_init()\
541 DCCG_REG_LIST_DCN35()
542
543 static const struct dccg_shift dccg_shift = {
544 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
545 };
546
547 static const struct dccg_mask dccg_mask = {
548 DCCG_MASK_SH_LIST_DCN35(_MASK)
549 };
550
551 static struct pg_cntl_registers pg_cntl_regs;
552
553 #define pg_cntl_dcn35_regs_init() \
554 PG_CNTL_REG_LIST_DCN35()
555
556 static const struct pg_cntl_shift pg_cntl_shift = {
557 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
558 };
559
560 static const struct pg_cntl_mask pg_cntl_mask = {
561 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
562 };
563
564 #define SRII2(reg_name_pre, reg_name_post, id)\
565 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
566 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
567 reg ## reg_name_pre ## id ## _ ## reg_name_post
568
569 static struct dce_hwseq_registers hwseq_reg;
570
571 #define hwseq_reg_init()\
572 HWSEQ_DCN35_REG_LIST()
573
574 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
575 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
576 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
577 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
578 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
579 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
580 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
581 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
582 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
583 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
584 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
585 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
586 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
587 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
588 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
589 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
590 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
591 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
592 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
593 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
594 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
595 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
596 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
597 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
598 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
599 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
600 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
601 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
602 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
603 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
604 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
605 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
615 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
616 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
619 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
620 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
621 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
622 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
623 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
624 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
625 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
626 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
627 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
628 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
629 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
630 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
631 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
632 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
633 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
634 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
635 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
636 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
637 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
638 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
639 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
640 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
641 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
642 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
643 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
644 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
645 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
646 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
647 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
648 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
649 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
650 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
651 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
652 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
653 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
654 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
655 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
656 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
657 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
658 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
659 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
660 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
661 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
662
663 static const struct dce_hwseq_shift hwseq_shift = {
664 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
665 };
666
667 static const struct dce_hwseq_mask hwseq_mask = {
668 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
669 };
670
671 #define vmid_regs_init(id)\
672 DCN20_VMID_REG_LIST_RI(id)
673
674 static struct dcn_vmid_registers vmid_regs[16];
675
676 static const struct dcn20_vmid_shift vmid_shifts = {
677 DCN20_VMID_MASK_SH_LIST(__SHIFT)
678 };
679
680 static const struct dcn20_vmid_mask vmid_masks = {
681 DCN20_VMID_MASK_SH_LIST(_MASK)
682 };
683
684 static struct dcn_dio_registers dio_regs;
685
686 #define DIO_MASK_SH_LIST(mask_sh)\
687 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
688
689 static const struct dcn_dio_shift dio_shift = {
690 DIO_MASK_SH_LIST(__SHIFT)
691 };
692
693 static const struct dcn_dio_mask dio_mask = {
694 DIO_MASK_SH_LIST(_MASK)
695 };
696
697 static const struct resource_caps res_cap_dcn351 = {
698 .num_timing_generator = 4,
699 .num_opp = 4,
700 .num_video_plane = 4,
701 .num_audio = 5,
702 .num_stream_encoder = 5,
703 .num_dig_link_enc = 5,
704 .num_hpo_frl = 1,
705 .num_hpo_dp_stream_encoder = 4,
706 .num_hpo_dp_link_encoder = 2,
707 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
708 .num_dwb = 1,
709 .num_ddc = 5,
710 .num_vmid = 16,
711 .num_mpc_3dlut = 2,
712 .num_dsc = 4,
713 };
714
715 static const struct dc_plane_cap plane_cap = {
716 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
717 .per_pixel_alpha = true,
718
719 .pixel_format_support = {
720 .argb8888 = true,
721 .nv12 = true,
722 .fp16 = true,
723 .p010 = true,
724 .ayuv = false,
725 },
726
727 .max_upscale_factor = {
728 .argb8888 = 16000,
729 .nv12 = 16000,
730 .fp16 = 16000
731 },
732
733 // 6:1 downscaling ratio: 1000/6 = 166.666
734 .max_downscale_factor = {
735 .argb8888 = 250,
736 .nv12 = 167,
737 .fp16 = 167
738 },
739 64,
740 64
741 };
742
743 static const struct dc_debug_options debug_defaults_drv = {
744 .limit_ffe = 3,
745 .disable_dmcu = true,
746 .force_abm_enable = false,
747 .clock_trace = true,
748 .disable_pplib_clock_request = false,
749 .pipe_split_policy = MPC_SPLIT_AVOID,
750 .force_single_disp_pipe_split = false,
751 .disable_dcc = DCC_ENABLE,
752 .disable_dpp_power_gate = true,
753 .disable_hubp_power_gate = true,
754 .disable_optc_power_gate = true, /*should the same as above two*/
755 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
756 .disable_clock_gate = false,
757 .disable_dsc_power_gate = true,
758 .vsr_support = true,
759 .performance_trace = false,
760 .max_downscale_src_width = 4096,/*upto true 4k*/
761 .disable_pplib_wm_range = false,
762 .scl_reset_length10 = true,
763 .sanity_checks = false,
764 .underflow_assert_delay_us = 0xFFFFFFFF,
765 .dwb_fi_phase = -1, // -1 = disable,
766 .dmub_command_table = true,
767 .pstate_enabled = true,
768 .use_max_lb = true,
769 .enable_mem_low_power = {
770 .bits = {
771 .vga = false,
772 .i2c = true,
773 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
774 .dscl = true,
775 .cm = true,
776 .mpc = true,
777 .optc = true,
778 .vpg = true,
779 .afmt = true,
780 }
781 },
782 .root_clock_optimization = {
783 .bits = {
784 .dpp = true,
785 .dsc = true,/*dscclk and dsc pg*/
786 .hdmistream = true,
787 .hdmichar = true,
788 .dpstream = true,
789 .symclk32_se = true,
790 .symclk32_le = false,
791 .symclk_fe = true,
792 .physymclk = false,
793 .dpiasymclk = true,
794 }
795 },
796 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
797 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
798 .minimum_z8_residency_time = 1,
799 .using_dml2 = true,
800 .support_eDP1_5 = true,
801 .enable_hpo_pg_support = false,
802 .enable_single_display_2to1_odm_policy = true,
803 .disable_idle_power_optimizations = false,
804 .disable_boot_optimizations = false,
805 .disable_unbounded_requesting = false,
806 .disable_mem_low_power = false,
807 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
808 .enable_double_buffered_dsc_pg_support = true,
809 .enable_dp_dig_pixel_rate_div_policy = 1,
810 .disable_z10 = false,
811 .ignore_pg = true,
812 .psp_disabled_wa = true,
813 .ips2_eval_delay_us = 2000,
814 .ips2_entry_delay_us = 800,
815 .disable_dmub_reallow_idle = false,
816 .static_screen_wait_frames = 2,
817 .notify_dpia_hr_bw = true,
818 .min_disp_clk_khz = 50000,
819 };
820
821 static const struct dc_check_config config_defaults = {
822 .enable_legacy_fast_update = false,
823 };
824
825 static const struct dc_panel_config panel_config_defaults = {
826 .psr = {
827 .disable_psr = false,
828 .disallow_psrsu = false,
829 .disallow_replay = false,
830 },
831 .ilr = {
832 .optimize_edp_link_rate = true,
833 },
834 };
835
dcn35_dpp_destroy(struct dpp ** dpp)836 static void dcn35_dpp_destroy(struct dpp **dpp)
837 {
838 kfree(TO_DCN20_DPP(*dpp));
839 *dpp = NULL;
840 }
841
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)842 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
843 {
844 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
845 bool success = (dpp != NULL);
846
847 if (!success)
848 return NULL;
849
850 #undef REG_STRUCT
851 #define REG_STRUCT dpp_regs
852 dpp_regs_init(0),
853 dpp_regs_init(1),
854 dpp_regs_init(2),
855 dpp_regs_init(3);
856
857 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
858 &tf_mask);
859 if (success) {
860 dpp35_set_fgcg(
861 dpp,
862 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
863 return &dpp->base;
864 }
865
866 BREAK_TO_DEBUGGER();
867 kfree(dpp);
868 return NULL;
869 }
870
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)871 static struct output_pixel_processor *dcn35_opp_create(
872 struct dc_context *ctx, uint32_t inst)
873 {
874 struct dcn20_opp *opp =
875 kzalloc_obj(struct dcn20_opp);
876
877 if (!opp) {
878 BREAK_TO_DEBUGGER();
879 return NULL;
880 }
881
882 #undef REG_STRUCT
883 #define REG_STRUCT opp_regs
884 opp_regs_init(0),
885 opp_regs_init(1),
886 opp_regs_init(2),
887 opp_regs_init(3);
888
889 dcn35_opp_construct(opp, ctx, inst,
890 &opp_regs[inst], &opp_shift, &opp_mask);
891
892 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
893
894 return &opp->base;
895 }
896
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)897 static struct dce_aux *dcn31_aux_engine_create(
898 struct dc_context *ctx,
899 uint32_t inst)
900 {
901 struct aux_engine_dce110 *aux_engine =
902 kzalloc_obj(struct aux_engine_dce110);
903
904 if (!aux_engine)
905 return NULL;
906
907 #undef REG_STRUCT
908 #define REG_STRUCT aux_engine_regs
909 aux_engine_regs_init(0),
910 aux_engine_regs_init(1),
911 aux_engine_regs_init(2),
912 aux_engine_regs_init(3),
913 aux_engine_regs_init(4);
914
915 dce110_aux_engine_construct(aux_engine, ctx, inst,
916 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
917 &aux_engine_regs[inst],
918 &aux_mask,
919 &aux_shift,
920 ctx->dc->caps.extended_aux_timeout_support);
921
922 return &aux_engine->base;
923 }
924
925 #define i2c_inst_regs_init(id)\
926 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
927
928 static struct dce_i2c_registers i2c_hw_regs[5];
929
930 static const struct dce_i2c_shift i2c_shifts = {
931 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
932 };
933
934 static const struct dce_i2c_mask i2c_masks = {
935 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
936 };
937
938 /* ========================================================== */
939
940 /*
941 * DPIA index | Preferred Encoder | Host Router
942 * 0 | C | 0
943 * 1 | First Available | 0
944 * 2 | D | 1
945 * 3 | First Available | 1
946 */
947 /* ========================================================== */
948 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
949 ENGINE_ID_DIGC,
950 ENGINE_ID_DIGC,
951 ENGINE_ID_DIGD,
952 ENGINE_ID_DIGD
953 };
954
dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)955 static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
956 {
957 return dpia_to_preferred_enc_id_table[dpia_index];
958 }
959
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)960 static struct dce_i2c_hw *dcn31_i2c_hw_create(
961 struct dc_context *ctx,
962 uint32_t inst)
963 {
964 struct dce_i2c_hw *dce_i2c_hw =
965 kzalloc_obj(struct dce_i2c_hw);
966
967 if (!dce_i2c_hw)
968 return NULL;
969
970 #undef REG_STRUCT
971 #define REG_STRUCT i2c_hw_regs
972 i2c_inst_regs_init(1),
973 i2c_inst_regs_init(2),
974 i2c_inst_regs_init(3),
975 i2c_inst_regs_init(4),
976 i2c_inst_regs_init(5);
977
978 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
979 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
980
981 return dce_i2c_hw;
982 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)983 static struct mpc *dcn35_mpc_create(
984 struct dc_context *ctx,
985 int num_mpcc,
986 int num_rmu)
987 {
988 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
989
990 if (!mpc30)
991 return NULL;
992
993 #undef REG_STRUCT
994 #define REG_STRUCT mpc_regs
995 dcn_mpc_regs_init();
996
997 dcn32_mpc_construct(mpc30, ctx,
998 &mpc_regs,
999 &mpc_shift,
1000 &mpc_mask,
1001 num_mpcc,
1002 num_rmu);
1003
1004 return &mpc30->base;
1005 }
1006
dcn351_dio_create(struct dc_context * ctx)1007 static struct dio *dcn351_dio_create(struct dc_context *ctx)
1008 {
1009 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1010
1011 if (!dio10)
1012 return NULL;
1013
1014 #undef REG_STRUCT
1015 #define REG_STRUCT dio_regs
1016 DIO_REG_LIST_DCN10();
1017
1018 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1019
1020 return &dio10->base;
1021 }
1022
dcn35_hubbub_create(struct dc_context * ctx)1023 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
1024 {
1025 int i;
1026
1027 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1028
1029 if (!hubbub3)
1030 return NULL;
1031
1032 #undef REG_STRUCT
1033 #define REG_STRUCT hubbub_reg
1034 hubbub_reg_init();
1035
1036 #undef REG_STRUCT
1037 #define REG_STRUCT vmid_regs
1038 vmid_regs_init(0),
1039 vmid_regs_init(1),
1040 vmid_regs_init(2),
1041 vmid_regs_init(3),
1042 vmid_regs_init(4),
1043 vmid_regs_init(5),
1044 vmid_regs_init(6),
1045 vmid_regs_init(7),
1046 vmid_regs_init(8),
1047 vmid_regs_init(9),
1048 vmid_regs_init(10),
1049 vmid_regs_init(11),
1050 vmid_regs_init(12),
1051 vmid_regs_init(13),
1052 vmid_regs_init(14),
1053 vmid_regs_init(15);
1054
1055 hubbub35_construct(hubbub3, ctx,
1056 &hubbub_reg,
1057 &hubbub_shift,
1058 &hubbub_mask,
1059 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1060 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1061 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1062
1063
1064 for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
1065 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1066
1067 vmid->ctx = ctx;
1068
1069 vmid->regs = &vmid_regs[i];
1070 vmid->shifts = &vmid_shifts;
1071 vmid->masks = &vmid_masks;
1072 }
1073
1074 return &hubbub3->base;
1075 }
1076
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1077 static struct timing_generator *dcn35_timing_generator_create(
1078 struct dc_context *ctx,
1079 uint32_t instance)
1080 {
1081 struct optc *tgn10 =
1082 kzalloc_obj(struct optc);
1083
1084 if (!tgn10)
1085 return NULL;
1086
1087 #undef REG_STRUCT
1088 #define REG_STRUCT optc_regs
1089 optc_regs_init(0),
1090 optc_regs_init(1),
1091 optc_regs_init(2),
1092 optc_regs_init(3);
1093
1094 tgn10->base.inst = instance;
1095 tgn10->base.ctx = ctx;
1096
1097 tgn10->tg_regs = &optc_regs[instance];
1098 tgn10->tg_shift = &optc_shift;
1099 tgn10->tg_mask = &optc_mask;
1100
1101 dcn35_timing_generator_init(tgn10);
1102
1103 return &tgn10->base;
1104 }
1105
1106 static const struct encoder_feature_support link_enc_feature = {
1107 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1108 .max_hdmi_pixel_clock = 600000,
1109 .hdmi_ycbcr420_supported = true,
1110 .dp_ycbcr420_supported = true,
1111 .fec_supported = true,
1112 .flags.bits.IS_HBR2_CAPABLE = true,
1113 .flags.bits.IS_HBR3_CAPABLE = true,
1114 .flags.bits.IS_TPS3_CAPABLE = true,
1115 .flags.bits.IS_TPS4_CAPABLE = true
1116 };
1117
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1118 static struct link_encoder *dcn35_link_encoder_create(
1119 struct dc_context *ctx,
1120 const struct encoder_init_data *enc_init_data)
1121 {
1122 struct dcn20_link_encoder *enc20 =
1123 kzalloc_obj(struct dcn20_link_encoder);
1124
1125 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1126 return NULL;
1127
1128 #undef REG_STRUCT
1129 #define REG_STRUCT link_enc_aux_regs
1130 aux_regs_init(0),
1131 aux_regs_init(1),
1132 aux_regs_init(2),
1133 aux_regs_init(3),
1134 aux_regs_init(4);
1135
1136 #undef REG_STRUCT
1137 #define REG_STRUCT link_enc_hpd_regs
1138 hpd_regs_init(0),
1139 hpd_regs_init(1),
1140 hpd_regs_init(2),
1141 hpd_regs_init(3),
1142 hpd_regs_init(4);
1143
1144 #undef REG_STRUCT
1145 #define REG_STRUCT link_enc_regs
1146 link_regs_init(0, A),
1147 link_regs_init(1, B),
1148 link_regs_init(2, C),
1149 link_regs_init(3, D),
1150 link_regs_init(4, E);
1151
1152 dcn35_link_encoder_construct(enc20,
1153 enc_init_data,
1154 &link_enc_feature,
1155 &link_enc_regs[enc_init_data->transmitter],
1156 &link_enc_aux_regs[enc_init_data->channel - 1],
1157 &link_enc_hpd_regs[enc_init_data->hpd_source],
1158 &le_shift,
1159 &le_mask);
1160
1161 return &enc20->enc10.base;
1162 }
1163
1164 /* Create a minimal link encoder object not associated with a particular
1165 * physical connector.
1166 * resource_funcs.link_enc_create_minimal
1167 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1168 static struct link_encoder *dcn31_link_enc_create_minimal(
1169 struct dc_context *ctx, enum engine_id eng_id)
1170 {
1171 struct dcn20_link_encoder *enc20;
1172
1173 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1174 return NULL;
1175
1176 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1177 if (!enc20)
1178 return NULL;
1179
1180 dcn31_link_encoder_construct_minimal(
1181 enc20,
1182 ctx,
1183 &link_enc_feature,
1184 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1185 &le_shift,
1186 &le_mask,
1187 eng_id);
1188
1189 return &enc20->enc10.base;
1190 }
1191
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1192 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1193 {
1194 struct dcn31_panel_cntl *panel_cntl =
1195 kzalloc_obj(struct dcn31_panel_cntl);
1196
1197 if (!panel_cntl)
1198 return NULL;
1199
1200 dcn31_panel_cntl_construct(panel_cntl, init_data);
1201
1202 return &panel_cntl->base;
1203 }
1204
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1205 static void read_dce_straps(
1206 struct dc_context *ctx,
1207 struct resource_straps *straps)
1208 {
1209 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1210 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1211
1212 }
1213
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1214 static struct audio *dcn31_create_audio(
1215 struct dc_context *ctx, unsigned int inst)
1216 {
1217
1218 #undef REG_STRUCT
1219 #define REG_STRUCT audio_regs
1220 audio_regs_init(0),
1221 audio_regs_init(1),
1222 audio_regs_init(2),
1223 audio_regs_init(3),
1224 audio_regs_init(4);
1225 audio_regs_init(5);
1226 audio_regs_init(6);
1227
1228 return dce_audio_create(ctx, inst,
1229 &audio_regs[inst], &audio_shift, &audio_mask);
1230 }
1231
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1232 static struct vpg *dcn31_vpg_create(
1233 struct dc_context *ctx,
1234 uint32_t inst)
1235 {
1236 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1237
1238 if (!vpg31)
1239 return NULL;
1240
1241 #undef REG_STRUCT
1242 #define REG_STRUCT vpg_regs
1243 vpg_regs_init(0),
1244 vpg_regs_init(1),
1245 vpg_regs_init(2),
1246 vpg_regs_init(3),
1247 vpg_regs_init(4),
1248 vpg_regs_init(5),
1249 vpg_regs_init(6),
1250 vpg_regs_init(7),
1251 vpg_regs_init(8),
1252 vpg_regs_init(9);
1253
1254 vpg31_construct(vpg31, ctx, inst,
1255 &vpg_regs[inst],
1256 &vpg_shift,
1257 &vpg_mask);
1258
1259 return &vpg31->base;
1260 }
1261
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1262 static struct afmt *dcn31_afmt_create(
1263 struct dc_context *ctx,
1264 uint32_t inst)
1265 {
1266 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1267
1268 if (!afmt31)
1269 return NULL;
1270
1271 #undef REG_STRUCT
1272 #define REG_STRUCT afmt_regs
1273 afmt_regs_init(0),
1274 afmt_regs_init(1),
1275 afmt_regs_init(2),
1276 afmt_regs_init(3),
1277 afmt_regs_init(4),
1278 afmt_regs_init(5);
1279
1280 afmt31_construct(afmt31, ctx, inst,
1281 &afmt_regs[inst],
1282 &afmt_shift,
1283 &afmt_mask);
1284
1285 // Light sleep by default, no need to power down here
1286
1287 return &afmt31->base;
1288 }
1289
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1290 static struct apg *dcn31_apg_create(
1291 struct dc_context *ctx,
1292 uint32_t inst)
1293 {
1294 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1295
1296 if (!apg31)
1297 return NULL;
1298
1299 #undef REG_STRUCT
1300 #define REG_STRUCT apg_regs
1301 apg_regs_init(0),
1302 apg_regs_init(1),
1303 apg_regs_init(2),
1304 apg_regs_init(3);
1305
1306 apg31_construct(apg31, ctx, inst,
1307 &apg_regs[inst],
1308 &apg_shift,
1309 &apg_mask);
1310
1311 return &apg31->base;
1312 }
1313
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1314 static struct stream_encoder *dcn35_stream_encoder_create(
1315 enum engine_id eng_id,
1316 struct dc_context *ctx)
1317 {
1318 struct dcn10_stream_encoder *enc1;
1319 struct vpg *vpg;
1320 struct afmt *afmt;
1321 int vpg_inst;
1322 int afmt_inst;
1323
1324 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1325 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1326 return NULL;
1327
1328 vpg_inst = eng_id;
1329 afmt_inst = eng_id;
1330
1331 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1332 vpg = dcn31_vpg_create(ctx, vpg_inst);
1333 afmt = dcn31_afmt_create(ctx, afmt_inst);
1334
1335 if (!enc1 || !vpg || !afmt) {
1336 kfree(enc1);
1337 kfree(vpg);
1338 kfree(afmt);
1339 return NULL;
1340 }
1341
1342 #undef REG_STRUCT
1343 #define REG_STRUCT stream_enc_regs
1344 stream_enc_regs_init(0),
1345 stream_enc_regs_init(1),
1346 stream_enc_regs_init(2),
1347 stream_enc_regs_init(3),
1348 stream_enc_regs_init(4);
1349
1350 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1351 eng_id, vpg, afmt,
1352 &stream_enc_regs[eng_id],
1353 &se_shift, &se_mask);
1354
1355 return &enc1->base;
1356 }
1357
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1358 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(
1359 enum engine_id eng_id,
1360 struct dc_context *ctx)
1361 {
1362 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1363 struct vpg *vpg;
1364 struct afmt *afmt;
1365 int vpg_inst;
1366 int afmt_inst;
1367
1368 #undef REG_STRUCT
1369 #define REG_STRUCT hpo_frl_stream_enc_regs
1370 hpo_frl_stream_encoder_reg_list(0),
1371 hpo_frl_stream_encoder_dme_reg_list(6);
1372
1373 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1374 if (eng_id == ENGINE_ID_HPO_0) {
1375 vpg_inst = 5;
1376 afmt_inst = 5;
1377 } else
1378 return NULL;
1379
1380 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1381 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1382 vpg = dcn31_vpg_create(ctx, vpg_inst);
1383 afmt = dcn31_afmt_create(ctx, afmt_inst);
1384
1385 if (!hpo_enc3 || !vpg || !afmt) {
1386 kfree(hpo_enc3);
1387 kfree(vpg);
1388 kfree(afmt);
1389 return NULL;
1390 }
1391
1392 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios,
1393 eng_id, vpg, afmt,
1394 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0],
1395 &hpo_se_shift, &hpo_se_mask);
1396
1397 return &hpo_enc3->base;
1398 }
1399
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1400 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(
1401 enum engine_id eng_id,
1402 struct dc_context *ctx)
1403 {
1404 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1405
1406 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1407
1408 #undef REG_STRUCT
1409 #define REG_STRUCT hpo_frl_link_enc_regs
1410 hpo_frl_link_encoder_reg_list(0);
1411
1412 /* allocate HPO link encoder */
1413 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1414 if (!hpo_enc3)
1415 return NULL; /* out of memory */
1416
1417 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0,
1418 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0],
1419 &hpo_le_shift, &hpo_le_mask);
1420
1421 return &hpo_enc3->base;
1422 }
1423
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1424 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1425 enum engine_id eng_id,
1426 struct dc_context *ctx)
1427 {
1428 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1429 struct vpg *vpg;
1430 struct apg *apg;
1431 uint32_t hpo_dp_inst;
1432 uint32_t vpg_inst;
1433 uint32_t apg_inst;
1434
1435 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1436 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1437
1438 /* Mapping of VPG register blocks to HPO DP block instance:
1439 * VPG[6] -> HPO_DP[0]
1440 * VPG[7] -> HPO_DP[1]
1441 * VPG[8] -> HPO_DP[2]
1442 * VPG[9] -> HPO_DP[3]
1443 */
1444 vpg_inst = hpo_dp_inst + 6;
1445
1446 /* Mapping of APG register blocks to HPO DP block instance:
1447 * APG[0] -> HPO_DP[0]
1448 * APG[1] -> HPO_DP[1]
1449 * APG[2] -> HPO_DP[2]
1450 * APG[3] -> HPO_DP[3]
1451 */
1452 apg_inst = hpo_dp_inst;
1453
1454 /* allocate HPO stream encoder and create VPG sub-block */
1455 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1456 vpg = dcn31_vpg_create(ctx, vpg_inst);
1457 apg = dcn31_apg_create(ctx, apg_inst);
1458
1459 if (!hpo_dp_enc31 || !vpg || !apg) {
1460 kfree(hpo_dp_enc31);
1461 kfree(vpg);
1462 kfree(apg);
1463 return NULL;
1464 }
1465
1466 #undef REG_STRUCT
1467 #define REG_STRUCT hpo_dp_stream_enc_regs
1468 hpo_dp_stream_encoder_reg_init(0),
1469 hpo_dp_stream_encoder_reg_init(1),
1470 hpo_dp_stream_encoder_reg_init(2),
1471 hpo_dp_stream_encoder_reg_init(3);
1472
1473 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1474 hpo_dp_inst, eng_id, vpg, apg,
1475 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1476 &hpo_dp_se_shift, &hpo_dp_se_mask);
1477
1478 return &hpo_dp_enc31->base;
1479 }
1480
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1481 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1482 uint8_t inst,
1483 struct dc_context *ctx)
1484 {
1485 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1486
1487 /* allocate HPO link encoder */
1488 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1489 if (!hpo_dp_enc31)
1490 return NULL; /* out of memory */
1491
1492 #undef REG_STRUCT
1493 #define REG_STRUCT hpo_dp_link_enc_regs
1494 hpo_dp_link_encoder_reg_init(0),
1495 hpo_dp_link_encoder_reg_init(1);
1496
1497 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1498 &hpo_dp_link_enc_regs[inst],
1499 &hpo_dp_le_shift, &hpo_dp_le_mask);
1500
1501 return &hpo_dp_enc31->base;
1502 }
1503
dcn351_hwseq_create(struct dc_context * ctx)1504 static struct dce_hwseq *dcn351_hwseq_create(
1505 struct dc_context *ctx)
1506 {
1507 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1508
1509 #undef REG_STRUCT
1510 #define REG_STRUCT hwseq_reg
1511 hwseq_reg_init();
1512
1513 if (hws) {
1514 hws->ctx = ctx;
1515 hws->regs = &hwseq_reg;
1516 hws->shifts = &hwseq_shift;
1517 hws->masks = &hwseq_mask;
1518 }
1519 return hws;
1520 }
1521 static const struct resource_create_funcs res_create_funcs = {
1522 .read_dce_straps = read_dce_straps,
1523 .create_audio = dcn31_create_audio,
1524 .create_stream_encoder = dcn35_stream_encoder_create,
1525 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1526 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1527 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1528 .create_hwseq = dcn351_hwseq_create,
1529 };
1530
dcn351_resource_destruct(struct dcn351_resource_pool * pool)1531 static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1532 {
1533 unsigned int i;
1534
1535 for (i = 0; i < pool->base.stream_enc_count; i++) {
1536 if (pool->base.stream_enc[i] != NULL) {
1537 if (pool->base.stream_enc[i]->vpg != NULL) {
1538 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1539 pool->base.stream_enc[i]->vpg = NULL;
1540 }
1541 if (pool->base.stream_enc[i]->afmt != NULL) {
1542 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1543 pool->base.stream_enc[i]->afmt = NULL;
1544 }
1545 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1546 pool->base.stream_enc[i] = NULL;
1547 }
1548 }
1549
1550 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1551 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1552 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1553 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1554 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1555 }
1556 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1557 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1558 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1559 }
1560 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1561 pool->base.hpo_frl_stream_enc[i] = NULL;
1562 }
1563 }
1564
1565 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1566 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1567 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1568 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1569 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1570 }
1571 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1572 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1573 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1574 }
1575 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1576 pool->base.hpo_dp_stream_enc[i] = NULL;
1577 }
1578 }
1579
1580 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1581 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1582 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1583 pool->base.hpo_dp_link_enc[i] = NULL;
1584 }
1585 }
1586
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1588 if (pool->base.dscs[i] != NULL)
1589 dcn20_dsc_destroy(&pool->base.dscs[i]);
1590 }
1591
1592 if (pool->base.mpc != NULL) {
1593 kfree(TO_DCN20_MPC(pool->base.mpc));
1594 pool->base.mpc = NULL;
1595 }
1596 if (pool->base.hubbub != NULL) {
1597 kfree(pool->base.hubbub);
1598 pool->base.hubbub = NULL;
1599 }
1600 for (i = 0; i < pool->base.pipe_count; i++) {
1601 if (pool->base.dpps[i] != NULL)
1602 dcn35_dpp_destroy(&pool->base.dpps[i]);
1603
1604 if (pool->base.ipps[i] != NULL)
1605 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1606
1607 if (pool->base.hubps[i] != NULL) {
1608 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1609 pool->base.hubps[i] = NULL;
1610 }
1611
1612 if (pool->base.irqs != NULL) {
1613 dal_irq_service_destroy(&pool->base.irqs);
1614 }
1615 }
1616
1617 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1618 if (pool->base.engines[i] != NULL)
1619 dce110_engine_destroy(&pool->base.engines[i]);
1620 if (pool->base.hw_i2cs[i] != NULL) {
1621 kfree(pool->base.hw_i2cs[i]);
1622 pool->base.hw_i2cs[i] = NULL;
1623 }
1624 if (pool->base.sw_i2cs[i] != NULL) {
1625 kfree(pool->base.sw_i2cs[i]);
1626 pool->base.sw_i2cs[i] = NULL;
1627 }
1628 }
1629
1630 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1631 if (pool->base.opps[i] != NULL)
1632 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1633 }
1634
1635 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1636 if (pool->base.timing_generators[i] != NULL) {
1637 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1638 pool->base.timing_generators[i] = NULL;
1639 }
1640 }
1641
1642 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1643 if (pool->base.dwbc[i] != NULL) {
1644 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1645 pool->base.dwbc[i] = NULL;
1646 }
1647 if (pool->base.mcif_wb[i] != NULL) {
1648 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1649 pool->base.mcif_wb[i] = NULL;
1650 }
1651 }
1652
1653 for (i = 0; i < pool->base.audio_count; i++) {
1654 if (pool->base.audios[i])
1655 dce_aud_destroy(&pool->base.audios[i]);
1656 }
1657
1658 for (i = 0; i < pool->base.clk_src_count; i++) {
1659 if (pool->base.clock_sources[i] != NULL) {
1660 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1661 pool->base.clock_sources[i] = NULL;
1662 }
1663 }
1664
1665 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1666 if (pool->base.mpc_lut[i] != NULL) {
1667 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1668 pool->base.mpc_lut[i] = NULL;
1669 }
1670 if (pool->base.mpc_shaper[i] != NULL) {
1671 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1672 pool->base.mpc_shaper[i] = NULL;
1673 }
1674 }
1675
1676 if (pool->base.dp_clock_source != NULL) {
1677 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1678 pool->base.dp_clock_source = NULL;
1679 }
1680
1681 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1682 if (pool->base.multiple_abms[i] != NULL)
1683 dce_abm_destroy(&pool->base.multiple_abms[i]);
1684 }
1685
1686 if (pool->base.psr != NULL)
1687 dmub_psr_destroy(&pool->base.psr);
1688
1689 if (pool->base.replay != NULL)
1690 dmub_replay_destroy(&pool->base.replay);
1691
1692 if (pool->base.pg_cntl != NULL)
1693 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1694
1695 if (pool->base.dccg != NULL)
1696 dcn_dccg_destroy(&pool->base.dccg);
1697
1698 if (pool->base.dio != NULL) {
1699 kfree(TO_DCN10_DIO(pool->base.dio));
1700 pool->base.dio = NULL;
1701 }
1702 }
1703
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1704 static struct hubp *dcn35_hubp_create(
1705 struct dc_context *ctx,
1706 uint32_t inst)
1707 {
1708 struct dcn20_hubp *hubp2 =
1709 kzalloc_obj(struct dcn20_hubp);
1710
1711 if (!hubp2)
1712 return NULL;
1713
1714 #undef REG_STRUCT
1715 #define REG_STRUCT hubp_regs
1716 hubp_regs_init(0),
1717 hubp_regs_init(1),
1718 hubp_regs_init(2),
1719 hubp_regs_init(3);
1720
1721 if (hubp35_construct(hubp2, ctx, inst,
1722 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1723 return &hubp2->base;
1724
1725 BREAK_TO_DEBUGGER();
1726 kfree(hubp2);
1727 return NULL;
1728 }
1729
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1730 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1731 {
1732 dcn35_dwbc_set_fgcg(
1733 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1734 }
1735
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1736 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1737 {
1738 unsigned int i;
1739 uint32_t pipe_count = pool->res_cap->num_dwb;
1740
1741 for (i = 0; i < pipe_count; i++) {
1742 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1743
1744 if (!dwbc30) {
1745 dm_error("DC: failed to create dwbc30!\n");
1746 return false;
1747 }
1748
1749 #undef REG_STRUCT
1750 #define REG_STRUCT dwbc35_regs
1751 dwbc_regs_dcn3_init(0);
1752
1753 dcn35_dwbc_construct(dwbc30, ctx,
1754 &dwbc35_regs[i],
1755 &dwbc35_shift,
1756 &dwbc35_mask,
1757 i);
1758
1759 pool->dwbc[i] = &dwbc30->base;
1760
1761 dcn35_dwbc_init(dwbc30, ctx);
1762 }
1763 return true;
1764 }
1765
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1766 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1767 struct dc_context *ctx)
1768 {
1769 dcn35_mmhubbub_set_fgcg(
1770 mcif_wb30,
1771 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1772 }
1773
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1774 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1775 {
1776 unsigned int i;
1777 uint32_t pipe_count = pool->res_cap->num_dwb;
1778
1779 for (i = 0; i < pipe_count; i++) {
1780 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1781
1782 if (!mcif_wb30) {
1783 dm_error("DC: failed to create mcif_wb30!\n");
1784 return false;
1785 }
1786
1787 #undef REG_STRUCT
1788 #define REG_STRUCT mcif_wb35_regs
1789 mcif_wb_regs_dcn3_init(0);
1790
1791 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1792 &mcif_wb35_regs[i],
1793 &mcif_wb35_shift,
1794 &mcif_wb35_mask,
1795 i);
1796
1797 dcn35_mmhubbub_init(mcif_wb30, ctx);
1798
1799 pool->mcif_wb[i] = &mcif_wb30->base;
1800 }
1801 return true;
1802 }
1803
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1804 static struct display_stream_compressor *dcn35_dsc_create(
1805 struct dc_context *ctx, uint32_t inst)
1806 {
1807 struct dcn20_dsc *dsc =
1808 kzalloc_obj(struct dcn20_dsc);
1809
1810 if (!dsc) {
1811 BREAK_TO_DEBUGGER();
1812 return NULL;
1813 }
1814
1815 #undef REG_STRUCT
1816 #define REG_STRUCT dsc_regs
1817 dsc_regsDCN35_init(0),
1818 dsc_regsDCN35_init(1),
1819 dsc_regsDCN35_init(2),
1820 dsc_regsDCN35_init(3);
1821
1822 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1823 dsc35_set_fgcg(dsc,
1824 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1825 return &dsc->base;
1826 }
1827
dcn351_destroy_resource_pool(struct resource_pool ** pool)1828 static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1829 {
1830 struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1831
1832 dcn351_resource_destruct(dcn351_pool);
1833 kfree(dcn351_pool);
1834 *pool = NULL;
1835 }
1836
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1837 static struct clock_source *dcn35_clock_source_create(
1838 struct dc_context *ctx,
1839 struct dc_bios *bios,
1840 enum clock_source_id id,
1841 const struct dce110_clk_src_regs *regs,
1842 bool dp_clk_src)
1843 {
1844 struct dce110_clk_src *clk_src =
1845 kzalloc_obj(struct dce110_clk_src);
1846
1847 if (!clk_src)
1848 return NULL;
1849
1850 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1851 regs, &cs_shift, &cs_mask)) {
1852 clk_src->base.dp_clk_src = dp_clk_src;
1853 return &clk_src->base;
1854 }
1855
1856 kfree(clk_src);
1857 BREAK_TO_DEBUGGER();
1858 return NULL;
1859 }
1860
1861 static struct dc_cap_funcs cap_funcs = {
1862 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1863 };
1864
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1865 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1866 {
1867 *panel_config = panel_config_defaults;
1868 }
1869
1870
dcn351_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1871 static enum dc_status dcn351_validate_bandwidth(struct dc *dc,
1872 struct dc_state *context,
1873 enum dc_validate_mode validate_mode)
1874 {
1875 bool out = false;
1876
1877 DC_FP_START();
1878 out = dml2_validate(dc, context,
1879 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1880 validate_mode);
1881 DC_FP_END();
1882
1883 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1884 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1885
1886 DC_FP_START();
1887 dcn35_decide_zstate_support(dc, context);
1888 DC_FP_END();
1889
1890 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1891 }
1892
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1893 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1894 struct dc_state *context,
1895 display_e2e_pipe_params_st *pipes,
1896 enum dc_validate_mode validate_mode)
1897 {
1898 int ret;
1899
1900 DC_FP_START();
1901 ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1902 DC_FP_END();
1903
1904 return ret;
1905
1906 }
1907
dcn351_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1908 static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1909 {
1910 DC_FP_START();
1911 dcn351_update_bw_bounding_box_fpu(dc, bw_params);
1912 DC_FP_END();
1913 }
1914 static struct resource_funcs dcn351_res_pool_funcs = {
1915 .destroy = dcn351_destroy_resource_pool,
1916 .link_enc_create = dcn35_link_encoder_create,
1917 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1918 .link_encs_assign = link_enc_cfg_link_encs_assign,
1919 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1920 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1921 .panel_cntl_create = dcn31_panel_cntl_create,
1922 .validate_bandwidth = dcn351_validate_bandwidth,
1923 .calculate_wm_and_dlg = NULL,
1924 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1925 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1926 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1927 .release_pipe = dcn20_release_pipe,
1928 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1929 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1930 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1931 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1932 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1933 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1934 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1935 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1936 .update_bw_bounding_box = dcn351_update_bw_bounding_box,
1937 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1938 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1939 .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1940 .get_det_buffer_size = dcn31_get_det_buffer_size,
1941 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1942 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1943 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1944 .get_default_tiling_info = dcn10_get_default_tiling_info
1945 };
1946
dcn351_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn351_resource_pool * pool)1947 static bool dcn351_resource_construct(
1948 uint8_t num_virtual_links,
1949 struct dc *dc,
1950 struct dcn351_resource_pool *pool)
1951 {
1952 int i;
1953 struct dc_context *ctx = dc->ctx;
1954 struct irq_service_init_data init_data;
1955
1956 #undef REG_STRUCT
1957 #define REG_STRUCT bios_regs
1958 bios_regs_init();
1959
1960 #undef REG_STRUCT
1961 #define REG_STRUCT clk_src_regs
1962 clk_src_regs_init(0, A),
1963 clk_src_regs_init(1, B),
1964 clk_src_regs_init(2, C),
1965 clk_src_regs_init(3, D),
1966 clk_src_regs_init(4, E);
1967
1968 /* Enable 4to1MPC by default */
1969 dc->config.allow_4to1MPC = true;
1970
1971 #undef REG_STRUCT
1972 #define REG_STRUCT abm_regs
1973 abm_regs_init(0),
1974 abm_regs_init(1),
1975 abm_regs_init(2),
1976 abm_regs_init(3);
1977
1978 #undef REG_STRUCT
1979 #define REG_STRUCT dccg_regs
1980 dccg_regs_init();
1981
1982 ctx->dc_bios->regs = &bios_regs;
1983
1984 pool->base.res_cap = &res_cap_dcn351;
1985
1986 pool->base.funcs = &dcn351_res_pool_funcs;
1987
1988 /*************************************************
1989 * Resource + asic cap harcoding *
1990 *************************************************/
1991 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1992 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1993 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1994 dc->caps.max_downscale_ratio = 600;
1995 dc->caps.i2c_speed_in_khz = 100;
1996 dc->caps.i2c_speed_in_khz_hdcp = 100;
1997 dc->caps.max_cursor_size = 256;
1998 dc->caps.min_horizontal_blanking_period = 80;
1999 dc->caps.dmdata_alloc_size = 2048;
2000 dc->caps.max_slave_planes = 3;
2001 dc->caps.max_slave_yuv_planes = 3;
2002 dc->caps.max_slave_rgb_planes = 3;
2003 dc->caps.post_blend_color_processing = true;
2004 dc->caps.force_dp_tps4_for_cp2520 = true;
2005 if (dc->config.forceHBR2CP2520)
2006 dc->caps.force_dp_tps4_for_cp2520 = false;
2007 dc->caps.hdmi_hpo = true;
2008 dc->caps.dp_hpo = true;
2009 dc->caps.dp_hdmi21_pcon_support = true;
2010
2011 dc->caps.edp_dsc_support = true;
2012 dc->caps.extended_aux_timeout_support = true;
2013 dc->caps.dmcub_support = true;
2014 dc->caps.is_apu = true;
2015 dc->caps.seamless_odm = true;
2016
2017 dc->caps.zstate_support = true;
2018 dc->caps.ips_support = true;
2019 dc->caps.max_v_total = (1 << 15) - 1;
2020 dc->caps.vtotal_limited_by_fp2 = true;
2021
2022 /* Color pipeline capabilities */
2023 dc->caps.color.dpp.dcn_arch = 1;
2024 dc->caps.color.dpp.input_lut_shared = 0;
2025 dc->caps.color.dpp.icsc = 1;
2026 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2027 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2028 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2029 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2030 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2031 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2032 dc->caps.color.dpp.post_csc = 1;
2033 dc->caps.color.dpp.gamma_corr = 1;
2034 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2035 dc->caps.color.dpp.upsp_pre_scaler = 0;
2036
2037 dc->caps.color.dpp.hw_3d_lut = 0;
2038 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2039 // no OGAM ROM on DCN301
2040 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2041 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2042 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2043 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2044 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2045 dc->caps.color.dpp.ocsc = 0;
2046
2047 dc->caps.color.mpc.gamut_remap = 1;
2048 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
2049 dc->caps.color.mpc.ogam_ram = 1;
2050 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2051 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2052 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2053 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2054 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2055 dc->caps.color.mpc.ocsc = 1;
2056 dc->caps.color.mpc.preblend = true;
2057 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2058
2059 dc->caps.num_of_host_routers = 2;
2060 dc->caps.num_of_dpias_per_host_router = 2;
2061
2062 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
2063 * to provide some margin.
2064 * It's expected for furture ASIC to have equal or higher value, in order to
2065 * have determinstic power improvement from generate to genration.
2066 * (i.e., we should not expect new ASIC generation with lower vmin rate)
2067 */
2068 dc->caps.max_disp_clock_khz_at_vmin = 650000;
2069
2070 /* Use pipe context based otg sync logic */
2071 dc->config.use_pipe_ctx_sync_logic = true;
2072
2073
2074 /* Use psp mailbox to enable assr */
2075 dc->config.use_assr_psp_message = true;
2076
2077 /* read VBIOS LTTPR caps */
2078 {
2079 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2080 enum bp_result bp_query_result;
2081 uint8_t is_vbios_lttpr_enable = 0;
2082
2083 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2084 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2085 }
2086
2087 /* interop bit is implicit */
2088 {
2089 dc->caps.vbios_lttpr_aware = true;
2090 }
2091 }
2092 dc->check_config = config_defaults;
2093
2094 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2095 dc->debug = debug_defaults_drv;
2096
2097 /*HW default is to have all the FGCG enabled, SW no need to program them*/
2098 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
2099 // Init the vm_helper
2100 if (dc->vm_helper)
2101 vm_helper_init(dc->vm_helper, 16);
2102
2103 /*************************************************
2104 * Create resources *
2105 *************************************************/
2106
2107 /* Clock Sources for Pixel Clock*/
2108 pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
2109 dcn35_clock_source_create(ctx, ctx->dc_bios,
2110 CLOCK_SOURCE_COMBO_PHY_PLL0,
2111 &clk_src_regs[0], false);
2112 pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
2113 dcn35_clock_source_create(ctx, ctx->dc_bios,
2114 CLOCK_SOURCE_COMBO_PHY_PLL1,
2115 &clk_src_regs[1], false);
2116 pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
2117 dcn35_clock_source_create(ctx, ctx->dc_bios,
2118 CLOCK_SOURCE_COMBO_PHY_PLL2,
2119 &clk_src_regs[2], false);
2120 pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
2121 dcn35_clock_source_create(ctx, ctx->dc_bios,
2122 CLOCK_SOURCE_COMBO_PHY_PLL3,
2123 &clk_src_regs[3], false);
2124 pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
2125 dcn35_clock_source_create(ctx, ctx->dc_bios,
2126 CLOCK_SOURCE_COMBO_PHY_PLL4,
2127 &clk_src_regs[4], false);
2128
2129 pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
2130
2131 /* todo: not reuse phy_pll registers */
2132 pool->base.dp_clock_source =
2133 dcn35_clock_source_create(ctx, ctx->dc_bios,
2134 CLOCK_SOURCE_ID_DP_DTO,
2135 &clk_src_regs[0], true);
2136
2137 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2138 if (pool->base.clock_sources[i] == NULL) {
2139 dm_error("DC: failed to create clock sources!\n");
2140 BREAK_TO_DEBUGGER();
2141 goto create_fail;
2142 }
2143 }
2144 /*temp till dml2 fully work without dml1*/
2145 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2146
2147 /* TODO: DCCG */
2148 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2149 if (pool->base.dccg == NULL) {
2150 dm_error("DC: failed to create dccg!\n");
2151 BREAK_TO_DEBUGGER();
2152 goto create_fail;
2153 }
2154
2155 #undef REG_STRUCT
2156 #define REG_STRUCT pg_cntl_regs
2157 pg_cntl_dcn35_regs_init();
2158
2159 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2160 if (pool->base.pg_cntl == NULL) {
2161 dm_error("DC: failed to create power gate control!\n");
2162 BREAK_TO_DEBUGGER();
2163 goto create_fail;
2164 }
2165
2166 /* TODO: IRQ */
2167 init_data.ctx = dc->ctx;
2168 pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
2169 if (!pool->base.irqs)
2170 goto create_fail;
2171
2172 /* HUBBUB */
2173 pool->base.hubbub = dcn35_hubbub_create(ctx);
2174 if (pool->base.hubbub == NULL) {
2175 BREAK_TO_DEBUGGER();
2176 dm_error("DC: failed to create hubbub!\n");
2177 goto create_fail;
2178 }
2179
2180 /* DIO */
2181 pool->base.dio = dcn351_dio_create(ctx);
2182 if (pool->base.dio == NULL) {
2183 BREAK_TO_DEBUGGER();
2184 dm_error("DC: failed to create dio!\n");
2185 goto create_fail;
2186 }
2187
2188 /* HUBPs, DPPs, OPPs and TGs */
2189 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2190 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2191 if (pool->base.hubps[i] == NULL) {
2192 BREAK_TO_DEBUGGER();
2193 dm_error(
2194 "DC: failed to create hubps!\n");
2195 goto create_fail;
2196 }
2197
2198 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2199 if (pool->base.dpps[i] == NULL) {
2200 BREAK_TO_DEBUGGER();
2201 dm_error(
2202 "DC: failed to create dpps!\n");
2203 goto create_fail;
2204 }
2205 }
2206
2207 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2208 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2209 if (pool->base.opps[i] == NULL) {
2210 BREAK_TO_DEBUGGER();
2211 dm_error(
2212 "DC: failed to create output pixel processor!\n");
2213 goto create_fail;
2214 }
2215 }
2216
2217 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2218 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2219 ctx, i);
2220 if (pool->base.timing_generators[i] == NULL) {
2221 BREAK_TO_DEBUGGER();
2222 dm_error("DC: failed to create tg!\n");
2223 goto create_fail;
2224 }
2225 }
2226 pool->base.timing_generator_count = i;
2227
2228 /* PSR */
2229 pool->base.psr = dmub_psr_create(ctx);
2230 if (pool->base.psr == NULL) {
2231 dm_error("DC: failed to create psr obj!\n");
2232 BREAK_TO_DEBUGGER();
2233 goto create_fail;
2234 }
2235
2236 /* Replay */
2237 pool->base.replay = dmub_replay_create(ctx);
2238 if (pool->base.replay == NULL) {
2239 dm_error("DC: failed to create replay obj!\n");
2240 BREAK_TO_DEBUGGER();
2241 goto create_fail;
2242 }
2243
2244 /* ABM */
2245 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2246 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2247 &abm_regs[i],
2248 &abm_shift,
2249 &abm_mask);
2250 if (pool->base.multiple_abms[i] == NULL) {
2251 dm_error("DC: failed to create abm for pipe %d!\n", i);
2252 BREAK_TO_DEBUGGER();
2253 goto create_fail;
2254 }
2255 }
2256
2257 /* MPC and DSC */
2258 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2259 if (pool->base.mpc == NULL) {
2260 BREAK_TO_DEBUGGER();
2261 dm_error("DC: failed to create mpc!\n");
2262 goto create_fail;
2263 }
2264
2265 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2266 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2267 if (pool->base.dscs[i] == NULL) {
2268 BREAK_TO_DEBUGGER();
2269 dm_error("DC: failed to create display stream compressor %d!\n", i);
2270 goto create_fail;
2271 }
2272 }
2273
2274 /* DWB and MMHUBBUB */
2275 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2276 BREAK_TO_DEBUGGER();
2277 dm_error("DC: failed to create dwbc!\n");
2278 goto create_fail;
2279 }
2280
2281 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2282 BREAK_TO_DEBUGGER();
2283 dm_error("DC: failed to create mcif_wb!\n");
2284 goto create_fail;
2285 }
2286
2287 /* AUX and I2C */
2288 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2289 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2290 if (pool->base.engines[i] == NULL) {
2291 BREAK_TO_DEBUGGER();
2292 dm_error(
2293 "DC:failed to create aux engine!!\n");
2294 goto create_fail;
2295 }
2296 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2297 if (pool->base.hw_i2cs[i] == NULL) {
2298 BREAK_TO_DEBUGGER();
2299 dm_error(
2300 "DC:failed to create hw i2c!!\n");
2301 goto create_fail;
2302 }
2303 pool->base.sw_i2cs[i] = NULL;
2304 }
2305
2306 /* DCN3.5 has 6 DPIA */
2307 pool->base.usb4_dpia_count = 4;
2308 if (dc->debug.dpia_debug.bits.disable_dpia)
2309 pool->base.usb4_dpia_count = 0;
2310
2311 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2312 if (!resource_construct(num_virtual_links, dc, &pool->base,
2313 &res_create_funcs))
2314 goto create_fail;
2315
2316 /* HW Sequencer and Plane caps */
2317 dcn351_hw_sequencer_construct(dc);
2318
2319 dc->caps.max_planes = pool->base.pipe_count;
2320
2321 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2322 dc->caps.planes[i] = plane_cap;
2323
2324 dc->caps.max_odm_combine_factor = 4;
2325
2326 dc->cap_funcs = cap_funcs;
2327
2328
2329 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2330
2331 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2332 dc->dml2_options.use_native_soc_bb_construction = true;
2333 dc->dml2_options.minimize_dispclk_using_odm = false;
2334 if (dc->config.EnableMinDispClkODM)
2335 dc->dml2_options.minimize_dispclk_using_odm = true;
2336 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2337
2338 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2339 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2340
2341 dc->dml2_options.max_segments_per_hubp = 24;
2342 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2343 dc->dml2_options.override_det_buffer_size_kbytes = true;
2344
2345 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2346 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2347
2348 return true;
2349
2350 create_fail:
2351
2352 dcn351_resource_destruct(pool);
2353
2354 return false;
2355 }
2356
dcn351_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2357 struct resource_pool *dcn351_create_resource_pool(
2358 const struct dc_init_data *init_data,
2359 struct dc *dc)
2360 {
2361 struct dcn351_resource_pool *pool =
2362 kzalloc_obj(struct dcn351_resource_pool);
2363
2364 if (!pool)
2365 return NULL;
2366
2367 if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2368 return &pool->base;
2369
2370 BREAK_TO_DEBUGGER();
2371 kfree(pool);
2372 return NULL;
2373 }
2374