1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dc_types.h"
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn32/dcn32_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "basics/conversion.h"
36 #include "dcn32_resource.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn32/dcn32_hubbub.h"
45 #include "dcn32/dcn32_mpc.h"
46 #include "dcn32/dcn32_hubp.h"
47 #include "irq/dcn32/irq_service_dcn32.h"
48 #include "dcn32/dcn32_dpp.h"
49 #include "dcn32/dcn32_optc.h"
50 #include "dcn20/dcn20_hwseq.h"
51 #include "dcn30/dcn30_hwseq.h"
52 #include "dce110/dce110_hwseq.h"
53 #include "dcn30/dcn30_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn30/dcn30_vpg.h"
56 #include "dcn30/dcn30_afmt.h"
57 #include "dcn30/dcn30_dio_stream_encoder.h"
58 #include "dcn32/dcn32_dio_stream_encoder.h"
59 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
60 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
62 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
63 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
64 #include "dcn31/dcn31_apg.h"
65 #include "dcn31/dcn31_dio_link_encoder.h"
66 #include "dcn32/dcn32_dio_link_encoder.h"
67 #include "dce/dce_clock_source.h"
68 #include "dce/dce_audio.h"
69 #include "dce/dce_hwseq.h"
70 #include "clk_mgr.h"
71 #include "dio/virtual/virtual_stream_encoder.h"
72 #include "dio/dcn10/dcn10_dio.h"
73 #include "dml/display_mode_vba.h"
74 #include "dcn32/dcn32_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "link_service.h"
77 #include "dcn31/dcn31_panel_cntl.h"
78
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn32/dcn32_mmhubbub.h"
81
82 #include "dcn/dcn_3_2_0_offset.h"
83 #include "dcn/dcn_3_2_0_sh_mask.h"
84 #include "nbio/nbio_4_3_0_offset.h"
85
86 #include "reg_helper.h"
87 #include "dce/dmub_abm.h"
88 #include "dce/dmub_psr.h"
89 #include "dce/dce_aux.h"
90 #include "dce/dce_i2c.h"
91
92 #include "dml/dcn30/display_mode_vba_30.h"
93 #include "vm_helper.h"
94 #include "dcn20/dcn20_vmid.h"
95 #include "dml/dcn32/dcn32_fpu.h"
96
97 #include "dc_state_priv.h"
98 #include "dc_fpu.h"
99
100 #include "dml2_0/dml2_wrapper.h"
101
102 #if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
103 #define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
104 #endif
105
106 #define DC_LOGGER_INIT(logger)
107
108 enum dcn32_clk_src_array_id {
109 DCN32_CLK_SRC_PLL0,
110 DCN32_CLK_SRC_PLL1,
111 DCN32_CLK_SRC_PLL2,
112 DCN32_CLK_SRC_PLL3,
113 DCN32_CLK_SRC_PLL4,
114 DCN32_CLK_SRC_TOTAL
115 };
116
117 /* begin *********************
118 * macros to expend register list macro defined in HW object header file
119 */
120
121 /* DCN */
122 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
123
124 #define BASE(seg) BASE_INNER(seg)
125
126 #define SR(reg_name)\
127 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
128 reg ## reg_name
129 #define SR_ARR(reg_name, id) \
130 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
131
132 #define SR_ARR_INIT(reg_name, id, value) \
133 REG_STRUCT[id].reg_name = value
134
135 #define SRI(reg_name, block, id)\
136 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 reg ## block ## id ## _ ## reg_name
138
139 #define SRI_ARR(reg_name, block, id)\
140 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 reg ## block ## id ## _ ## reg_name
142
143 #define SR_ARR_I2C(reg_name, id) \
144 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
145
146 #define SRI_ARR_I2C(reg_name, block, id)\
147 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
148 reg ## block ## id ## _ ## reg_name
149
150 #define SRI_ARR_DME(reg_name, block, id, offset)\
151 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 reg ## block ## id ## _ ## reg_name
153
154 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
155 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
156 reg ## block ## id ## _ ## reg_name
157
158 #define SRI2(reg_name, block, id)\
159 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
160 reg ## reg_name
161 #define SRI2_ARR(reg_name, block, id)\
162 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
163 reg ## reg_name
164
165 #define SRIR(var_name, reg_name, block, id)\
166 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
168
169 #define SRII(reg_name, block, id)\
170 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## reg_name
172
173 #define SRII_ARR_2(reg_name, block, id, inst)\
174 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## reg_name
176
177 #define SRII_MPC_RMU(reg_name, block, id)\
178 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## reg_name
180
181 #define SRII_DWB(reg_name, temp_name, block, id)\
182 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
183 reg ## block ## id ## _ ## temp_name
184
185 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
186 .field_name = reg_name ## __ ## field_name ## post_fix
187
188 #define DCCG_SRII(reg_name, block, id)\
189 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 reg ## block ## id ## _ ## reg_name
191
192 #define VUPDATE_SRII(reg_name, block, id)\
193 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
194 reg ## reg_name ## _ ## block ## id
195
196 /* NBIO */
197 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
198
199 #define NBIO_BASE(seg) \
200 NBIO_BASE_INNER(seg)
201
202 #define NBIO_SR(reg_name)\
203 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
204 regBIF_BX0_ ## reg_name
205 #define NBIO_SR_ARR(reg_name, id)\
206 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
207 regBIF_BX0_ ## reg_name
208
209 #undef CTX
210 #define CTX ctx
211 #define REG(reg_name) \
212 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
213
214 static struct bios_registers bios_regs;
215
216 #define bios_regs_init() \
217 ( \
218 NBIO_SR(BIOS_SCRATCH_3),\
219 NBIO_SR(BIOS_SCRATCH_6)\
220 )
221
222 #define clk_src_regs_init(index, pllid)\
223 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
224
225 static struct dce110_clk_src_regs clk_src_regs[5];
226
227 static const struct dce110_clk_src_shift cs_shift = {
228 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
229 };
230
231 static const struct dce110_clk_src_mask cs_mask = {
232 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
233 };
234
235 #define abm_regs_init(id)\
236 ABM_DCN32_REG_LIST_RI(id)
237
238 static struct dce_abm_registers abm_regs[4];
239
240 static const struct dce_abm_shift abm_shift = {
241 ABM_MASK_SH_LIST_DCN32(__SHIFT)
242 };
243
244 static const struct dce_abm_mask abm_mask = {
245 ABM_MASK_SH_LIST_DCN32(_MASK)
246 };
247
248 #define audio_regs_init(id)\
249 AUD_COMMON_REG_LIST_RI(id)
250
251 static struct dce_audio_registers audio_regs[5];
252
253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
257
258 static const struct dce_audio_shift audio_shift = {
259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
260 };
261
262 static const struct dce_audio_mask audio_mask = {
263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
264 };
265
266 #define vpg_regs_init(id)\
267 VPG_DCN3_REG_LIST_RI(id)
268
269 static struct dcn30_vpg_registers vpg_regs[10];
270
271 static const struct dcn30_vpg_shift vpg_shift = {
272 DCN3_VPG_MASK_SH_LIST(__SHIFT)
273 };
274
275 static const struct dcn30_vpg_mask vpg_mask = {
276 DCN3_VPG_MASK_SH_LIST(_MASK)
277 };
278
279 #define afmt_regs_init(id)\
280 AFMT_DCN3_REG_LIST_RI(id)
281
282 static struct dcn30_afmt_registers afmt_regs[6];
283
284 static const struct dcn30_afmt_shift afmt_shift = {
285 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dcn30_afmt_mask afmt_mask = {
289 DCN3_AFMT_MASK_SH_LIST(_MASK)
290 };
291
292 #define apg_regs_init(id)\
293 APG_DCN31_REG_LIST_RI(id)
294
295 static struct dcn31_apg_registers apg_regs[4];
296
297 static const struct dcn31_apg_shift apg_shift = {
298 DCN31_APG_MASK_SH_LIST(__SHIFT)
299 };
300
301 static const struct dcn31_apg_mask apg_mask = {
302 DCN31_APG_MASK_SH_LIST(_MASK)
303 };
304
305 #define stream_enc_regs_init(id)\
306 SE_DCN32_REG_LIST_RI(id)
307
308 static struct dcn10_stream_enc_registers stream_enc_regs[5];
309
310 static const struct dcn10_stream_encoder_shift se_shift = {
311 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
312 };
313
314 static const struct dcn10_stream_encoder_mask se_mask = {
315 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
316 };
317
318
319 #define aux_regs_init(id)\
320 DCN2_AUX_REG_LIST_RI(id)
321
322 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
323
324 #define hpd_regs_init(id)\
325 HPD_REG_LIST_RI(id)
326
327 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
328
329 #define link_regs_init(id, phyid)\
330 ( \
331 LE_DCN31_REG_LIST_RI(id), \
332 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
333 )
334 /*DPCS_DCN31_REG_LIST(id),*/ \
335
336 static struct dcn10_link_enc_registers link_enc_regs[5];
337
338 static const struct dcn10_link_enc_shift le_shift = {
339 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
340 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dcn10_link_enc_mask le_mask = {
344 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
345 //DPCS_DCN31_MASK_SH_LIST(_MASK)
346 };
347
348 #define hpo_frl_stream_encoder_reg_list(id)\
349 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
350
351 #define hpo_frl_stream_encoder_dme_reg_list(id)\
352 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6)
353
354
355 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
356
357 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
358 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
362 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
363 };
364
365 #define hpo_frl_link_encoder_reg_list(id)\
366 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
367
368 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
369
370 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
371 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
372 };
373
374 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
375 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
376 };
377
378 #define hpo_dp_stream_encoder_reg_init(id)\
379 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
380
381 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
382
383 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
384 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
385 };
386
387 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
388 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
389 };
390
391
392 #define hpo_dp_link_encoder_reg_init(id)\
393 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
394 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
395 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
396 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
397 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
398
399 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
400
401 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
402 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
403 };
404
405 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
406 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
407 };
408
409 #define dpp_regs_init(id)\
410 DPP_REG_LIST_DCN30_COMMON_RI(id)
411
412 static struct dcn3_dpp_registers dpp_regs[4];
413
414 static const struct dcn3_dpp_shift tf_shift = {
415 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
416 };
417
418 static const struct dcn3_dpp_mask tf_mask = {
419 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
420 };
421
422
423 #define opp_regs_init(id)\
424 OPP_REG_LIST_DCN30_RI(id)
425
426 static struct dcn20_opp_registers opp_regs[4];
427
428 static const struct dcn20_opp_shift opp_shift = {
429 OPP_MASK_SH_LIST_DCN20(__SHIFT)
430 };
431
432 static const struct dcn20_opp_mask opp_mask = {
433 OPP_MASK_SH_LIST_DCN20(_MASK)
434 };
435
436 #define aux_engine_regs_init(id)\
437 ( \
438 AUX_COMMON_REG_LIST0_RI(id), \
439 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
440 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
441 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
442 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
443 )
444
445 static struct dce110_aux_registers aux_engine_regs[5];
446
447 static const struct dce110_aux_registers_shift aux_shift = {
448 DCN_AUX_MASK_SH_LIST(__SHIFT)
449 };
450
451 static const struct dce110_aux_registers_mask aux_mask = {
452 DCN_AUX_MASK_SH_LIST(_MASK)
453 };
454
455 #define dwbc_regs_dcn3_init(id)\
456 DWBC_COMMON_REG_LIST_DCN30_RI(id)
457
458 static struct dcn30_dwbc_registers dwbc30_regs[1];
459
460 static const struct dcn30_dwbc_shift dwbc30_shift = {
461 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
462 };
463
464 static const struct dcn30_dwbc_mask dwbc30_mask = {
465 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
466 };
467
468 #define mcif_wb_regs_dcn3_init(id)\
469 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
470
471 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
472
473 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
474 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
475 };
476
477 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
478 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
479 };
480
481 #define dsc_regsDCN20_init(id)\
482 DSC_REG_LIST_DCN20_RI(id)
483
484 static struct dcn20_dsc_registers dsc_regs[4];
485
486 static const struct dcn20_dsc_shift dsc_shift = {
487 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
488 };
489
490 static const struct dcn20_dsc_mask dsc_mask = {
491 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
492 };
493
494 static struct dcn30_mpc_registers mpc_regs;
495
496 #define dcn_mpc_regs_init() \
497 MPC_REG_LIST_DCN3_2_RI(0),\
498 MPC_REG_LIST_DCN3_2_RI(1),\
499 MPC_REG_LIST_DCN3_2_RI(2),\
500 MPC_REG_LIST_DCN3_2_RI(3),\
501 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
502 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
503 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
504 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
505 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
506
507 static const struct dcn30_mpc_shift mpc_shift = {
508 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
509 };
510
511 static const struct dcn30_mpc_mask mpc_mask = {
512 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
513 };
514
515 #define optc_regs_init(id)\
516 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
517
518 static struct dcn_optc_registers optc_regs[4];
519
520 static const struct dcn_optc_shift optc_shift = {
521 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
522 };
523
524 static const struct dcn_optc_mask optc_mask = {
525 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
526 };
527
528 #define hubp_regs_init(id)\
529 HUBP_REG_LIST_DCN32_RI(id)
530
531 static struct dcn_hubp2_registers hubp_regs[4];
532
533
534 static const struct dcn_hubp2_shift hubp_shift = {
535 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
536 };
537
538 static const struct dcn_hubp2_mask hubp_mask = {
539 HUBP_MASK_SH_LIST_DCN32(_MASK)
540 };
541
542 static struct dcn_hubbub_registers hubbub_reg;
543 #define hubbub_reg_init()\
544 HUBBUB_REG_LIST_DCN32_RI(0)
545
546 static const struct dcn_hubbub_shift hubbub_shift = {
547 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
548 };
549
550 static const struct dcn_hubbub_mask hubbub_mask = {
551 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
552 };
553
554 static struct dccg_registers dccg_regs;
555
556 #define dccg_regs_init()\
557 DCCG_REG_LIST_DCN32_RI()
558
559 static const struct dccg_shift dccg_shift = {
560 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
561 };
562
563 static const struct dccg_mask dccg_mask = {
564 DCCG_MASK_SH_LIST_DCN32(_MASK)
565 };
566
567
568 #define SRII2(reg_name_pre, reg_name_post, id)\
569 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
570 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
571 reg ## reg_name_pre ## id ## _ ## reg_name_post
572
573
574 #define HWSEQ_DCN32_REG_LIST()\
575 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
576 SR(DIO_MEM_PWR_CTRL), \
577 SR(ODM_MEM_PWR_CTRL3), \
578 SR(MMHUBBUB_MEM_PWR_CNTL), \
579 SR(DCCG_GATE_DISABLE_CNTL), \
580 SR(DCCG_GATE_DISABLE_CNTL2), \
581 SR(DCFCLK_CNTL),\
582 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
583 SRII(PIXEL_RATE_CNTL, OTG, 0), \
584 SRII(PIXEL_RATE_CNTL, OTG, 1),\
585 SRII(PIXEL_RATE_CNTL, OTG, 2),\
586 SRII(PIXEL_RATE_CNTL, OTG, 3),\
587 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
588 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
589 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
590 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
591 SR(MICROSECOND_TIME_BASE_DIV), \
592 SR(MILLISECOND_TIME_BASE_DIV), \
593 SR(DISPCLK_FREQ_CHANGE_CNTL), \
594 SR(RBBMIF_TIMEOUT_DIS), \
595 SR(RBBMIF_TIMEOUT_DIS_2), \
596 SR(DCHUBBUB_CRC_CTRL), \
597 SR(DPP_TOP0_DPP_CRC_CTRL), \
598 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
599 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
600 SR(MPC_CRC_CTRL), \
601 SR(MPC_CRC_RESULT_GB), \
602 SR(MPC_CRC_RESULT_C), \
603 SR(MPC_CRC_RESULT_AR), \
604 SR(DOMAIN0_PG_CONFIG), \
605 SR(DOMAIN1_PG_CONFIG), \
606 SR(DOMAIN2_PG_CONFIG), \
607 SR(DOMAIN3_PG_CONFIG), \
608 SR(DOMAIN16_PG_CONFIG), \
609 SR(DOMAIN17_PG_CONFIG), \
610 SR(DOMAIN18_PG_CONFIG), \
611 SR(DOMAIN19_PG_CONFIG), \
612 SR(DOMAIN0_PG_STATUS), \
613 SR(DOMAIN1_PG_STATUS), \
614 SR(DOMAIN2_PG_STATUS), \
615 SR(DOMAIN3_PG_STATUS), \
616 SR(DOMAIN16_PG_STATUS), \
617 SR(DOMAIN17_PG_STATUS), \
618 SR(DOMAIN18_PG_STATUS), \
619 SR(DOMAIN19_PG_STATUS), \
620 SR(D1VGA_CONTROL), \
621 SR(D2VGA_CONTROL), \
622 SR(D3VGA_CONTROL), \
623 SR(D4VGA_CONTROL), \
624 SR(D5VGA_CONTROL), \
625 SR(D6VGA_CONTROL), \
626 SR(DC_IP_REQUEST_CNTL), \
627 SR(AZALIA_AUDIO_DTO), \
628 SR(AZALIA_CONTROLLER_CLOCK_GATING)
629
630 static struct dce_hwseq_registers hwseq_reg;
631
632 #define hwseq_reg_init()\
633 HWSEQ_DCN32_REG_LIST()
634
635 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
636 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
637 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
638 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
639 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
640 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
641 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
642 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
643 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
644 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
645 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
646 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
647 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
648 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
649 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
650 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
651 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
652 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
653 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
654 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
655 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
656 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
657 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
658 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
659 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
660 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
661 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
662 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
663 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
664 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
665 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
666 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
667 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
668
669 static const struct dce_hwseq_shift hwseq_shift = {
670 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
671 };
672
673 static const struct dce_hwseq_mask hwseq_mask = {
674 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
675 };
676 #define vmid_regs_init(id)\
677 DCN20_VMID_REG_LIST_RI(id)
678
679 static struct dcn_vmid_registers vmid_regs[16];
680
681 static const struct dcn20_vmid_shift vmid_shifts = {
682 DCN20_VMID_MASK_SH_LIST(__SHIFT)
683 };
684
685 static const struct dcn20_vmid_mask vmid_masks = {
686 DCN20_VMID_MASK_SH_LIST(_MASK)
687 };
688
689 static struct dcn_dio_registers dio_regs;
690
691 #define DIO_MASK_SH_LIST(mask_sh)\
692 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
693
694 static const struct dcn_dio_shift dio_shift = {
695 DIO_MASK_SH_LIST(__SHIFT)
696 };
697
698 static const struct dcn_dio_mask dio_mask = {
699 DIO_MASK_SH_LIST(_MASK)
700 };
701
702 static const struct resource_caps res_cap_dcn32 = {
703 .num_timing_generator = 4,
704 .num_opp = 4,
705 .num_video_plane = 4,
706 .num_audio = 5,
707 .num_stream_encoder = 5,
708 .num_hpo_frl = 1,
709 .num_hpo_dp_stream_encoder = 4,
710 .num_hpo_dp_link_encoder = 2,
711 .num_pll = 5,
712 .num_dwb = 1,
713 .num_ddc = 5,
714 .num_vmid = 16,
715 .num_mpc_3dlut = 4,
716 .num_dsc = 4,
717 };
718
719 static const struct dc_plane_cap plane_cap = {
720 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
721 .per_pixel_alpha = true,
722
723 .pixel_format_support = {
724 .argb8888 = true,
725 .nv12 = true,
726 .fp16 = true,
727 .p010 = true,
728 .ayuv = false,
729 },
730
731 .max_upscale_factor = {
732 .argb8888 = 16000,
733 .nv12 = 16000,
734 .fp16 = 16000
735 },
736
737 // 6:1 downscaling ratio: 1000/6 = 166.666
738 .max_downscale_factor = {
739 .argb8888 = 167,
740 .nv12 = 167,
741 .fp16 = 167
742 },
743 64,
744 64
745 };
746
747 static const struct dc_debug_options debug_defaults_drv = {
748 .limit_ffe = 3,
749 .disable_dmcu = true,
750 .force_abm_enable = false,
751 .clock_trace = true,
752 .disable_pplib_clock_request = false,
753 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
754 .force_single_disp_pipe_split = false,
755 .disable_dcc = DCC_ENABLE,
756 .vsr_support = true,
757 .performance_trace = false,
758 .max_downscale_src_width = 7680,/*upto 8K*/
759 .disable_pplib_wm_range = false,
760 .scl_reset_length10 = true,
761 .sanity_checks = false,
762 .underflow_assert_delay_us = 0xFFFFFFFF,
763 .dwb_fi_phase = -1, // -1 = disable,
764 .dmub_command_table = true,
765 .enable_mem_low_power = {
766 .bits = {
767 .vga = false,
768 .i2c = false,
769 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
770 .dscl = false,
771 .cm = false,
772 .mpc = false,
773 .optc = true,
774 }
775 },
776 .use_max_lb = true,
777 .force_disable_subvp = false,
778 .exit_idle_opt_for_cursor_updates = true,
779 .using_dml2 = false,
780 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
781 .enable_single_display_2to1_odm_policy = true,
782
783 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
784 .enable_double_buffered_dsc_pg_support = true,
785 .enable_dp_dig_pixel_rate_div_policy = 1,
786 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
787 .alloc_extra_way_for_cursor = true,
788 .min_prefetch_in_strobe_ns = 60000, // 60us
789 .disable_unbounded_requesting = false,
790 .override_dispclk_programming = true,
791 .disable_fpo_optimizations = false,
792 .fpo_vactive_margin_us = 2000, // 2000us
793 .disable_fpo_vactive = false,
794 .disable_boot_optimizations = false,
795 .disable_subvp_high_refresh = false,
796 .disable_dp_plus_plus_wa = true,
797 .fpo_vactive_min_active_margin_us = 200,
798 .fpo_vactive_max_blank_us = 1000,
799 .disable_stutter_for_wm_program = true
800 };
801
802 static const struct dc_check_config config_defaults = {
803 .enable_legacy_fast_update = false,
804 };
805
dcn32_aux_engine_create(struct dc_context * ctx,uint32_t inst)806 static struct dce_aux *dcn32_aux_engine_create(
807 struct dc_context *ctx,
808 uint32_t inst)
809 {
810 struct aux_engine_dce110 *aux_engine =
811 kzalloc_obj(struct aux_engine_dce110);
812
813 if (!aux_engine)
814 return NULL;
815
816 #undef REG_STRUCT
817 #define REG_STRUCT aux_engine_regs
818 aux_engine_regs_init(0),
819 aux_engine_regs_init(1),
820 aux_engine_regs_init(2),
821 aux_engine_regs_init(3),
822 aux_engine_regs_init(4);
823
824 dce110_aux_engine_construct(aux_engine, ctx, inst,
825 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
826 &aux_engine_regs[inst],
827 &aux_mask,
828 &aux_shift,
829 ctx->dc->caps.extended_aux_timeout_support);
830
831 return &aux_engine->base;
832 }
833 #define i2c_inst_regs_init(id)\
834 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
835
836 static struct dce_i2c_registers i2c_hw_regs[5];
837
838 static const struct dce_i2c_shift i2c_shifts = {
839 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
840 };
841
842 static const struct dce_i2c_mask i2c_masks = {
843 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
844 };
845
dcn32_i2c_hw_create(struct dc_context * ctx,uint32_t inst)846 static struct dce_i2c_hw *dcn32_i2c_hw_create(
847 struct dc_context *ctx,
848 uint32_t inst)
849 {
850 struct dce_i2c_hw *dce_i2c_hw =
851 kzalloc_obj(struct dce_i2c_hw);
852
853 if (!dce_i2c_hw)
854 return NULL;
855
856 #undef REG_STRUCT
857 #define REG_STRUCT i2c_hw_regs
858 i2c_inst_regs_init(1),
859 i2c_inst_regs_init(2),
860 i2c_inst_regs_init(3),
861 i2c_inst_regs_init(4),
862 i2c_inst_regs_init(5);
863
864 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
865 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
866
867 return dce_i2c_hw;
868 }
869
dcn32_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)870 static struct clock_source *dcn32_clock_source_create(
871 struct dc_context *ctx,
872 struct dc_bios *bios,
873 enum clock_source_id id,
874 const struct dce110_clk_src_regs *regs,
875 bool dp_clk_src)
876 {
877 struct dce110_clk_src *clk_src =
878 kzalloc_obj(struct dce110_clk_src);
879
880 if (!clk_src)
881 return NULL;
882
883 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
884 regs, &cs_shift, &cs_mask)) {
885 clk_src->base.dp_clk_src = dp_clk_src;
886 return &clk_src->base;
887 }
888
889 kfree(clk_src);
890 BREAK_TO_DEBUGGER();
891 return NULL;
892 }
893
dcn32_dio_create(struct dc_context * ctx)894 static struct dio *dcn32_dio_create(struct dc_context *ctx)
895 {
896 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
897
898 if (!dio10)
899 return NULL;
900
901 #undef REG_STRUCT
902 #define REG_STRUCT dio_regs
903 DIO_REG_LIST_DCN10();
904
905 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
906
907 return &dio10->base;
908 }
909
dcn32_hubbub_create(struct dc_context * ctx)910 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
911 {
912 int i;
913
914 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
915
916 if (!hubbub2)
917 return NULL;
918
919 #undef REG_STRUCT
920 #define REG_STRUCT hubbub_reg
921 hubbub_reg_init();
922
923 #undef REG_STRUCT
924 #define REG_STRUCT vmid_regs
925 vmid_regs_init(0),
926 vmid_regs_init(1),
927 vmid_regs_init(2),
928 vmid_regs_init(3),
929 vmid_regs_init(4),
930 vmid_regs_init(5),
931 vmid_regs_init(6),
932 vmid_regs_init(7),
933 vmid_regs_init(8),
934 vmid_regs_init(9),
935 vmid_regs_init(10),
936 vmid_regs_init(11),
937 vmid_regs_init(12),
938 vmid_regs_init(13),
939 vmid_regs_init(14),
940 vmid_regs_init(15);
941
942 hubbub32_construct(hubbub2, ctx,
943 &hubbub_reg,
944 &hubbub_shift,
945 &hubbub_mask,
946 ctx->dc->dml.ip.det_buffer_size_kbytes,
947 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
948 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
949
950
951 for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
952 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
953
954 vmid->ctx = ctx;
955
956 vmid->regs = &vmid_regs[i];
957 vmid->shifts = &vmid_shifts;
958 vmid->masks = &vmid_masks;
959 }
960
961 return &hubbub2->base;
962 }
963
dcn32_hubp_create(struct dc_context * ctx,uint32_t inst)964 static struct hubp *dcn32_hubp_create(
965 struct dc_context *ctx,
966 uint32_t inst)
967 {
968 struct dcn20_hubp *hubp2 =
969 kzalloc_obj(struct dcn20_hubp);
970
971 if (!hubp2)
972 return NULL;
973
974 #undef REG_STRUCT
975 #define REG_STRUCT hubp_regs
976 hubp_regs_init(0),
977 hubp_regs_init(1),
978 hubp_regs_init(2),
979 hubp_regs_init(3);
980
981 if (hubp32_construct(hubp2, ctx, inst,
982 &hubp_regs[inst], &hubp_shift, &hubp_mask))
983 return &hubp2->base;
984
985 BREAK_TO_DEBUGGER();
986 kfree(hubp2);
987 return NULL;
988 }
989
dcn32_dpp_destroy(struct dpp ** dpp)990 static void dcn32_dpp_destroy(struct dpp **dpp)
991 {
992 kfree(TO_DCN30_DPP(*dpp));
993 *dpp = NULL;
994 }
995
dcn32_dpp_create(struct dc_context * ctx,uint32_t inst)996 static struct dpp *dcn32_dpp_create(
997 struct dc_context *ctx,
998 uint32_t inst)
999 {
1000 struct dcn3_dpp *dpp3 =
1001 kzalloc_obj(struct dcn3_dpp);
1002
1003 if (!dpp3)
1004 return NULL;
1005
1006 #undef REG_STRUCT
1007 #define REG_STRUCT dpp_regs
1008 dpp_regs_init(0),
1009 dpp_regs_init(1),
1010 dpp_regs_init(2),
1011 dpp_regs_init(3);
1012
1013 if (dpp32_construct(dpp3, ctx, inst,
1014 &dpp_regs[inst], &tf_shift, &tf_mask))
1015 return &dpp3->base;
1016
1017 BREAK_TO_DEBUGGER();
1018 kfree(dpp3);
1019 return NULL;
1020 }
1021
dcn32_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1022 static struct mpc *dcn32_mpc_create(
1023 struct dc_context *ctx,
1024 int num_mpcc,
1025 int num_rmu)
1026 {
1027 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1028
1029 if (!mpc30)
1030 return NULL;
1031
1032 #undef REG_STRUCT
1033 #define REG_STRUCT mpc_regs
1034 dcn_mpc_regs_init();
1035
1036 dcn32_mpc_construct(mpc30, ctx,
1037 &mpc_regs,
1038 &mpc_shift,
1039 &mpc_mask,
1040 num_mpcc,
1041 num_rmu);
1042
1043 return &mpc30->base;
1044 }
1045
dcn32_opp_create(struct dc_context * ctx,uint32_t inst)1046 static struct output_pixel_processor *dcn32_opp_create(
1047 struct dc_context *ctx, uint32_t inst)
1048 {
1049 struct dcn20_opp *opp2 =
1050 kzalloc_obj(struct dcn20_opp);
1051
1052 if (!opp2) {
1053 BREAK_TO_DEBUGGER();
1054 return NULL;
1055 }
1056
1057 #undef REG_STRUCT
1058 #define REG_STRUCT opp_regs
1059 opp_regs_init(0),
1060 opp_regs_init(1),
1061 opp_regs_init(2),
1062 opp_regs_init(3);
1063
1064 dcn20_opp_construct(opp2, ctx, inst,
1065 &opp_regs[inst], &opp_shift, &opp_mask);
1066 return &opp2->base;
1067 }
1068
1069
dcn32_timing_generator_create(struct dc_context * ctx,uint32_t instance)1070 static struct timing_generator *dcn32_timing_generator_create(
1071 struct dc_context *ctx,
1072 uint32_t instance)
1073 {
1074 struct optc *tgn10 =
1075 kzalloc_obj(struct optc);
1076
1077 if (!tgn10)
1078 return NULL;
1079
1080 #undef REG_STRUCT
1081 #define REG_STRUCT optc_regs
1082 optc_regs_init(0),
1083 optc_regs_init(1),
1084 optc_regs_init(2),
1085 optc_regs_init(3);
1086
1087 tgn10->base.inst = instance;
1088 tgn10->base.ctx = ctx;
1089
1090 tgn10->tg_regs = &optc_regs[instance];
1091 tgn10->tg_shift = &optc_shift;
1092 tgn10->tg_mask = &optc_mask;
1093
1094 dcn32_timing_generator_init(tgn10);
1095
1096 return &tgn10->base;
1097 }
1098
1099 static const struct encoder_feature_support link_enc_feature = {
1100 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1101 .max_hdmi_pixel_clock = 600000,
1102 .hdmi_ycbcr420_supported = true,
1103 .dp_ycbcr420_supported = true,
1104 .fec_supported = true,
1105 .flags.bits.IS_HBR2_CAPABLE = true,
1106 .flags.bits.IS_HBR3_CAPABLE = true,
1107 .flags.bits.IS_TPS3_CAPABLE = true,
1108 .flags.bits.IS_TPS4_CAPABLE = true
1109 };
1110
dcn32_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1111 static struct link_encoder *dcn32_link_encoder_create(
1112 struct dc_context *ctx,
1113 const struct encoder_init_data *enc_init_data)
1114 {
1115 struct dcn20_link_encoder *enc20 =
1116 kzalloc_obj(struct dcn20_link_encoder);
1117
1118 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1119 return NULL;
1120
1121 #undef REG_STRUCT
1122 #define REG_STRUCT link_enc_aux_regs
1123 aux_regs_init(0),
1124 aux_regs_init(1),
1125 aux_regs_init(2),
1126 aux_regs_init(3),
1127 aux_regs_init(4);
1128
1129 #undef REG_STRUCT
1130 #define REG_STRUCT link_enc_hpd_regs
1131 hpd_regs_init(0),
1132 hpd_regs_init(1),
1133 hpd_regs_init(2),
1134 hpd_regs_init(3),
1135 hpd_regs_init(4);
1136
1137 #undef REG_STRUCT
1138 #define REG_STRUCT link_enc_regs
1139 link_regs_init(0, A),
1140 link_regs_init(1, B),
1141 link_regs_init(2, C),
1142 link_regs_init(3, D),
1143 link_regs_init(4, E);
1144
1145 dcn32_link_encoder_construct(enc20,
1146 enc_init_data,
1147 &link_enc_feature,
1148 &link_enc_regs[enc_init_data->transmitter],
1149 &link_enc_aux_regs[enc_init_data->channel - 1],
1150 &link_enc_hpd_regs[enc_init_data->hpd_source],
1151 &le_shift,
1152 &le_mask);
1153
1154 return &enc20->enc10.base;
1155 }
1156
dcn32_panel_cntl_create(const struct panel_cntl_init_data * init_data)1157 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1158 {
1159 struct dcn31_panel_cntl *panel_cntl =
1160 kzalloc_obj(struct dcn31_panel_cntl);
1161
1162 if (!panel_cntl)
1163 return NULL;
1164
1165 dcn31_panel_cntl_construct(panel_cntl, init_data);
1166
1167 return &panel_cntl->base;
1168 }
1169
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1170 static void read_dce_straps(
1171 struct dc_context *ctx,
1172 struct resource_straps *straps)
1173 {
1174 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1175 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1176
1177 }
1178
dcn32_create_audio(struct dc_context * ctx,unsigned int inst)1179 static struct audio *dcn32_create_audio(
1180 struct dc_context *ctx, unsigned int inst)
1181 {
1182
1183 #undef REG_STRUCT
1184 #define REG_STRUCT audio_regs
1185 audio_regs_init(0),
1186 audio_regs_init(1),
1187 audio_regs_init(2),
1188 audio_regs_init(3),
1189 audio_regs_init(4);
1190
1191 return dce_audio_create(ctx, inst,
1192 &audio_regs[inst], &audio_shift, &audio_mask);
1193 }
1194
dcn32_vpg_create(struct dc_context * ctx,uint32_t inst)1195 static struct vpg *dcn32_vpg_create(
1196 struct dc_context *ctx,
1197 uint32_t inst)
1198 {
1199 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
1200
1201 if (!vpg3)
1202 return NULL;
1203
1204 #undef REG_STRUCT
1205 #define REG_STRUCT vpg_regs
1206 vpg_regs_init(0),
1207 vpg_regs_init(1),
1208 vpg_regs_init(2),
1209 vpg_regs_init(3),
1210 vpg_regs_init(4),
1211 vpg_regs_init(5),
1212 vpg_regs_init(6),
1213 vpg_regs_init(7),
1214 vpg_regs_init(8),
1215 vpg_regs_init(9);
1216
1217 vpg3_construct(vpg3, ctx, inst,
1218 &vpg_regs[inst],
1219 &vpg_shift,
1220 &vpg_mask);
1221
1222 return &vpg3->base;
1223 }
1224
dcn32_afmt_create(struct dc_context * ctx,uint32_t inst)1225 static struct afmt *dcn32_afmt_create(
1226 struct dc_context *ctx,
1227 uint32_t inst)
1228 {
1229 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1230
1231 if (!afmt3)
1232 return NULL;
1233
1234 #undef REG_STRUCT
1235 #define REG_STRUCT afmt_regs
1236 afmt_regs_init(0),
1237 afmt_regs_init(1),
1238 afmt_regs_init(2),
1239 afmt_regs_init(3),
1240 afmt_regs_init(4),
1241 afmt_regs_init(5);
1242
1243 afmt3_construct(afmt3, ctx, inst,
1244 &afmt_regs[inst],
1245 &afmt_shift,
1246 &afmt_mask);
1247
1248 return &afmt3->base;
1249 }
1250
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1251 static struct apg *dcn31_apg_create(
1252 struct dc_context *ctx,
1253 uint32_t inst)
1254 {
1255 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1256
1257 if (!apg31)
1258 return NULL;
1259
1260 #undef REG_STRUCT
1261 #define REG_STRUCT apg_regs
1262 apg_regs_init(0),
1263 apg_regs_init(1),
1264 apg_regs_init(2),
1265 apg_regs_init(3);
1266
1267 apg31_construct(apg31, ctx, inst,
1268 &apg_regs[inst],
1269 &apg_shift,
1270 &apg_mask);
1271
1272 return &apg31->base;
1273 }
1274
dcn32_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1275 static struct stream_encoder *dcn32_stream_encoder_create(
1276 enum engine_id eng_id,
1277 struct dc_context *ctx)
1278 {
1279 struct dcn10_stream_encoder *enc1;
1280 struct vpg *vpg;
1281 struct afmt *afmt;
1282 int vpg_inst;
1283 int afmt_inst;
1284
1285 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1286 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1287 return NULL;
1288
1289 vpg_inst = eng_id;
1290 afmt_inst = eng_id;
1291
1292 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1293 vpg = dcn32_vpg_create(ctx, vpg_inst);
1294 afmt = dcn32_afmt_create(ctx, afmt_inst);
1295
1296 if (!enc1 || !vpg || !afmt) {
1297 kfree(enc1);
1298 kfree(vpg);
1299 kfree(afmt);
1300 return NULL;
1301 }
1302
1303 #undef REG_STRUCT
1304 #define REG_STRUCT stream_enc_regs
1305 stream_enc_regs_init(0),
1306 stream_enc_regs_init(1),
1307 stream_enc_regs_init(2),
1308 stream_enc_regs_init(3),
1309 stream_enc_regs_init(4);
1310
1311 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1312 eng_id, vpg, afmt,
1313 &stream_enc_regs[eng_id],
1314 &se_shift, &se_mask);
1315
1316 return &enc1->base;
1317 }
1318
dcn32_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1319 static struct hpo_frl_stream_encoder *dcn32_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1320 struct dc_context *ctx)
1321 {
1322 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1323 struct afmt *afmt;
1324 struct vpg *vpg;
1325 int afmt_inst;
1326 int vpg_inst;
1327
1328 #undef REG_STRUCT
1329 #define REG_STRUCT hpo_frl_stream_enc_regs
1330 hpo_frl_stream_encoder_reg_list(0),
1331 hpo_frl_stream_encoder_dme_reg_list(6);
1332
1333 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1334 if (eng_id == ENGINE_ID_HPO_0) {
1335 vpg_inst = 5;
1336 afmt_inst = 5;
1337 } else {
1338 return NULL;
1339 }
1340
1341 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1342 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1343 vpg = dcn32_vpg_create(ctx, vpg_inst);
1344 afmt = dcn32_afmt_create(ctx, afmt_inst);
1345
1346 if (!hpo_enc3 || !vpg || !afmt) {
1347 kfree(hpo_enc3);
1348 kfree(vpg);
1349 kfree(afmt);
1350 return NULL;
1351 }
1352
1353 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1354 ctx,
1355 ctx->dc_bios,
1356 eng_id,
1357 vpg,
1358 afmt,
1359 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1360 &hpo_se_shift,
1361 &hpo_se_mask);
1362
1363 return &hpo_enc3->base;
1364 }
1365
dcn32_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1366 static struct hpo_frl_link_encoder *dcn32_hpo_frl_link_encoder_create(enum engine_id eng_id,
1367 struct dc_context *ctx)
1368 {
1369 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1370
1371 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1372
1373 #undef REG_STRUCT
1374 #define REG_STRUCT hpo_frl_link_enc_regs
1375 hpo_frl_link_encoder_reg_list(0);
1376
1377 /* allocate HPO link encoder */
1378 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1379 if (!hpo_enc3)
1380 return NULL; /* out of memory */
1381
1382 hpo_frl_link_encoder3_construct(hpo_enc3,
1383 ctx,
1384 eng_id - ENGINE_ID_HPO_0,
1385 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1386 &hpo_le_shift,
1387 &hpo_le_mask);
1388
1389 return &hpo_enc3->base;
1390 }
1391
dcn32_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1392 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1393 enum engine_id eng_id,
1394 struct dc_context *ctx)
1395 {
1396 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1397 struct vpg *vpg;
1398 struct apg *apg;
1399 uint32_t hpo_dp_inst;
1400 uint32_t vpg_inst;
1401 uint32_t apg_inst;
1402
1403 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1404 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1405
1406 /* Mapping of VPG register blocks to HPO DP block instance:
1407 * VPG[6] -> HPO_DP[0]
1408 * VPG[7] -> HPO_DP[1]
1409 * VPG[8] -> HPO_DP[2]
1410 * VPG[9] -> HPO_DP[3]
1411 */
1412 vpg_inst = hpo_dp_inst + 6;
1413
1414 /* Mapping of APG register blocks to HPO DP block instance:
1415 * APG[0] -> HPO_DP[0]
1416 * APG[1] -> HPO_DP[1]
1417 * APG[2] -> HPO_DP[2]
1418 * APG[3] -> HPO_DP[3]
1419 */
1420 apg_inst = hpo_dp_inst;
1421
1422 /* allocate HPO stream encoder and create VPG sub-block */
1423 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1424 vpg = dcn32_vpg_create(ctx, vpg_inst);
1425 apg = dcn31_apg_create(ctx, apg_inst);
1426
1427 if (!hpo_dp_enc31 || !vpg || !apg) {
1428 kfree(hpo_dp_enc31);
1429 kfree(vpg);
1430 kfree(apg);
1431 return NULL;
1432 }
1433
1434 #undef REG_STRUCT
1435 #define REG_STRUCT hpo_dp_stream_enc_regs
1436 hpo_dp_stream_encoder_reg_init(0),
1437 hpo_dp_stream_encoder_reg_init(1),
1438 hpo_dp_stream_encoder_reg_init(2),
1439 hpo_dp_stream_encoder_reg_init(3);
1440
1441 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1442 hpo_dp_inst, eng_id, vpg, apg,
1443 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1444 &hpo_dp_se_shift, &hpo_dp_se_mask);
1445
1446 return &hpo_dp_enc31->base;
1447 }
1448
dcn32_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1449 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1450 uint8_t inst,
1451 struct dc_context *ctx)
1452 {
1453 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1454
1455 /* allocate HPO link encoder */
1456 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1457 if (!hpo_dp_enc31)
1458 return NULL; /* out of memory */
1459
1460 #undef REG_STRUCT
1461 #define REG_STRUCT hpo_dp_link_enc_regs
1462 hpo_dp_link_encoder_reg_init(0),
1463 hpo_dp_link_encoder_reg_init(1);
1464
1465 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1466 &hpo_dp_link_enc_regs[inst],
1467 &hpo_dp_le_shift, &hpo_dp_le_mask);
1468
1469 return &hpo_dp_enc31->base;
1470 }
1471
dcn32_hwseq_create(struct dc_context * ctx)1472 static struct dce_hwseq *dcn32_hwseq_create(
1473 struct dc_context *ctx)
1474 {
1475 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1476
1477 #undef REG_STRUCT
1478 #define REG_STRUCT hwseq_reg
1479 hwseq_reg_init();
1480
1481 if (hws) {
1482 hws->ctx = ctx;
1483 hws->regs = &hwseq_reg;
1484 hws->shifts = &hwseq_shift;
1485 hws->masks = &hwseq_mask;
1486 }
1487 return hws;
1488 }
1489 static const struct resource_create_funcs res_create_funcs = {
1490 .read_dce_straps = read_dce_straps,
1491 .create_audio = dcn32_create_audio,
1492 .create_stream_encoder = dcn32_stream_encoder_create,
1493 .create_hpo_frl_stream_encoder = dcn32_hpo_frl_stream_encoder_create,
1494 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1495 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1496 .create_hwseq = dcn32_hwseq_create,
1497 };
1498
dcn32_resource_destruct(struct dcn32_resource_pool * pool)1499 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1500 {
1501 unsigned int i;
1502
1503 for (i = 0; i < pool->base.stream_enc_count; i++) {
1504 if (pool->base.stream_enc[i] != NULL) {
1505 if (pool->base.stream_enc[i]->vpg != NULL) {
1506 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1507 pool->base.stream_enc[i]->vpg = NULL;
1508 }
1509 if (pool->base.stream_enc[i]->afmt != NULL) {
1510 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1511 pool->base.stream_enc[i]->afmt = NULL;
1512 }
1513 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1514 pool->base.stream_enc[i] = NULL;
1515 }
1516 }
1517
1518 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1519 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1520 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1521 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1522 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1523 }
1524
1525 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1526 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1527 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1528 }
1529
1530 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1531 pool->base.hpo_frl_stream_enc[i] = NULL;
1532 }
1533 }
1534
1535 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1536 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1537 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1538 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1539 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1540 }
1541 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1542 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1543 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1544 }
1545 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1546 pool->base.hpo_dp_stream_enc[i] = NULL;
1547 }
1548 }
1549
1550 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1551 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1552 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1553 pool->base.hpo_dp_link_enc[i] = NULL;
1554 }
1555 }
1556
1557 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1558 if (pool->base.dscs[i] != NULL)
1559 dcn20_dsc_destroy(&pool->base.dscs[i]);
1560 }
1561
1562 if (pool->base.mpc != NULL) {
1563 kfree(TO_DCN20_MPC(pool->base.mpc));
1564 pool->base.mpc = NULL;
1565 }
1566 if (pool->base.hubbub != NULL) {
1567 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1568 pool->base.hubbub = NULL;
1569 }
1570 for (i = 0; i < pool->base.pipe_count; i++) {
1571 if (pool->base.dpps[i] != NULL)
1572 dcn32_dpp_destroy(&pool->base.dpps[i]);
1573
1574 if (pool->base.ipps[i] != NULL)
1575 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1576
1577 if (pool->base.hubps[i] != NULL) {
1578 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1579 pool->base.hubps[i] = NULL;
1580 }
1581
1582 if (pool->base.irqs != NULL) {
1583 dal_irq_service_destroy(&pool->base.irqs);
1584 }
1585 }
1586
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1588 if (pool->base.engines[i] != NULL)
1589 dce110_engine_destroy(&pool->base.engines[i]);
1590 if (pool->base.hw_i2cs[i] != NULL) {
1591 kfree(pool->base.hw_i2cs[i]);
1592 pool->base.hw_i2cs[i] = NULL;
1593 }
1594 if (pool->base.sw_i2cs[i] != NULL) {
1595 kfree(pool->base.sw_i2cs[i]);
1596 pool->base.sw_i2cs[i] = NULL;
1597 }
1598 }
1599
1600 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1601 if (pool->base.opps[i] != NULL)
1602 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1603 }
1604
1605 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1606 if (pool->base.timing_generators[i] != NULL) {
1607 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1608 pool->base.timing_generators[i] = NULL;
1609 }
1610 }
1611
1612 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1613 if (pool->base.dwbc[i] != NULL) {
1614 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1615 pool->base.dwbc[i] = NULL;
1616 }
1617 if (pool->base.mcif_wb[i] != NULL) {
1618 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1619 pool->base.mcif_wb[i] = NULL;
1620 }
1621 }
1622
1623 for (i = 0; i < pool->base.audio_count; i++) {
1624 if (pool->base.audios[i])
1625 dce_aud_destroy(&pool->base.audios[i]);
1626 }
1627
1628 for (i = 0; i < pool->base.clk_src_count; i++) {
1629 if (pool->base.clock_sources[i] != NULL) {
1630 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1631 pool->base.clock_sources[i] = NULL;
1632 }
1633 }
1634
1635 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1636 if (pool->base.mpc_lut[i] != NULL) {
1637 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1638 pool->base.mpc_lut[i] = NULL;
1639 }
1640 if (pool->base.mpc_shaper[i] != NULL) {
1641 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1642 pool->base.mpc_shaper[i] = NULL;
1643 }
1644 }
1645
1646 if (pool->base.dp_clock_source != NULL) {
1647 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1648 pool->base.dp_clock_source = NULL;
1649 }
1650
1651 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1652 if (pool->base.multiple_abms[i] != NULL)
1653 dce_abm_destroy(&pool->base.multiple_abms[i]);
1654 }
1655
1656 if (pool->base.psr != NULL)
1657 dmub_psr_destroy(&pool->base.psr);
1658
1659 if (pool->base.dccg != NULL)
1660 dcn_dccg_destroy(&pool->base.dccg);
1661
1662 if (pool->base.dio != NULL) {
1663 kfree(TO_DCN10_DIO(pool->base.dio));
1664 pool->base.dio = NULL;
1665 }
1666
1667 if (pool->base.oem_device != NULL) {
1668 struct dc *dc = pool->base.oem_device->ctx->dc;
1669
1670 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1671 }
1672 }
1673
1674
dcn32_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1675 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1676 {
1677 unsigned int i;
1678 uint32_t dwb_count = pool->res_cap->num_dwb;
1679
1680 for (i = 0; i < dwb_count; i++) {
1681 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1682
1683 if (!dwbc30) {
1684 dm_error("DC: failed to create dwbc30!\n");
1685 return false;
1686 }
1687
1688 #undef REG_STRUCT
1689 #define REG_STRUCT dwbc30_regs
1690 dwbc_regs_dcn3_init(0);
1691
1692 dcn30_dwbc_construct(dwbc30, ctx,
1693 &dwbc30_regs[i],
1694 &dwbc30_shift,
1695 &dwbc30_mask,
1696 i);
1697
1698 pool->dwbc[i] = &dwbc30->base;
1699 }
1700 return true;
1701 }
1702
dcn32_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1703 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1704 {
1705 unsigned int i;
1706 uint32_t dwb_count = pool->res_cap->num_dwb;
1707
1708 for (i = 0; i < dwb_count; i++) {
1709 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1710
1711 if (!mcif_wb30) {
1712 dm_error("DC: failed to create mcif_wb30!\n");
1713 return false;
1714 }
1715
1716 #undef REG_STRUCT
1717 #define REG_STRUCT mcif_wb30_regs
1718 mcif_wb_regs_dcn3_init(0);
1719
1720 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1721 &mcif_wb30_regs[i],
1722 &mcif_wb30_shift,
1723 &mcif_wb30_mask,
1724 i);
1725
1726 pool->mcif_wb[i] = &mcif_wb30->base;
1727 }
1728 return true;
1729 }
1730
dcn32_dsc_create(struct dc_context * ctx,uint32_t inst)1731 static struct display_stream_compressor *dcn32_dsc_create(
1732 struct dc_context *ctx, uint32_t inst)
1733 {
1734 struct dcn20_dsc *dsc =
1735 kzalloc_obj(struct dcn20_dsc);
1736
1737 if (!dsc) {
1738 BREAK_TO_DEBUGGER();
1739 return NULL;
1740 }
1741
1742 #undef REG_STRUCT
1743 #define REG_STRUCT dsc_regs
1744 dsc_regsDCN20_init(0),
1745 dsc_regsDCN20_init(1),
1746 dsc_regsDCN20_init(2),
1747 dsc_regsDCN20_init(3);
1748
1749 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1750
1751 dsc->max_image_width = 6016;
1752
1753 return &dsc->base;
1754 }
1755
dcn32_destroy_resource_pool(struct resource_pool ** pool)1756 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1757 {
1758 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1759
1760 dcn32_resource_destruct(dcn32_pool);
1761 kfree(dcn32_pool);
1762 *pool = NULL;
1763 }
1764
dcn32_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1765 bool dcn32_acquire_post_bldn_3dlut(
1766 struct resource_context *res_ctx,
1767 const struct resource_pool *pool,
1768 int mpcc_id,
1769 struct dc_3dlut **lut,
1770 struct dc_transfer_func **shaper)
1771 {
1772 bool ret = false;
1773
1774 ASSERT(*lut == NULL && *shaper == NULL);
1775 *lut = NULL;
1776 *shaper = NULL;
1777
1778 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1779 *lut = pool->mpc_lut[mpcc_id];
1780 *shaper = pool->mpc_shaper[mpcc_id];
1781 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1782 ret = true;
1783 }
1784 return ret;
1785 }
1786
dcn32_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1787 bool dcn32_release_post_bldn_3dlut(
1788 struct resource_context *res_ctx,
1789 const struct resource_pool *pool,
1790 struct dc_3dlut **lut,
1791 struct dc_transfer_func **shaper)
1792 {
1793 int i;
1794 bool ret = false;
1795
1796 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1797 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1798 res_ctx->is_mpc_3dlut_acquired[i] = false;
1799 pool->mpc_lut[i]->state.raw = 0;
1800 *lut = NULL;
1801 *shaper = NULL;
1802 ret = true;
1803 break;
1804 }
1805 }
1806 return ret;
1807 }
1808
dcn32_enable_phantom_plane(struct dc * dc,struct dc_state * context,struct dc_stream_state * phantom_stream,unsigned int dc_pipe_idx)1809 static void dcn32_enable_phantom_plane(struct dc *dc,
1810 struct dc_state *context,
1811 struct dc_stream_state *phantom_stream,
1812 unsigned int dc_pipe_idx)
1813 {
1814 struct dc_plane_state *phantom_plane = NULL;
1815 struct dc_plane_state *prev_phantom_plane = NULL;
1816 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1817
1818 while (curr_pipe) {
1819 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1820 phantom_plane = prev_phantom_plane;
1821 else
1822 DC_RUN_WITH_PREEMPTION_ENABLED(phantom_plane =
1823 dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state));
1824
1825 if (!phantom_plane)
1826 continue;
1827
1828 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1829 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1830 sizeof(phantom_plane->scaling_quality));
1831 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1832 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1833 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1834 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1835 sizeof(phantom_plane->plane_size));
1836 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1837 sizeof(phantom_plane->tiling_info));
1838 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1839 phantom_plane->format = curr_pipe->plane_state->format;
1840 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1841 phantom_plane->visible = curr_pipe->plane_state->visible;
1842
1843 /* Shadow pipe has small viewport. */
1844 phantom_plane->clip_rect.y = 0;
1845 phantom_plane->clip_rect.height = phantom_stream->src.height;
1846
1847 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);
1848
1849 curr_pipe = curr_pipe->bottom_pipe;
1850 prev_phantom_plane = phantom_plane;
1851 }
1852 }
1853
dcn32_enable_phantom_stream(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)1854 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1855 struct dc_state *context,
1856 display_e2e_pipe_params_st *pipes,
1857 unsigned int pipe_cnt,
1858 unsigned int dc_pipe_idx)
1859 {
1860 struct dc_stream_state *phantom_stream = NULL;
1861 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1862
1863 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);
1864 if (!phantom_stream)
1865 return phantom_stream;
1866
1867 /* stream has limited viewport and small timing */
1868 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1869 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1870 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1871 DC_FP_START();
1872 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1873 DC_FP_END();
1874
1875 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);
1876 return phantom_stream;
1877 }
1878
1879 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1880 * require a phantom pipe / stream
1881 */
dcn32_add_phantom_pipes(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int index)1882 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1883 display_e2e_pipe_params_st *pipes,
1884 unsigned int pipe_cnt,
1885 unsigned int index)
1886 {
1887 struct dc_stream_state *phantom_stream = NULL;
1888 unsigned int i;
1889
1890 // The index of the DC pipe passed into this function is guarenteed to
1891 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1892 // already have phantom pipe assigned, etc.) by previous checks.
1893 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1894 if (!phantom_stream)
1895 return;
1896
1897 dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1898
1899 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1900 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1901
1902 // Build scaling params for phantom pipes which were newly added.
1903 // We determine which phantom pipes were added by comparing with
1904 // the phantom stream.
1905 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1906 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
1907 pipe->stream->use_dynamic_meta = false;
1908 pipe->plane_state->flip_immediate = false;
1909 if (!resource_build_scaling_params(pipe)) {
1910 // Log / remove phantom pipes since failed to build scaling params
1911 }
1912 }
1913 }
1914 }
1915
dml1_validate(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1916 static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)
1917 {
1918 bool out = false;
1919
1920 BW_VAL_TRACE_SETUP();
1921
1922 int vlevel = 0;
1923 int pipe_cnt = 0;
1924 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1925 dc->res_pool->pipe_count);
1926
1927 /* To handle Freesync properly, setting FreeSync DML parameters
1928 * to its default state for the first stage of validation
1929 */
1930 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1931 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1932
1933 DC_LOGGER_INIT(dc->ctx->logger);
1934
1935 BW_VAL_TRACE_COUNT();
1936
1937 if (!pipes)
1938 goto validate_fail;
1939
1940 DC_FP_START();
1941 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);
1942 DC_FP_END();
1943
1944 if (pipe_cnt == 0)
1945 goto validate_out;
1946
1947 if (!out)
1948 goto validate_fail;
1949
1950 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1951
1952 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1953 BW_VAL_TRACE_SKIP(fast);
1954 goto validate_out;
1955 }
1956
1957 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1958
1959 DC_FP_START();
1960 dcn32_override_min_req_memclk(dc, context);
1961 DC_FP_END();
1962
1963 dcn32_override_min_req_dcfclk(dc, context);
1964
1965 BW_VAL_TRACE_END_WATERMARKS();
1966
1967 goto validate_out;
1968
1969 validate_fail:
1970 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1971 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1972
1973 BW_VAL_TRACE_SKIP(fail);
1974 out = false;
1975
1976 validate_out:
1977 kfree(pipes);
1978
1979 BW_VAL_TRACE_FINISH();
1980
1981 return out;
1982 }
1983
dcn32_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1984 enum dc_status dcn32_validate_bandwidth(struct dc *dc,
1985 struct dc_state *context,
1986 enum dc_validate_mode validate_mode)
1987 {
1988 unsigned int i;
1989 enum dc_status status;
1990 const struct dc_stream_state *stream;
1991
1992 /* reset cursor limitations on subvp */
1993 for (i = 0; i < context->stream_count; i++) {
1994 stream = context->streams[i];
1995
1996 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1997 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1998 }
1999 }
2000
2001 if (dc->debug.using_dml2)
2002 status = dml2_validate(dc, context,
2003 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
2004 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
2005 else
2006 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
2007
2008 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
2009 /* check new stream configuration still supports cursor if subvp used */
2010 for (i = 0; i < context->stream_count; i++) {
2011 stream = context->streams[i];
2012
2013 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
2014 stream->cursor_position.enable &&
2015 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
2016 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
2017 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
2018 status = DC_FAIL_HW_CURSOR_SUPPORT;
2019 }
2020 }
2021 }
2022
2023 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
2024 /* attempt to validate again with subvp disabled due to cursor */
2025 if (dc->debug.using_dml2)
2026 status = dml2_validate(dc, context,
2027 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
2028 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
2029 else
2030 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
2031 }
2032
2033 return status;
2034 }
2035
dcn32_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)2036 int dcn32_populate_dml_pipes_from_context(
2037 struct dc *dc, struct dc_state *context,
2038 display_e2e_pipe_params_st *pipes,
2039 enum dc_validate_mode validate_mode)
2040 {
2041 unsigned int i;
2042 int pipe_cnt;
2043 struct resource_context *res_ctx = &context->res_ctx;
2044 struct pipe_ctx *pipe = NULL;
2045 bool subvp_in_use = false;
2046 struct dc_crtc_timing *timing;
2047 int subvp_main_pipe_index = -1;
2048 enum mall_stream_type mall_type;
2049 bool single_display_subvp = false;
2050 struct dc_stream_state *stream = NULL;
2051 int num_subvp_main = 0;
2052 int num_subvp_phantom = 0;
2053 int num_subvp_none = 0;
2054 int odm_slice_count;
2055
2056 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
2057
2058 /* For single display subvp, look for subvp main so if we have phantom
2059 * pipe, we can set odm policy to match main pipe
2060 */
2061 for (i = 0; i < context->stream_count; i++) {
2062 stream = context->streams[i];
2063 mall_type = dc_state_get_stream_subvp_type(context, stream);
2064 if (mall_type == SUBVP_MAIN)
2065 num_subvp_main++;
2066 else if (mall_type == SUBVP_PHANTOM)
2067 num_subvp_phantom++;
2068 else
2069 num_subvp_none++;
2070 }
2071 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0)
2072 single_display_subvp = true;
2073
2074 if (single_display_subvp) {
2075 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2076 pipe = &res_ctx->pipe_ctx[i];
2077 if (!res_ctx->pipe_ctx[i].stream)
2078 continue;
2079
2080 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
2081 if (mall_type == SUBVP_MAIN) {
2082 if (resource_is_pipe_type(pipe, OTG_MASTER))
2083 subvp_main_pipe_index = i;
2084 }
2085 pipe_cnt++;
2086 }
2087 }
2088
2089 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2090
2091 if (!res_ctx->pipe_ctx[i].stream)
2092 continue;
2093 pipe = &res_ctx->pipe_ctx[i];
2094 timing = &pipe->stream->timing;
2095
2096 pipes[pipe_cnt].pipe.src.gpuvm = true;
2097 DC_FP_START();
2098 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);
2099 DC_FP_END();
2100 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
2101 if (dc->config.enable_windowed_mpo_odm &&
2102 dc->debug.enable_single_display_2to1_odm_policy) {
2103 /* For single display subvp, if pipe is phantom pipe,
2104 * then copy odm policy from subvp main pipe
2105 */
2106 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
2107 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) {
2108 if (subvp_main_pipe_index < 0) {
2109 odm_slice_count = -1;
2110 ASSERT(0);
2111 } else {
2112 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);
2113 }
2114 } else {
2115 odm_slice_count = resource_get_odm_slice_count(pipe);
2116 }
2117 switch (odm_slice_count) {
2118 case 2:
2119 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
2120 break;
2121 case 4:
2122 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
2123 break;
2124 default:
2125 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
2126 }
2127 } else {
2128 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
2129 }
2130
2131 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
2132 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
2133 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
2134
2135 /* Only populate DML input with subvp info for full updates.
2136 * This is just a workaround -- needs a proper fix.
2137 */
2138 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
2139 switch (dc_state_get_pipe_subvp_type(context, pipe)) {
2140 case SUBVP_MAIN:
2141 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
2142 subvp_in_use = true;
2143 break;
2144 case SUBVP_PHANTOM:
2145 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
2146 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
2147 // Disallow unbounded req for SubVP according to DCHUB programming guide
2148 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
2149 break;
2150 case SUBVP_NONE:
2151 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
2152 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
2153 break;
2154 default:
2155 break;
2156 }
2157 }
2158
2159 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
2160 if (pipes[pipe_cnt].dout.dsc_enable) {
2161 switch (timing->display_color_depth) {
2162 case COLOR_DEPTH_888:
2163 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
2164 break;
2165 case COLOR_DEPTH_101010:
2166 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
2167 break;
2168 case COLOR_DEPTH_121212:
2169 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
2170 break;
2171 default:
2172 ASSERT(0);
2173 break;
2174 }
2175 }
2176
2177
2178 pipe_cnt++;
2179 }
2180
2181 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
2182 * the DET available for each pipe). Use the DET override input to maintain our driver
2183 * policy.
2184 */
2185 dcn32_set_det_allocations(dc, context, pipes);
2186
2187 // In general cases we want to keep the dram clock change requirement
2188 // (prefer configs that support MCLK switch). Only override to false
2189 // for SubVP
2190 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
2191 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
2192 else
2193 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
2194
2195 return pipe_cnt;
2196 }
2197
dcn32_calculate_mall_ways_from_bytes(const struct dc * dc,unsigned int total_size_in_mall_bytes)2198 unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)
2199 {
2200 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
2201
2202 if (total_size_in_mall_bytes == 0) {
2203 return 0;
2204 }
2205
2206 if (dc->caps.max_cab_allocation_bytes == 0) {
2207 return 0xffffffff;
2208 }
2209
2210 /* add 2 lines for worst case alignment */
2211 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
2212
2213 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
2214 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
2215 num_ways = cache_lines_used / lines_per_way;
2216 if (cache_lines_used % lines_per_way > 0)
2217 num_ways++;
2218
2219 return num_ways;
2220 }
2221
2222 static struct dc_cap_funcs cap_funcs = {
2223 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
2224 .get_subvp_en = dcn32_subvp_in_use,
2225 };
2226
dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2227 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
2228 display_e2e_pipe_params_st *pipes,
2229 int pipe_cnt,
2230 int vlevel)
2231 {
2232 DC_FP_START();
2233 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
2234 DC_FP_END();
2235 }
2236
dcn32_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2237 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2238 {
2239 DC_FP_START();
2240
2241 dcn32_update_bw_bounding_box_fpu(dc, bw_params);
2242
2243 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
2244 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
2245
2246 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
2247 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
2248
2249 DC_FP_END();
2250 }
2251
dcn32_get_max_hw_cursor_size(const struct dc * dc,struct dc_state * state,const struct dc_stream_state * stream)2252 unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
2253 struct dc_state *state,
2254 const struct dc_stream_state *stream)
2255 {
2256 bool limit_cur_to_buf;
2257
2258 limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) &&
2259 !stream->hw_cursor_req;
2260
2261 return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size;
2262 }
2263
2264 static struct resource_funcs dcn32_res_pool_funcs = {
2265 .destroy = dcn32_destroy_resource_pool,
2266 .link_enc_create = dcn32_link_encoder_create,
2267 .link_enc_create_minimal = NULL,
2268 .hpo_frl_link_enc_create = dcn32_hpo_frl_link_encoder_create,
2269 .panel_cntl_create = dcn32_panel_cntl_create,
2270 .validate_bandwidth = dcn32_validate_bandwidth,
2271 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
2272 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
2273 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
2274 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
2275 .release_pipe = dcn20_release_pipe,
2276 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2277 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2278 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2279 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2280 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2281 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2282 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
2283 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
2284 .update_bw_bounding_box = dcn32_update_bw_bounding_box,
2285 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2286 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2287 .add_phantom_pipes = dcn32_add_phantom_pipes,
2288 .get_default_tiling_info = dcn10_get_default_tiling_info,
2289 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
2290 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
2291 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2292 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
2293 };
2294
read_pipe_fuses(struct dc_context * ctx)2295 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2296 {
2297 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2298 /* DCN32 support max 4 pipes */
2299 value = value & 0xf;
2300 return value;
2301 }
2302
2303
dcn32_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn32_resource_pool * pool)2304 static bool dcn32_resource_construct(
2305 uint8_t num_virtual_links,
2306 struct dc *dc,
2307 struct dcn32_resource_pool *pool)
2308 {
2309 int i, j;
2310 struct dc_context *ctx = dc->ctx;
2311 struct irq_service_init_data init_data;
2312 struct ddc_service_init_data ddc_init_data = {0};
2313 uint32_t pipe_fuses = 0;
2314 uint32_t num_pipes = 4;
2315
2316 #undef REG_STRUCT
2317 #define REG_STRUCT bios_regs
2318 bios_regs_init();
2319
2320 #undef REG_STRUCT
2321 #define REG_STRUCT clk_src_regs
2322 clk_src_regs_init(0, A),
2323 clk_src_regs_init(1, B),
2324 clk_src_regs_init(2, C),
2325 clk_src_regs_init(3, D),
2326 clk_src_regs_init(4, E);
2327
2328 #undef REG_STRUCT
2329 #define REG_STRUCT abm_regs
2330 abm_regs_init(0),
2331 abm_regs_init(1),
2332 abm_regs_init(2),
2333 abm_regs_init(3);
2334
2335 #undef REG_STRUCT
2336 #define REG_STRUCT dccg_regs
2337 dccg_regs_init();
2338
2339 ctx->dc_bios->regs = &bios_regs;
2340
2341 pool->base.res_cap = &res_cap_dcn32;
2342 /* max number of pipes for ASIC before checking for pipe fuses */
2343 num_pipes = pool->base.res_cap->num_timing_generator;
2344 pipe_fuses = read_pipe_fuses(ctx);
2345
2346 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2347 if (pipe_fuses & 1 << i)
2348 num_pipes--;
2349
2350 if (pipe_fuses & 1)
2351 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2352
2353 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2354 ASSERT(0); //Entire DCN is harvested!
2355
2356 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2357 * value will be changed, update max_num_dpp and max_num_otg for dml.
2358 */
2359 dcn3_2_ip.max_num_dpp = num_pipes;
2360 dcn3_2_ip.max_num_otg = num_pipes;
2361
2362 pool->base.funcs = &dcn32_res_pool_funcs;
2363
2364 /*************************************************
2365 * Resource + asic cap harcoding *
2366 *************************************************/
2367 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2368 pool->base.timing_generator_count = num_pipes;
2369 pool->base.pipe_count = num_pipes;
2370 pool->base.mpcc_count = num_pipes;
2371 dc->caps.max_downscale_ratio = 600;
2372 dc->caps.i2c_speed_in_khz = 100;
2373 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2374 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
2375 dc->caps.max_cursor_size = 64;
2376 /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */
2377 dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64
2378 dc->caps.min_horizontal_blanking_period = 80;
2379 dc->caps.dmdata_alloc_size = 2048;
2380 dc->caps.mall_size_per_mem_channel = 4;
2381 /* total size = mall per channel * num channels * 1024 * 1024 */
2382 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2383 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2384
2385 dc->caps.cache_line_size = 64;
2386 dc->caps.cache_num_ways = 16;
2387
2388 /* Calculate the available MALL space */
2389 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
2390 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2391 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2392 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2393
2394 dc->caps.subvp_fw_processing_delay_us = 15;
2395 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2396 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2397 dc->caps.subvp_swath_height_margin_lines = 16;
2398 dc->caps.subvp_pstate_allow_width_us = 20;
2399 dc->caps.subvp_vertical_int_margin_us = 30;
2400 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2401
2402 dc->caps.max_slave_planes = 2;
2403 dc->caps.max_slave_yuv_planes = 2;
2404 dc->caps.max_slave_rgb_planes = 2;
2405 dc->caps.post_blend_color_processing = true;
2406 dc->caps.force_dp_tps4_for_cp2520 = true;
2407 if (dc->config.forceHBR2CP2520)
2408 dc->caps.force_dp_tps4_for_cp2520 = false;
2409 dc->caps.hdmi_hpo = true;
2410 dc->caps.dp_hpo = true;
2411 dc->caps.dp_hdmi21_pcon_support = true;
2412 dc->caps.edp_dsc_support = true;
2413 dc->caps.extended_aux_timeout_support = true;
2414 dc->caps.dmcub_support = true;
2415 dc->caps.seamless_odm = true;
2416 dc->caps.max_v_total = (1 << 15) - 1;
2417 dc->caps.vtotal_limited_by_fp2 = true;
2418
2419 /* Color pipeline capabilities */
2420 dc->caps.color.dpp.dcn_arch = 1;
2421 dc->caps.color.dpp.input_lut_shared = 0;
2422 dc->caps.color.dpp.icsc = 1;
2423 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2424 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2425 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2426 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2427 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2428 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2429 dc->caps.color.dpp.post_csc = 1;
2430 dc->caps.color.dpp.gamma_corr = 1;
2431 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2432 dc->caps.color.dpp.upsp_pre_scaler = 0;
2433
2434 dc->caps.color.dpp.hw_3d_lut = 0;
2435 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2436 // no OGAM ROM on DCN2 and later ASICs
2437 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2438 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2439 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2440 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2441 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2442 dc->caps.color.dpp.ocsc = 0;
2443
2444 dc->caps.color.mpc.gamut_remap = 1;
2445 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2446 dc->caps.color.mpc.ogam_ram = 1;
2447 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2448 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2449 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2450 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2451 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2452 dc->caps.color.mpc.ocsc = 1;
2453 dc->caps.color.mpc.preblend = true;
2454 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2455
2456 /* Use pipe context based otg sync logic */
2457 dc->config.use_pipe_ctx_sync_logic = true;
2458
2459 dc->config.dc_mode_clk_limit_support = true;
2460 dc->config.enable_windowed_mpo_odm = true;
2461 dc->config.disable_hbr_audio_dp2 = true;
2462 /* read VBIOS LTTPR caps */
2463 {
2464 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2465 enum bp_result bp_query_result;
2466 uint8_t is_vbios_lttpr_enable = 0;
2467
2468 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2469 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2470 }
2471
2472 /* interop bit is implicit */
2473 {
2474 dc->caps.vbios_lttpr_aware = true;
2475 }
2476 }
2477 dc->check_config = config_defaults;
2478
2479 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2480 dc->debug = debug_defaults_drv;
2481
2482 // Init the vm_helper
2483 if (dc->vm_helper)
2484 vm_helper_init(dc->vm_helper, 16);
2485
2486 /*************************************************
2487 * Create resources *
2488 *************************************************/
2489
2490 /* Clock Sources for Pixel Clock*/
2491 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2492 dcn32_clock_source_create(ctx, ctx->dc_bios,
2493 CLOCK_SOURCE_COMBO_PHY_PLL0,
2494 &clk_src_regs[0], false);
2495 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2496 dcn32_clock_source_create(ctx, ctx->dc_bios,
2497 CLOCK_SOURCE_COMBO_PHY_PLL1,
2498 &clk_src_regs[1], false);
2499 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2500 dcn32_clock_source_create(ctx, ctx->dc_bios,
2501 CLOCK_SOURCE_COMBO_PHY_PLL2,
2502 &clk_src_regs[2], false);
2503 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2504 dcn32_clock_source_create(ctx, ctx->dc_bios,
2505 CLOCK_SOURCE_COMBO_PHY_PLL3,
2506 &clk_src_regs[3], false);
2507 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2508 dcn32_clock_source_create(ctx, ctx->dc_bios,
2509 CLOCK_SOURCE_COMBO_PHY_PLL4,
2510 &clk_src_regs[4], false);
2511
2512 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2513
2514 /* todo: not reuse phy_pll registers */
2515 pool->base.dp_clock_source =
2516 dcn32_clock_source_create(ctx, ctx->dc_bios,
2517 CLOCK_SOURCE_ID_DP_DTO,
2518 &clk_src_regs[0], true);
2519
2520 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2521 if (pool->base.clock_sources[i] == NULL) {
2522 dm_error("DC: failed to create clock sources!\n");
2523 BREAK_TO_DEBUGGER();
2524 goto create_fail;
2525 }
2526 }
2527
2528 /* DCCG */
2529 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2530 if (pool->base.dccg == NULL) {
2531 dm_error("DC: failed to create dccg!\n");
2532 BREAK_TO_DEBUGGER();
2533 goto create_fail;
2534 }
2535
2536 /* DML */
2537 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2538
2539 /* IRQ Service */
2540 init_data.ctx = dc->ctx;
2541 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2542 if (!pool->base.irqs)
2543 goto create_fail;
2544
2545 /* HUBBUB */
2546 pool->base.hubbub = dcn32_hubbub_create(ctx);
2547 if (pool->base.hubbub == NULL) {
2548 BREAK_TO_DEBUGGER();
2549 dm_error("DC: failed to create hubbub!\n");
2550 goto create_fail;
2551 }
2552
2553 /* DIO */
2554 pool->base.dio = dcn32_dio_create(ctx);
2555 if (pool->base.dio == NULL) {
2556 BREAK_TO_DEBUGGER();
2557 dm_error("DC: failed to create dio!\n");
2558 goto create_fail;
2559 }
2560
2561 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2562 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2563
2564 /* if pipe is disabled, skip instance of HW pipe,
2565 * i.e, skip ASIC register instance
2566 */
2567 if (pipe_fuses & 1 << i)
2568 continue;
2569
2570 /* HUBPs */
2571 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2572 if (pool->base.hubps[j] == NULL) {
2573 BREAK_TO_DEBUGGER();
2574 dm_error(
2575 "DC: failed to create hubps!\n");
2576 goto create_fail;
2577 }
2578
2579 /* DPPs */
2580 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2581 if (pool->base.dpps[j] == NULL) {
2582 BREAK_TO_DEBUGGER();
2583 dm_error(
2584 "DC: failed to create dpps!\n");
2585 goto create_fail;
2586 }
2587
2588 /* OPPs */
2589 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2590 if (pool->base.opps[j] == NULL) {
2591 BREAK_TO_DEBUGGER();
2592 dm_error(
2593 "DC: failed to create output pixel processor!\n");
2594 goto create_fail;
2595 }
2596
2597 /* TGs */
2598 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2599 ctx, i);
2600 if (pool->base.timing_generators[j] == NULL) {
2601 BREAK_TO_DEBUGGER();
2602 dm_error("DC: failed to create tg!\n");
2603 goto create_fail;
2604 }
2605
2606 /* ABMs */
2607 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2608 &abm_regs[i],
2609 &abm_shift,
2610 &abm_mask);
2611 if (pool->base.multiple_abms[j] == NULL) {
2612 dm_error("DC: failed to create abm for pipe %d!\n", i);
2613 BREAK_TO_DEBUGGER();
2614 goto create_fail;
2615 }
2616
2617 /* index for resource pool arrays for next valid pipe */
2618 j++;
2619 }
2620
2621 /* PSR */
2622 pool->base.psr = dmub_psr_create(ctx);
2623 if (pool->base.psr == NULL) {
2624 dm_error("DC: failed to create psr obj!\n");
2625 BREAK_TO_DEBUGGER();
2626 goto create_fail;
2627 }
2628
2629 /* MPCCs */
2630 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2631 if (pool->base.mpc == NULL) {
2632 BREAK_TO_DEBUGGER();
2633 dm_error("DC: failed to create mpc!\n");
2634 goto create_fail;
2635 }
2636
2637 /* DSCs */
2638 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2639 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2640 if (pool->base.dscs[i] == NULL) {
2641 BREAK_TO_DEBUGGER();
2642 dm_error("DC: failed to create display stream compressor %d!\n", i);
2643 goto create_fail;
2644 }
2645 }
2646
2647 /* DWB */
2648 if (!dcn32_dwbc_create(ctx, &pool->base)) {
2649 BREAK_TO_DEBUGGER();
2650 dm_error("DC: failed to create dwbc!\n");
2651 goto create_fail;
2652 }
2653
2654 /* MMHUBBUB */
2655 if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2656 BREAK_TO_DEBUGGER();
2657 dm_error("DC: failed to create mcif_wb!\n");
2658 goto create_fail;
2659 }
2660
2661 /* AUX and I2C */
2662 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2663 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2664 if (pool->base.engines[i] == NULL) {
2665 BREAK_TO_DEBUGGER();
2666 dm_error(
2667 "DC:failed to create aux engine!!\n");
2668 goto create_fail;
2669 }
2670 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2671 if (pool->base.hw_i2cs[i] == NULL) {
2672 BREAK_TO_DEBUGGER();
2673 dm_error(
2674 "DC:failed to create hw i2c!!\n");
2675 goto create_fail;
2676 }
2677 pool->base.sw_i2cs[i] = NULL;
2678 }
2679
2680 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2681 if (!resource_construct(num_virtual_links, dc, &pool->base,
2682 &res_create_funcs))
2683 goto create_fail;
2684
2685 /* HW Sequencer init functions and Plane caps */
2686 dcn32_hw_sequencer_init_functions(dc);
2687
2688 dc->caps.max_planes = pool->base.pipe_count;
2689
2690 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2691 dc->caps.planes[i] = plane_cap;
2692
2693 dc->caps.max_odm_combine_factor = 4;
2694
2695 dc->cap_funcs = cap_funcs;
2696
2697 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2698 ddc_init_data.ctx = dc->ctx;
2699 ddc_init_data.link = NULL;
2700 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2701 ddc_init_data.id.enum_id = 0;
2702 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2703 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2704 } else {
2705 pool->base.oem_device = NULL;
2706 }
2707
2708 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2709 dc->dml2_options.use_native_soc_bb_construction = true;
2710 dc->dml2_options.minimize_dispclk_using_odm = true;
2711
2712 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2713 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2714 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2715 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2716
2717 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2718 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2719 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2720 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2721
2722 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2723 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2724
2725 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2726 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2727 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2728 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2729 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2730 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2731 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2732
2733 dc->dml2_options.max_segments_per_hubp = 18;
2734 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2735 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2736
2737 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
2738 dc->config.sdpif_request_limit_words_per_umc = 16;
2739
2740 /* init DC limited DML2 options */
2741 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2742 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2743
2744 return true;
2745
2746 create_fail:
2747
2748 dcn32_resource_destruct(pool);
2749
2750 return false;
2751 }
2752
dcn32_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2753 struct resource_pool *dcn32_create_resource_pool(
2754 const struct dc_init_data *init_data,
2755 struct dc *dc)
2756 {
2757 struct dcn32_resource_pool *pool =
2758 kzalloc_obj(struct dcn32_resource_pool);
2759
2760 if (!pool)
2761 return NULL;
2762
2763 if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2764 return &pool->base;
2765
2766 BREAK_TO_DEBUGGER();
2767 kfree(pool);
2768 return NULL;
2769 }
2770
2771 /*
2772 * Find the most optimal free pipe from res_ctx, which could be used as a
2773 * secondary dpp pipe for input opp head pipe.
2774 *
2775 * a free pipe - a pipe in input res_ctx not yet used for any streams or
2776 * planes.
2777 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending
2778 * tree. This is typical used for rendering MPO planes or additional offset
2779 * areas in MPCC combine.
2780 *
2781 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe
2782 * -------------------------------------------------------------------------
2783 *
2784 * PROBLEM:
2785 *
2786 * 1. There is a hardware limitation that a secondary DPP pipe cannot be
2787 * transferred from one MPC blending tree to the other in a single frame.
2788 * Otherwise it could cause glitches on the screen.
2789 *
2790 * For instance, we cannot transition from state 1 to state 2 in one frame. This
2791 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to
2792 * PIPE2's MPC blending tree, which is not supported by hardware.
2793 * To support this transition we need to first remove PIPE1 from PIPE0's MPC
2794 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree
2795 * in the next frame. This is not optimal as it will delay the flip for two
2796 * frames.
2797 *
2798 * State 1:
2799 * PIPE0 -- secondary DPP pipe --> (PIPE1)
2800 * PIPE2 -- secondary DPP pipe --> NONE
2801 *
2802 * State 2:
2803 * PIPE0 -- secondary DPP pipe --> NONE
2804 * PIPE2 -- secondary DPP pipe --> (PIPE1)
2805 *
2806 * 2. We want to in general minimize the unnecessary changes in pipe topology.
2807 * If a pipe is already added in current blending tree and there are no changes
2808 * to plane topology, we don't want to swap it with another free pipe
2809 * unnecessarily in every update. Powering up and down a pipe would require a
2810 * full update which delays the flip for 1 frame. If we use the original pipe
2811 * we don't have to toggle its power. So we can flip faster.
2812 */
dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_opp_head)2813 int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2814 const struct resource_context *cur_res_ctx,
2815 struct resource_context *new_res_ctx,
2816 const struct resource_pool *pool,
2817 const struct pipe_ctx *new_opp_head)
2818 {
2819 const struct pipe_ctx *cur_opp_head;
2820 int free_pipe_idx;
2821
2822 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];
2823 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree(
2824 cur_res_ctx, new_res_ctx, cur_opp_head);
2825
2826 /* Up until here if we have not found a free secondary pipe, we will
2827 * need to wait for at least one frame to complete the transition
2828 * sequence.
2829 */
2830 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2831 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2832 cur_res_ctx, new_res_ctx, pool);
2833
2834 /* Up until here if we have not found a free secondary pipe, we will
2835 * need to wait for at least two frames to complete the transition
2836 * sequence. It really doesn't matter which pipe we decide take from
2837 * current enabled pipes. It won't save our frame time when we swap only
2838 * one pipe or more pipes.
2839 */
2840 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2841 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
2842 cur_res_ctx, new_res_ctx, pool);
2843
2844 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2845 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2846
2847 return free_pipe_idx;
2848 }
2849
find_idle_secondary_pipe_check_mpo(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)2850 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2851 struct resource_context *res_ctx,
2852 const struct resource_pool *pool,
2853 const struct pipe_ctx *primary_pipe)
2854 {
2855 int i;
2856 struct pipe_ctx *secondary_pipe = NULL;
2857 struct pipe_ctx *next_odm_mpo_pipe = NULL;
2858 int primary_index, preferred_pipe_idx;
2859 struct pipe_ctx *old_primary_pipe = NULL;
2860
2861 /*
2862 * Modified from find_idle_secondary_pipe
2863 * With windowed MPO and ODM, we want to avoid the case where we want a
2864 * free pipe for the left side but the free pipe is being used on the
2865 * right side.
2866 * Add check on current_state if the primary_pipe is the left side,
2867 * to check the right side ( primary_pipe->next_odm_pipe ) to see if
2868 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2869 * - If so, then don't use this pipe
2870 * EXCEPTION - 3 plane ( 2 MPO plane ) case
2871 * - in this case, the primary pipe has already gotten a free pipe for the
2872 * MPO window in the left
2873 * - when it tries to get a free pipe for the MPO window on the right,
2874 * it will see that it is already assigned to the right side
2875 * ( primary_pipe->next_odm_pipe ). But in this case, we want this
2876 * free pipe, since it will be for the right side. So add an
2877 * additional condition, that skipping the free pipe on the right only
2878 * applies if the primary pipe has no bottom pipe currently assigned
2879 */
2880 if (primary_pipe) {
2881 primary_index = primary_pipe->pipe_idx;
2882 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2883 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2884 && (!primary_pipe->bottom_pipe))
2885 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2886
2887 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2888 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2889 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2890 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2891 secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
2892 }
2893 }
2894
2895 /*
2896 * search backwards for the second pipe to keep pipe
2897 * assignment more consistent
2898 */
2899 if (!secondary_pipe)
2900 for (i = pool->pipe_count - 1; i >= 0; i--) {
2901 if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2902 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2903 secondary_pipe = &res_ctx->pipe_ctx[i];
2904 secondary_pipe->pipe_idx = (uint8_t)i;
2905 break;
2906 }
2907 }
2908
2909 return secondary_pipe;
2910 }
2911
dcn32_acquire_idle_pipe_for_head_pipe_in_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream,const struct pipe_ctx * head_pipe)2912 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2913 struct dc_state *state,
2914 const struct resource_pool *pool,
2915 struct dc_stream_state *stream,
2916 const struct pipe_ctx *head_pipe)
2917 {
2918 struct resource_context *res_ctx = &state->res_ctx;
2919 struct pipe_ctx *idle_pipe, *pipe;
2920 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2921 int head_index;
2922
2923 if (!head_pipe) {
2924 ASSERT(0);
2925 return NULL;
2926 }
2927
2928 /*
2929 * Modified from dcn20_acquire_idle_pipe_for_layer
2930 * Check if head_pipe in old_context already has bottom_pipe allocated.
2931 * - If so, check if that pipe is available in the current context.
2932 * -- If so, reuse pipe from old_context
2933 */
2934 head_index = head_pipe->pipe_idx;
2935 pipe = &old_ctx->pipe_ctx[head_index];
2936 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2937 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2938 idle_pipe->pipe_idx = (uint8_t)pipe->bottom_pipe->pipe_idx;
2939 } else {
2940 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2941 if (!idle_pipe)
2942 return NULL;
2943 }
2944
2945 idle_pipe->stream = head_pipe->stream;
2946 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2947 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2948
2949 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2950 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2951 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2952 idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
2953
2954 return idle_pipe;
2955 }
2956
find_optimal_free_pipe_as_secondary_opp_head(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_otg_master)2957 static int find_optimal_free_pipe_as_secondary_opp_head(
2958 const struct resource_context *cur_res_ctx,
2959 struct resource_context *new_res_ctx,
2960 const struct resource_pool *pool,
2961 const struct pipe_ctx *new_otg_master)
2962 {
2963 const struct pipe_ctx *cur_otg_master;
2964 int free_pipe_idx;
2965
2966 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
2967 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
2968 cur_res_ctx, new_res_ctx, cur_otg_master);
2969
2970 /* Up until here if we have not found a free secondary pipe, we will
2971 * need to wait for at least one frame to complete the transition
2972 * sequence.
2973 */
2974 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2975 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2976 cur_res_ctx, new_res_ctx, pool);
2977
2978 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2979 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2980
2981 return free_pipe_idx;
2982 }
2983
dcn32_acquire_free_pipe_as_secondary_dpp_pipe(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)2984 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
2985 const struct dc_state *cur_ctx,
2986 struct dc_state *new_ctx,
2987 const struct resource_pool *pool,
2988 const struct pipe_ctx *opp_head_pipe)
2989 {
2990
2991 int free_pipe_idx;
2992 struct pipe_ctx *free_pipe;
2993
2994 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
2995 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2996 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2997
2998 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2999 &cur_ctx->res_ctx, &new_ctx->res_ctx,
3000 pool, opp_head_pipe);
3001 if (free_pipe_idx >= 0) {
3002 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
3003 free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
3004 free_pipe->stream = opp_head_pipe->stream;
3005 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
3006 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
3007
3008 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
3009 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
3010 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
3011 free_pipe->plane_res.mpcc_inst =
3012 (uint8_t)pool->dpps[free_pipe->pipe_idx]->inst;
3013 } else {
3014 ASSERT(opp_head_pipe);
3015 free_pipe = NULL;
3016 }
3017
3018 return free_pipe;
3019 }
3020
dcn32_acquire_free_pipe_as_secondary_opp_head(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * otg_master)3021 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
3022 const struct dc_state *cur_ctx,
3023 struct dc_state *new_ctx,
3024 const struct resource_pool *pool,
3025 const struct pipe_ctx *otg_master)
3026 {
3027 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
3028 &cur_ctx->res_ctx, &new_ctx->res_ctx,
3029 pool, otg_master);
3030 struct pipe_ctx *free_pipe;
3031
3032 if (free_pipe_idx >= 0) {
3033 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
3034 free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
3035 free_pipe->stream = otg_master->stream;
3036 free_pipe->stream_res.tg = otg_master->stream_res.tg;
3037 free_pipe->stream_res.dsc = NULL;
3038 free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
3039 free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
3040 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
3041 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
3042 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
3043 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
3044 free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst;
3045 free_pipe->dsc_padding_params = otg_master->dsc_padding_params;
3046 if (free_pipe->stream->timing.flags.DSC == 1) {
3047 dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
3048 &new_ctx->res_ctx,
3049 &free_pipe->stream_res.dsc,
3050 free_pipe_idx);
3051 ASSERT(free_pipe->stream_res.dsc);
3052 if (free_pipe->stream_res.dsc == NULL) {
3053 memset(free_pipe, 0, sizeof(*free_pipe));
3054 free_pipe = NULL;
3055 }
3056 }
3057 } else {
3058 ASSERT(otg_master);
3059 free_pipe = NULL;
3060 }
3061
3062 return free_pipe;
3063 }
3064
dcn32_calc_num_avail_chans_for_mall(struct dc * dc,int num_chans)3065 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
3066 {
3067 /*
3068 * DCN32 and DCN321 SKUs may have different sizes for MALL
3069 * but we may not be able to access all the MALL space.
3070 * If the num_chans is power of 2, then we can access all
3071 * of the available MALL space. Otherwise, we can only
3072 * access:
3073 *
3074 * max_cab_size_in_bytes = total_cache_size_in_bytes *
3075 * ((2^floor(log2(num_chans)))/num_chans)
3076 *
3077 * Calculating the MALL sizes for all available SKUs, we
3078 * have come up with the follow simplified check.
3079 * - we have max_chans which provides the max MALL size.
3080 * Each chans supports 4MB of MALL so:
3081 *
3082 * total_cache_size_in_bytes = max_chans * 4 MB
3083 *
3084 * - we have avail_chans which shows the number of channels
3085 * we can use if we can't access the entire MALL space.
3086 * It is generally half of max_chans
3087 * - so we use the following checks:
3088 *
3089 * if (num_chans == max_chans), return max_chans
3090 * if (num_chans < max_chans), return avail_chans
3091 *
3092 * - exception is GC_11_0_0 where we can't access max_chans,
3093 * so we define max_avail_chans as the maximum available
3094 * MALL space
3095 *
3096 */
3097 int gc_11_0_0_max_chans = 48;
3098 int gc_11_0_0_max_avail_chans = 32;
3099 int gc_11_0_0_avail_chans = 16;
3100 int gc_11_0_3_max_chans = 16;
3101 int gc_11_0_3_avail_chans = 8;
3102 int gc_11_0_2_max_chans = 8;
3103 int gc_11_0_2_avail_chans = 4;
3104
3105 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {
3106 return (num_chans == gc_11_0_0_max_chans) ?
3107 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;
3108 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {
3109 return (num_chans == gc_11_0_2_max_chans) ?
3110 gc_11_0_2_max_chans : gc_11_0_2_avail_chans;
3111 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {
3112 return (num_chans == gc_11_0_3_max_chans) ?
3113 gc_11_0_3_max_chans : gc_11_0_3_avail_chans;
3114 }
3115 }
3116