1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn30_hwseq.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30/dcn30_mpc.h"
35 #include "dcn30/dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30/dcn30_cm_common.h"
38 #include "reg_helper.h"
39 #include "dcn10/dcn10_hubbub.h"
40 #include "abm.h"
41 #include "clk_mgr.h"
42 #include "hubp.h"
43 #include "dchubbub.h"
44 #include "timing_generator.h"
45 #include "opp.h"
46 #include "ipp.h"
47 #include "mpc.h"
48 #include "mcif_wb.h"
49 #include "dc_dmub_srv.h"
50 #include "link_hwss.h"
51 #include "dpcd_defs.h"
52 #include "dcn20/dcn20_hwseq.h"
53 #include "dcn30/dcn30_resource.h"
54 #include "link_service.h"
55 #include "dc_state_priv.h"
56 #include "dio/dcn10/dcn10_dio.h"
57
58 #define TO_DCN_DCCG(dccg)\
59 container_of(dccg, struct dcn_dccg, base)
60
61 #define DC_LOGGER_INIT(logger)
62
63 #define CTX \
64 hws->ctx
65 #define REG(reg)\
66 hws->regs->reg
67 #define DC_LOGGER \
68 dc->ctx->logger
69
70
71 #undef FN
72 #define FN(reg_name, field_name) \
73 hws->shifts->field_name, hws->masks->field_name
74
dcn30_log_color_state(struct dc * dc,struct dc_log_buffer_ctx * log_ctx)75 void dcn30_log_color_state(struct dc *dc,
76 struct dc_log_buffer_ctx *log_ctx)
77 {
78 struct dc_context *dc_ctx = dc->ctx;
79 struct resource_pool *pool = dc->res_pool;
80 bool is_gamut_remap_available = false;
81 int i;
82
83 DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode"
84 " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode"
85 " GAMUT adjust "
86 "C11 C12 C13 C14 "
87 "C21 C22 C23 C24 "
88 "C31 C32 C33 C34 \n");
89
90 for (i = 0; i < pool->pipe_count; i++) {
91 struct dpp *dpp = pool->dpps[i];
92 struct dcn_dpp_state s = {0};
93
94 dpp->funcs->dpp_read_state(dpp, &s);
95
96 if (dpp->funcs->dpp_get_gamut_remap) {
97 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
98 is_gamut_remap_available = true;
99 }
100
101 if (!s.is_enabled)
102 continue;
103
104 DTN_INFO("[%2d]: %7x %13s %8s %11s %10s %15s %10s %9s",
105 dpp->inst,
106 s.pre_dgam_mode,
107 (s.pre_dgam_select == 0) ? "sRGB" :
108 ((s.pre_dgam_select == 1) ? "Gamma 2.2" :
109 ((s.pre_dgam_select == 2) ? "Gamma 2.4" :
110 ((s.pre_dgam_select == 3) ? "Gamma 2.6" :
111 ((s.pre_dgam_select == 4) ? "BT.709" :
112 ((s.pre_dgam_select == 5) ? "PQ" :
113 ((s.pre_dgam_select == 6) ? "HLG" :
114 "Unknown")))))),
115 (s.gamcor_mode == 0) ? "Bypass" :
116 ((s.gamcor_mode == 1) ? "RAM A" :
117 "RAM B"),
118 (s.shaper_lut_mode == 1) ? "RAM A" :
119 ((s.shaper_lut_mode == 2) ? "RAM B" :
120 "Bypass"),
121 (s.lut3d_mode == 1) ? "RAM A" :
122 ((s.lut3d_mode == 2) ? "RAM B" :
123 "Bypass"),
124 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
125 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
126 (s.rgam_lut_mode == 0) ? "Bypass" :
127 ((s.rgam_lut_mode == 1) ? "RAM A" :
128 "RAM B"));
129
130 if (is_gamut_remap_available) {
131 DTN_INFO(" %12s "
132 "%010lld %010lld %010lld %010lld "
133 "%010lld %010lld %010lld %010lld "
134 "%010lld %010lld %010lld %010lld",
135
136 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
137 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
138 "SW"),
139 s.gamut_remap.temperature_matrix[0].value,
140 s.gamut_remap.temperature_matrix[1].value,
141 s.gamut_remap.temperature_matrix[2].value,
142 s.gamut_remap.temperature_matrix[3].value,
143 s.gamut_remap.temperature_matrix[4].value,
144 s.gamut_remap.temperature_matrix[5].value,
145 s.gamut_remap.temperature_matrix[6].value,
146 s.gamut_remap.temperature_matrix[7].value,
147 s.gamut_remap.temperature_matrix[8].value,
148 s.gamut_remap.temperature_matrix[9].value,
149 s.gamut_remap.temperature_matrix[10].value,
150 s.gamut_remap.temperature_matrix[11].value);
151 }
152
153 DTN_INFO("\n");
154 }
155 DTN_INFO("\n");
156 DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
157 " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
158 " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
159 " blnd_lut:%d oscs:%d\n\n",
160 dc->caps.color.dpp.input_lut_shared,
161 dc->caps.color.dpp.icsc,
162 dc->caps.color.dpp.dgam_ram,
163 dc->caps.color.dpp.dgam_rom_caps.srgb,
164 dc->caps.color.dpp.dgam_rom_caps.bt2020,
165 dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
166 dc->caps.color.dpp.dgam_rom_caps.pq,
167 dc->caps.color.dpp.dgam_rom_caps.hlg,
168 dc->caps.color.dpp.post_csc,
169 dc->caps.color.dpp.gamma_corr,
170 dc->caps.color.dpp.dgam_rom_for_yuv,
171 dc->caps.color.dpp.hw_3d_lut,
172 dc->caps.color.dpp.ogam_ram,
173 dc->caps.color.dpp.ocsc);
174
175 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"
176 " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT"
177 " GAMUT adjust "
178 "C11 C12 C13 C14 "
179 "C21 C22 C23 C24 "
180 "C31 C32 C33 C34 \n");
181
182 for (i = 0; i < pool->mpcc_count; i++) {
183 struct mpcc_state s = {0};
184
185 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
186 mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);
187
188 if (s.opp_id != 0xf)
189 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %11s %11s %16s %11s %10s %9s"
190 " %-12s "
191 "%010lld %010lld %010lld %010lld "
192 "%010lld %010lld %010lld %010lld "
193 "%010lld %010lld %010lld %010lld\n",
194 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
195 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
196 s.idle,
197 (s.shaper_lut_mode == 1) ? "RAM A" :
198 ((s.shaper_lut_mode == 2) ? "RAM B" :
199 "Bypass"),
200 (s.lut3d_mode == 1) ? "RAM A" :
201 ((s.lut3d_mode == 2) ? "RAM B" :
202 "Bypass"),
203 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
204 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
205 (s.rgam_mode == 0) ? "Bypass" :
206 ((s.rgam_mode == 2) ? "RAM" :
207 "Unknown"),
208 (s.rgam_mode == 1) ? "B" : "A",
209 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
210 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
211 "SW"),
212 s.gamut_remap.temperature_matrix[0].value,
213 s.gamut_remap.temperature_matrix[1].value,
214 s.gamut_remap.temperature_matrix[2].value,
215 s.gamut_remap.temperature_matrix[3].value,
216 s.gamut_remap.temperature_matrix[4].value,
217 s.gamut_remap.temperature_matrix[5].value,
218 s.gamut_remap.temperature_matrix[6].value,
219 s.gamut_remap.temperature_matrix[7].value,
220 s.gamut_remap.temperature_matrix[8].value,
221 s.gamut_remap.temperature_matrix[9].value,
222 s.gamut_remap.temperature_matrix[10].value,
223 s.gamut_remap.temperature_matrix[11].value);
224
225 }
226 DTN_INFO("\n");
227 DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
228 dc->caps.color.mpc.gamut_remap,
229 dc->caps.color.mpc.num_3dluts,
230 dc->caps.color.mpc.ogam_ram,
231 dc->caps.color.mpc.ocsc);
232 }
233
dcn30_set_blend_lut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)234 bool dcn30_set_blend_lut(
235 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
236 {
237 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
238 bool result = true;
239 const struct pwl_params *blend_lut = NULL;
240
241 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
242 blend_lut = &plane_state->blend_tf.pwl;
243 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
244 result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
245 &plane_state->blend_tf, &dpp_base->regamma_params, false);
246 if (!result)
247 return result;
248
249 blend_lut = &dpp_base->regamma_params;
250 }
251 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
252
253 return result;
254 }
255
dcn30_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)256 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
257 const struct dc_stream_state *stream)
258 {
259 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
260 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
261 struct dc *dc = pipe_ctx->stream->ctx->dc;
262 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
263 bool result = false;
264 int acquired_rmu = 0;
265 int mpcc_id_projected = 0;
266
267 const struct pwl_params *shaper_lut = NULL;
268 //get the shaper lut params
269 if (stream->func_shaper) {
270 if (stream->func_shaper->type == TF_TYPE_HWPWL) {
271 shaper_lut = &stream->func_shaper->pwl;
272 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
273 cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
274 &dpp_base->shaper_params, true);
275 shaper_lut = &dpp_base->shaper_params;
276 }
277 }
278
279 if (stream->lut3d_func &&
280 stream->lut3d_func->state.bits.initialized == 1 &&
281 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
282 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
283 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
284 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
285 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
286 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
287 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
288 if (mpcc_id_projected != mpcc_id)
289 BREAK_TO_DEBUGGER();
290 /* find the reason why logical layer assigned a different
291 * mpcc_id into acquire_post_bldn_3dlut
292 */
293 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
294 stream->lut3d_func->state.bits.rmu_mux_num);
295 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
296 BREAK_TO_DEBUGGER();
297
298 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
299 stream->lut3d_func->state.bits.rmu_mux_num);
300 if (!result)
301 DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);
302
303 result = mpc->funcs->program_shaper(mpc, shaper_lut,
304 stream->lut3d_func->state.bits.rmu_mux_num);
305 if (!result)
306 DC_LOG_ERROR("%s: program_shaper failed\n", __func__);
307
308 } else {
309 // loop through the available mux and release the requested mpcc_id
310 mpc->funcs->release_rmu(mpc, mpcc_id);
311 }
312
313 return result;
314 }
315
dcn30_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)316 bool dcn30_set_input_transfer_func(struct dc *dc,
317 struct pipe_ctx *pipe_ctx,
318 const struct dc_plane_state *plane_state)
319 {
320 struct dce_hwseq *hws = dc->hwseq;
321 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
322 enum dc_transfer_func_predefined tf;
323 bool result = true;
324 const struct pwl_params *params = NULL;
325
326 if (dpp_base == NULL || plane_state == NULL)
327 return false;
328
329 tf = TRANSFER_FUNCTION_UNITY;
330
331 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)
332 tf = plane_state->in_transfer_func.tf;
333
334 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
335
336 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
337 params = &plane_state->in_transfer_func.pwl;
338 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
339 cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
340 &plane_state->in_transfer_func,
341 &dpp_base->degamma_params, false))
342 params = &dpp_base->degamma_params;
343
344 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
345
346 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
347 if (dpp_base->funcs->dpp_program_blnd_lut)
348 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
349 if (dpp_base->funcs->dpp_program_shaper_lut &&
350 dpp_base->funcs->dpp_program_3dlut)
351 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
352 }
353
354 return result;
355 }
356
dcn30_program_gamut_remap(struct pipe_ctx * pipe_ctx)357 void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
358 {
359 int i = 0;
360 struct dpp_grph_csc_adjustment dpp_adjust;
361 struct mpc_grph_gamut_adjustment mpc_adjust;
362 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
363 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
364
365 memset(&dpp_adjust, 0, sizeof(dpp_adjust));
366 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
367
368 if (pipe_ctx->plane_state &&
369 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
370 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
371 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
372 dpp_adjust.temperature_matrix[i] =
373 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
374 }
375
376 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
377 &dpp_adjust);
378
379 memset(&mpc_adjust, 0, sizeof(mpc_adjust));
380 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
381
382 if (pipe_ctx->top_pipe == NULL) {
383 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
384 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
385 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
386 mpc_adjust.temperature_matrix[i] =
387 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
388 }
389 }
390
391 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
392 }
393
dcn30_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)394 bool dcn30_set_output_transfer_func(struct dc *dc,
395 struct pipe_ctx *pipe_ctx,
396 const struct dc_stream_state *stream)
397 {
398 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
399 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
400 const struct pwl_params *params = NULL;
401 bool ret = false;
402
403 /* program OGAM or 3DLUT only for the top pipe*/
404 if (pipe_ctx->top_pipe == NULL) {
405 /*program rmu shaper and 3dlut in MPC*/
406 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
407 if (ret == false && mpc->funcs->set_output_gamma) {
408 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
409 params = &stream->out_transfer_func.pwl;
410 else if (pipe_ctx->stream->out_transfer_func.type ==
411 TF_TYPE_DISTRIBUTED_POINTS &&
412 cm3_helper_translate_curve_to_hw_format(stream->ctx,
413 &stream->out_transfer_func,
414 &mpc->blender_params, false))
415 params = &mpc->blender_params;
416 /* there are no ROM LUTs in OUTGAM */
417 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)
418 BREAK_TO_DEBUGGER();
419 }
420 }
421
422 if (mpc->funcs->set_output_gamma)
423 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
424 else
425 DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);
426
427 return ret;
428 }
429
dcn30_set_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)430 static void dcn30_set_writeback(
431 struct dc *dc,
432 struct dc_writeback_info *wb_info,
433 struct dc_state *context)
434 {
435 struct mcif_wb *mcif_wb;
436 struct mcif_buf_params *mcif_buf_params;
437
438 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
439 ASSERT(wb_info->wb_enabled);
440 ASSERT(wb_info->mpcc_inst >= 0);
441 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
442 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
443 mcif_buf_params = &wb_info->mcif_buf_params;
444
445 /* set DWB MPC mux */
446 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
447 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
448 /* set MCIF_WB buffer and arbitration configuration */
449 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
450 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
451 }
452
dcn30_update_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)453 void dcn30_update_writeback(
454 struct dc *dc,
455 struct dc_writeback_info *wb_info,
456 struct dc_state *context)
457 {
458 struct dwbc *dwb;
459 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
460 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
461 __func__, wb_info->dwb_pipe_inst,\
462 wb_info->mpcc_inst);
463
464 dcn30_set_writeback(dc, wb_info, context);
465
466 /* update DWB */
467 dwb->funcs->update(dwb, &wb_info->dwb_params);
468 }
469
dcn30_mmhubbub_warmup(struct dc * dc,unsigned int num_dwb,struct dc_writeback_info * wb_info)470 bool dcn30_mmhubbub_warmup(
471 struct dc *dc,
472 unsigned int num_dwb,
473 struct dc_writeback_info *wb_info)
474 {
475 struct dwbc *dwb;
476 struct mcif_wb *mcif_wb;
477 struct mcif_warmup_params warmup_params = {0};
478 unsigned int i, i_buf;
479 /* make sure there is no active DWB enabled */
480 for (i = 0; i < num_dwb; i++) {
481 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
482 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
483 /*can not do warmup while any dwb enabled*/
484 return false;
485 }
486 }
487
488 if (wb_info->mcif_warmup_params.p_vmid == 0)
489 return false;
490
491 /*check whether this is new interface: warmup big buffer once*/
492 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
493 wb_info->mcif_warmup_params.region_size != 0) {
494 /*mmhubbub is shared, so it does not matter which MCIF*/
495 mcif_wb = dc->res_pool->mcif_wb[0];
496 /*warmup a big chunk of VM buffer at once*/
497 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
498 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;
499 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
500 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
501
502 if (warmup_params.address_increment == 0)
503 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
504
505 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
506 return true;
507 }
508 /*following is the original: warmup each DWB's mcif buffer*/
509 for (i = 0; i < num_dwb; i++) {
510 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
511 /*warmup is for VM mode only*/
512 if (wb_info[i].mcif_buf_params.p_vmid == 0)
513 return false;
514
515 /* Warmup MCIF_WB */
516 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
517 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
518 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
519 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
520 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
521 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
522 }
523 }
524 return true;
525 }
526
dcn30_enable_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)527 void dcn30_enable_writeback(
528 struct dc *dc,
529 struct dc_writeback_info *wb_info,
530 struct dc_state *context)
531 {
532 struct dwbc *dwb;
533 struct mcif_wb *mcif_wb;
534
535 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
536 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
537
538 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
539 __func__, wb_info->dwb_pipe_inst,\
540 wb_info->mpcc_inst);
541
542 /* Warmup interface */
543 dcn30_mmhubbub_warmup(dc, 1, wb_info);
544
545 /* Update writeback pipe */
546 dcn30_set_writeback(dc, wb_info, context);
547
548 /* Enable MCIF_WB */
549 mcif_wb->funcs->enable_mcif(mcif_wb);
550 /* Enable DWB */
551 dwb->funcs->enable(dwb, &wb_info->dwb_params);
552 }
553
dcn30_disable_writeback(struct dc * dc,unsigned int dwb_pipe_inst)554 void dcn30_disable_writeback(
555 struct dc *dc,
556 unsigned int dwb_pipe_inst)
557 {
558 struct dwbc *dwb;
559 struct mcif_wb *mcif_wb;
560
561 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
562 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
563 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
564 DC_LOG_DWB("%s dwb_pipe_inst = %d",\
565 __func__, dwb_pipe_inst);
566
567 /* disable DWB */
568 dwb->funcs->disable(dwb);
569 /* disable MCIF */
570 mcif_wb->funcs->disable_mcif(mcif_wb);
571 /* disable MPC DWB mux */
572 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
573 }
574
dcn30_program_all_writeback_pipes_in_tree(struct dc * dc,const struct dc_stream_state * stream,struct dc_state * context)575 void dcn30_program_all_writeback_pipes_in_tree(
576 struct dc *dc,
577 const struct dc_stream_state *stream,
578 struct dc_state *context)
579 {
580 struct dc_writeback_info wb_info;
581 struct dwbc *dwb;
582 struct dc_stream_status *stream_status = NULL;
583 int i_wb, i_pipe, i_stream;
584 DC_LOG_DWB("%s", __func__);
585
586 ASSERT(stream);
587 for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
588 if (context->streams[i_stream] == stream) {
589 stream_status = &context->stream_status[i_stream];
590 break;
591 }
592 }
593 ASSERT(stream_status);
594
595 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
596 /* For each writeback pipe */
597 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
598
599 /* copy writeback info to local non-const so mpcc_inst can be set */
600 wb_info = stream->writeback_info[i_wb];
601 if (wb_info.wb_enabled) {
602
603 /* get the MPCC instance for writeback_source_plane */
604 wb_info.mpcc_inst = -1;
605 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
606 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
607
608 if (!pipe_ctx->plane_state)
609 continue;
610
611 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
612 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
613 break;
614 }
615 }
616
617 if (wb_info.mpcc_inst == -1) {
618 /* Disable writeback pipe and disconnect from MPCC
619 * if source plane has been removed
620 */
621 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
622 continue;
623 }
624
625 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
626 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
627 if (dwb->funcs->is_enabled(dwb)) {
628 /* writeback pipe already enabled, only need to update */
629 dc->hwss.update_writeback(dc, &wb_info, context);
630 } else {
631 /* Enable writeback pipe and connect to MPCC */
632 dc->hwss.enable_writeback(dc, &wb_info, context);
633 }
634 } else {
635 /* Disable writeback pipe and disconnect from MPCC */
636 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
637 }
638 }
639 }
640
dcn30_init_hw(struct dc * dc)641 void dcn30_init_hw(struct dc *dc)
642 {
643 struct abm **abms = dc->res_pool->multiple_abms;
644 struct dce_hwseq *hws = dc->hwseq;
645 struct dc_bios *dcb = dc->ctx->dc_bios;
646 struct resource_pool *res_pool = dc->res_pool;
647 int i;
648 int edp_num;
649 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
650 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
651
652 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)
653 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
654
655 // Initialize the dccg
656 if (res_pool->dccg->funcs->dccg_init)
657 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
658
659 if (!dcb->funcs->is_accelerated_mode(dcb)) {
660 hws->funcs.bios_golden_init(dc);
661 hws->funcs.disable_vga(dc->hwseq);
662 }
663
664 if (dc->debug.enable_mem_low_power.bits.dmcu) {
665 // Force ERAM to shutdown if DMCU is not enabled
666 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
667 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
668 }
669 }
670
671 // Set default OPTC memory power states
672 if (dc->debug.enable_mem_low_power.bits.optc) {
673 // Shutdown when unassigned and light sleep in VBLANK
674 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
675 }
676
677 if (dc->debug.enable_mem_low_power.bits.vga) {
678 // Power down VGA memory
679 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
680 }
681
682 if (dc->ctx->dc_bios->fw_info_valid) {
683 res_pool->ref_clocks.xtalin_clock_inKhz =
684 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
685
686 if (res_pool->hubbub) {
687
688 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
689 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
690 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
691
692 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
693 res_pool->ref_clocks.dccg_ref_clock_inKhz,
694 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
695 } else {
696 // Not all ASICs have DCCG sw component
697 res_pool->ref_clocks.dccg_ref_clock_inKhz =
698 res_pool->ref_clocks.xtalin_clock_inKhz;
699 res_pool->ref_clocks.dchub_ref_clock_inKhz =
700 res_pool->ref_clocks.xtalin_clock_inKhz;
701 }
702 } else
703 ASSERT_CRITICAL(false);
704
705 for (i = 0; i < dc->link_count; i++) {
706 /* Power up AND update implementation according to the
707 * required signal (which may be different from the
708 * default signal on connector).
709 */
710 struct dc_link *link = dc->links[i];
711
712 link->link_enc->funcs->hw_init(link->link_enc);
713
714 /* Check for enabled DIG to identify enabled display */
715 if (link->link_enc->funcs->is_dig_enabled &&
716 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
717 link->link_status.link_active = true;
718 if (link->link_enc->funcs->fec_is_active &&
719 link->link_enc->funcs->fec_is_active(link->link_enc))
720 link->fec_state = dc_link_fec_enabled;
721 }
722 }
723
724 /* we want to turn off all dp displays before doing detection */
725 dc->link_srv->blank_all_dp_displays(dc);
726
727 if (hws->funcs.enable_power_gating_plane)
728 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
729
730 /* If taking control over from VBIOS, we may want to optimize our first
731 * mode set, so we need to skip powering down pipes until we know which
732 * pipes we want to use.
733 * Otherwise, if taking control is not possible, we need to power
734 * everything down.
735 */
736 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
737 hws->funcs.init_pipes(dc, dc->current_state);
738 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
739 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
740 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
741 }
742
743 /* In headless boot cases, DIG may be turned
744 * on which causes HW/SW discrepancies.
745 * To avoid this, power down hardware on boot
746 * if DIG is turned on and seamless boot not enabled
747 */
748 if (!dc->config.seamless_boot_edp_requested) {
749 struct dc_link *edp_links[MAX_NUM_EDP];
750 struct dc_link *edp_link = NULL;
751
752 dc_get_edp_links(dc, edp_links, &edp_num);
753 if (edp_num)
754 edp_link = edp_links[0];
755 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
756 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
757 dc->hwss.edp_backlight_control &&
758 hws->funcs.power_down &&
759 dc->hwss.edp_power_control) {
760 dc->hwss.edp_backlight_control(edp_link, false);
761 hws->funcs.power_down(dc);
762 dc->hwss.edp_power_control(edp_link, false);
763 } else {
764 for (i = 0; i < dc->link_count; i++) {
765 struct dc_link *link = dc->links[i];
766
767 if (link->link_enc->funcs->is_dig_enabled &&
768 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
769 hws->funcs.power_down) {
770 hws->funcs.power_down(dc);
771 break;
772 }
773
774 }
775 }
776 }
777
778 for (i = 0; i < res_pool->audio_count; i++) {
779 struct audio *audio = res_pool->audios[i];
780
781 audio->funcs->hw_init(audio);
782 }
783
784 for (i = 0; i < dc->link_count; i++) {
785 struct dc_link *link = dc->links[i];
786
787 if (link->panel_cntl) {
788 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
789 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
790 }
791 }
792
793 for (i = 0; i < dc->res_pool->pipe_count; i++) {
794 if (abms[i] != NULL)
795 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
796 }
797
798 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
799 if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)
800 dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);
801
802 if (!dc->debug.disable_clock_gate) {
803 /* enable all DCN clock gating */
804 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
805 dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
806
807 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
808 }
809
810 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
811 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
812
813 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)
814 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
815
816 //if softmax is enabled then hardmax will be set by a different call
817 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&
818 !dc->clk_mgr->dc_mode_softmax_enabled)
819 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
820
821 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
822 dc->res_pool->hubbub->funcs->force_pstate_change_control(
823 dc->res_pool->hubbub, false, false);
824 if (dc->res_pool->hubbub->funcs->init_crb)
825 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
826
827 // Get DMCUB capabilities
828 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
829 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
830 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
831 }
832
dcn30_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)833 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
834 {
835 if (pipe_ctx == NULL)
836 return;
837
838 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {
839 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
840 pipe_ctx->stream_res.stream_enc,
841 enable);
842
843 /* Wait for two frame to make sure AV mute is sent out */
844 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {
845 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
846 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
847 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
848 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
849 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
850 }
851 }
852 }
853
dcn30_update_info_frame(struct pipe_ctx * pipe_ctx)854 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
855 {
856 bool is_hdmi_tmds;
857 bool is_dp;
858
859 ASSERT(pipe_ctx->stream);
860
861 if (pipe_ctx->stream_res.stream_enc == NULL)
862 return; /* this is not root pipe */
863
864 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
865 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
866
867 if (!is_hdmi_tmds && !is_dp)
868 return;
869
870 if (is_hdmi_tmds)
871 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
872 pipe_ctx->stream_res.stream_enc,
873 &pipe_ctx->stream_res.encoder_info_frame);
874 else {
875 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
876 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
877 pipe_ctx->stream_res.stream_enc,
878 &pipe_ctx->stream_res.encoder_info_frame);
879
880 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
881 pipe_ctx->stream_res.stream_enc,
882 &pipe_ctx->stream_res.encoder_info_frame);
883 }
884 }
885
dcn30_program_dmdata_engine(struct pipe_ctx * pipe_ctx)886 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
887 {
888 struct dc_stream_state *stream = pipe_ctx->stream;
889 struct hubp *hubp = pipe_ctx->plane_res.hubp;
890 bool enable = false;
891 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
892 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
893 ? dmdata_dp
894 : dmdata_hdmi;
895
896 /* if using dynamic meta, don't set up generic infopackets */
897 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
898 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
899 enable = true;
900 }
901
902 if (!hubp)
903 return;
904
905 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
906 return;
907
908 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
909 hubp->inst, mode);
910 }
911
dcn30_apply_idle_power_optimizations(struct dc * dc,bool enable)912 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
913 {
914 union dmub_rb_cmd cmd;
915 uint32_t tmr_delay = 0, tmr_scale = 0;
916 struct dc_cursor_attributes cursor_attr = {0};
917 bool cursor_cache_enable = false;
918 struct dc_stream_state *stream = NULL;
919 struct dc_plane_state *plane = NULL;
920
921 if (!dc->ctx->dmub_srv)
922 return false;
923
924 if (enable) {
925 if (dc->current_state) {
926 int i;
927
928 /* First, check no-memory-requests case */
929 for (i = 0; i < dc->current_state->stream_count; i++) {
930 if (dc->current_state->stream_status[i].plane_count)
931 /* Fail eligibility on a visible stream */
932 break;
933 }
934
935 if (i == dc->current_state->stream_count) {
936 /* Enable no-memory-requests case */
937 memset(&cmd, 0, sizeof(cmd));
938 cmd.mall.header.type = DMUB_CMD__MALL;
939 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
940 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
941
942 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
943
944 return true;
945 }
946
947 stream = dc->current_state->streams[0];
948 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
949
950 if (!stream || !plane)
951 return false;
952
953 if (stream && plane) {
954 cursor_cache_enable = stream->cursor_position.enable &&
955 plane->address.grph.cursor_cache_addr.quad_part;
956 cursor_attr = stream->cursor_attributes;
957 }
958
959 /*
960 * Second, check MALL eligibility
961 *
962 * single display only, single surface only, 8 and 16 bit formats only, no VM,
963 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
964 *
965 * TODO: When we implement multi-display, PSR displays will be allowed if there is
966 * a non-PSR display present, since in that case we can't do D0i3.2
967 */
968 if (dc->current_state->stream_count == 1 &&
969 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
970 dc->current_state->stream_status[0].plane_count == 1 &&
971 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
972 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
973 plane->address.page_table_base.quad_part == 0 &&
974 dc->hwss.does_plane_fit_in_mall &&
975 dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,
976 plane->plane_size.surface_size.height, plane->format,
977 cursor_cache_enable ? &cursor_attr : NULL)) {
978 unsigned int v_total = stream->adjust.v_total_max ?
979 stream->adjust.v_total_max : stream->timing.v_total;
980 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
981 100LL, (v_total * stream->timing.h_total));
982
983 /*
984 * one frame time in microsec:
985 * Delay_Us = 1000000 / refresh
986 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
987 *
988 * one frame time modified by 'additional timer percent' (p):
989 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
990 * = dynamic_delay_us * (1 + p / 100)
991 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
992 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
993 *
994 * formula for timer duration based on parameters, from regspec:
995 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
996 *
997 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
998 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
999 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
1000 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
1001 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
1002 *
1003 * need to round up the result of the division before the subtraction
1004 */
1005 unsigned int denom = refresh_hz * 6528;
1006 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
1007
1008 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
1009 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
1010 denom) - 64LL;
1011
1012 /* In some cases the stutter period is really big (tiny modes) in these
1013 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
1014 *
1015 * We can check if stutter_period is more than 1/10th the frame time to
1016 * consider if we can actually meet the range of hysteresis timer
1017 */
1018 if (stutter_period > 100000/refresh_hz)
1019 return false;
1020
1021 /* scale should be increased until it fits into 6 bits */
1022 while (tmr_delay & ~0x3F) {
1023 tmr_scale++;
1024
1025 if (tmr_scale > 3) {
1026 /* Delay exceeds range of hysteresis timer */
1027 ASSERT(false);
1028 return false;
1029 }
1030
1031 denom *= 2;
1032 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
1033 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
1034 denom) - 64LL;
1035 }
1036
1037 /* Copy HW cursor */
1038 if (cursor_cache_enable) {
1039 memset(&cmd, 0, sizeof(cmd));
1040 cmd.mall.header.type = DMUB_CMD__MALL;
1041 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
1042 cmd.mall.header.payload_bytes =
1043 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1044
1045 switch (cursor_attr.color_format) {
1046 case CURSOR_MODE_MONO:
1047 cmd.mall.cursor_bpp = 2;
1048 break;
1049 case CURSOR_MODE_COLOR_1BIT_AND:
1050 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1051 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1052 cmd.mall.cursor_bpp = 32;
1053 break;
1054
1055 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1056 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1057 cmd.mall.cursor_bpp = 64;
1058 break;
1059 }
1060
1061 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
1062 cmd.mall.cursor_copy_dst.quad_part =
1063 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
1064 cmd.mall.cursor_width = cursor_attr.width;
1065 cmd.mall.cursor_height = cursor_attr.height;
1066 cmd.mall.cursor_pitch = cursor_attr.pitch;
1067
1068 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1069
1070 /* Use copied cursor, and it's okay to not switch back */
1071 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
1072 dc_stream_program_cursor_attributes(stream, &cursor_attr);
1073 }
1074
1075 /* Enable MALL */
1076 memset(&cmd, 0, sizeof(cmd));
1077 cmd.mall.header.type = DMUB_CMD__MALL;
1078 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
1079 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
1080 cmd.mall.tmr_delay = tmr_delay;
1081 cmd.mall.tmr_scale = tmr_scale;
1082 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
1083
1084 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
1085
1086 return true;
1087 }
1088 }
1089
1090 /* No applicable optimizations */
1091 return false;
1092 }
1093
1094 /* Disable MALL */
1095 memset(&cmd, 0, sizeof(cmd));
1096 cmd.mall.header.type = DMUB_CMD__MALL;
1097 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
1098 cmd.mall.header.payload_bytes =
1099 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1100
1101 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1102
1103 return true;
1104 }
1105
dcn30_does_plane_fit_in_mall(struct dc * dc,unsigned int pitch,unsigned int height,enum surface_pixel_format format,struct dc_cursor_attributes * cursor_attr)1106 bool dcn30_does_plane_fit_in_mall(struct dc *dc,
1107 unsigned int pitch,
1108 unsigned int height,
1109 enum surface_pixel_format format,
1110 struct dc_cursor_attributes *cursor_attr)
1111 {
1112 // add meta size?
1113 unsigned int surface_size = pitch * height *
1114 (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
1115 unsigned int mall_size = dc->caps.mall_size_total;
1116 unsigned int cursor_size = 0;
1117
1118 if (dc->debug.mall_size_override)
1119 mall_size = 1024 * 1024 * dc->debug.mall_size_override;
1120
1121 if (cursor_attr) {
1122 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
1123
1124 switch (cursor_attr->color_format) {
1125 case CURSOR_MODE_MONO:
1126 cursor_size /= 2;
1127 break;
1128 case CURSOR_MODE_COLOR_1BIT_AND:
1129 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1130 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1131 cursor_size *= 4;
1132 break;
1133
1134 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1135 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1136 cursor_size *= 8;
1137 break;
1138 }
1139 }
1140
1141 return (surface_size + cursor_size) < mall_size;
1142 }
1143
dcn30_hardware_release(struct dc * dc)1144 void dcn30_hardware_release(struct dc *dc)
1145 {
1146 bool subvp_in_use = false;
1147 uint32_t i;
1148
1149 dc_dmub_srv_p_state_delegate(dc, false, NULL);
1150 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
1151
1152 /* SubVP treated the same way as FPO. If driver disable and
1153 * we are using a SubVP config, disable and force on DCN side
1154 * to prevent P-State hang on driver enable.
1155 */
1156 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1157 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1158
1159 if (!pipe->stream)
1160 continue;
1161
1162 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {
1163 subvp_in_use = true;
1164 break;
1165 }
1166 }
1167 /* If pstate unsupported, or still supported
1168 * by firmware, force it supported by dcn
1169 */
1170 if (dc->current_state)
1171 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
1172 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
1173 dc->res_pool->hubbub->funcs->force_pstate_change_control)
1174 dc->res_pool->hubbub->funcs->force_pstate_change_control(
1175 dc->res_pool->hubbub, true, true);
1176 }
1177
dcn30_set_disp_pattern_generator(const struct dc * dc,struct pipe_ctx * pipe_ctx,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,const struct tg_color * solid_color,int width,int height,int offset)1178 void dcn30_set_disp_pattern_generator(const struct dc *dc,
1179 struct pipe_ctx *pipe_ctx,
1180 enum controller_dp_test_pattern test_pattern,
1181 enum controller_dp_color_space color_space,
1182 enum dc_color_depth color_depth,
1183 const struct tg_color *solid_color,
1184 int width, int height, int offset)
1185 {
1186 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
1187 color_space, color_depth, solid_color, width, height, offset);
1188 }
1189
dcn30_prepare_bandwidth(struct dc * dc,struct dc_state * context)1190 void dcn30_prepare_bandwidth(struct dc *dc,
1191 struct dc_state *context)
1192 {
1193 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1194 dc->optimized_required = true;
1195 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1196 }
1197
1198 if (dc->clk_mgr->dc_mode_softmax_enabled)
1199 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1200 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1201 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1202
1203 dcn20_prepare_bandwidth(dc, context);
1204
1205 if (!dc->clk_mgr->clks.fw_based_mclk_switching)
1206 dc_dmub_srv_p_state_delegate(dc, false, context);
1207 }
1208
dcn30_wait_for_all_pending_updates(const struct pipe_ctx * pipe_ctx)1209 void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)
1210 {
1211 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1212 bool pending_updates = false;
1213 unsigned int i;
1214
1215 if (tg && tg->funcs->is_tg_enabled(tg)) {
1216 // Poll for 100ms maximum
1217 for (i = 0; i < 100000; i++) {
1218 pending_updates = false;
1219 if (tg->funcs->get_optc_double_buffer_pending)
1220 pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg);
1221
1222 if (tg->funcs->get_otg_double_buffer_pending)
1223 pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg);
1224
1225 if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)
1226 pending_updates |= tg->funcs->get_pipe_update_pending(tg);
1227
1228 if (!pending_updates)
1229 break;
1230
1231 udelay(1);
1232 }
1233 }
1234 }
1235
dcn30_get_underflow_debug_data(const struct dc * dc,struct timing_generator * tg,struct dc_underflow_debug_data * out_data)1236 void dcn30_get_underflow_debug_data(const struct dc *dc,
1237 struct timing_generator *tg,
1238 struct dc_underflow_debug_data *out_data)
1239 {
1240 struct hubbub *hubbub = dc->res_pool->hubbub;
1241
1242 if (hubbub) {
1243 if (hubbub->funcs->hubbub_read_reg_state) {
1244 hubbub->funcs->hubbub_read_reg_state(hubbub, out_data->hubbub_reg_state);
1245 }
1246 }
1247
1248 for (int i = 0; i < MAX_PIPES; i++) {
1249 struct hubp *hubp = dc->res_pool->hubps[i];
1250 struct dpp *dpp = dc->res_pool->dpps[i];
1251 struct output_pixel_processor *opp = dc->res_pool->opps[i];
1252 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1253 struct mpc *mpc = dc->res_pool->mpc;
1254 struct timing_generator *optc = dc->res_pool->timing_generators[i];
1255 struct dccg *dccg = dc->res_pool->dccg;
1256
1257 if (hubp)
1258 if (hubp->funcs->hubp_read_reg_state)
1259 hubp->funcs->hubp_read_reg_state(hubp, out_data->hubp_reg_state[i]);
1260
1261 if (dpp)
1262 if (dpp->funcs->dpp_read_reg_state)
1263 dpp->funcs->dpp_read_reg_state(dpp, out_data->dpp_reg_state[i]);
1264
1265 if (opp)
1266 if (opp->funcs->opp_read_reg_state)
1267 opp->funcs->opp_read_reg_state(opp, out_data->opp_reg_state[i]);
1268
1269 if (dsc)
1270 if (dsc->funcs->dsc_read_reg_state)
1271 dsc->funcs->dsc_read_reg_state(dsc, out_data->dsc_reg_state[i]);
1272
1273 if (mpc)
1274 if (mpc->funcs->mpc_read_reg_state)
1275 mpc->funcs->mpc_read_reg_state(mpc, i, out_data->mpc_reg_state[i]);
1276
1277 if (optc)
1278 if (optc->funcs->optc_read_reg_state)
1279 optc->funcs->optc_read_reg_state(optc, out_data->optc_reg_state[i]);
1280
1281 if (dccg)
1282 if (dccg->funcs->dccg_read_reg_state)
1283 dccg->funcs->dccg_read_reg_state(dccg, out_data->dccg_reg_state[i]);
1284 }
1285 }
1286