1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn302/dcn302_init.h"
27 #include "dcn302_resource.h"
28 #include "dcn302/dcn302_dccg.h"
29 #include "irq/dcn302/irq_service_dcn302.h"
30 #include "basics/conversion.h"
31
32 #include "dcn30/dcn30_dio_link_encoder.h"
33 #include "dcn30/dcn30_dio_stream_encoder.h"
34 #include "dcn30/dcn30_dwb.h"
35 #include "dcn30/dcn30_dpp.h"
36 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
37 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
38 #include "dcn30/dcn30_hubbub.h"
39 #include "dcn30/dcn30_hubp.h"
40 #include "dcn30/dcn30_mmhubbub.h"
41 #include "dcn30/dcn30_mpc.h"
42 #include "dcn30/dcn30_opp.h"
43 #include "dcn30/dcn30_optc.h"
44 #include "dcn30/dcn30_resource.h"
45
46 #include "dcn20/dcn20_dsc.h"
47 #include "dcn20/dcn20_resource.h"
48
49 #include "dml/dcn30/dcn30_fpu.h"
50
51 #include "dcn10/dcn10_resource.h"
52 #include "dio/dcn10/dcn10_dio.h"
53
54 #include "link_service.h"
55
56 #include "dce/dce_abm.h"
57 #include "dce/dce_audio.h"
58 #include "dce/dce_aux.h"
59 #include "dce/dce_clock_source.h"
60 #include "dce/dce_hwseq.h"
61 #include "dce/dce_i2c_hw.h"
62 #include "dce/dce_panel_cntl.h"
63 #include "dce/dmub_abm.h"
64 #include "dce/dmub_psr.h"
65 #include "clk_mgr.h"
66
67 #include "hw_sequencer_private.h"
68 #include "reg_helper.h"
69 #include "resource.h"
70 #include "vm_helper.h"
71
72 #include "dml/dcn302/dcn302_fpu.h"
73
74 #include "dimgrey_cavefish_ip_offset.h"
75 #include "dcn/dcn_3_0_2_offset.h"
76 #include "dcn/dcn_3_0_2_sh_mask.h"
77 #include "dpcs/dpcs_3_0_0_offset.h"
78 #include "dpcs/dpcs_3_0_0_sh_mask.h"
79 #include "nbio/nbio_7_4_offset.h"
80 #include "amdgpu_socbb.h"
81
82 #define DC_LOGGER \
83 dc->ctx->logger
84 #define DC_LOGGER_INIT(logger)
85
86 static const struct dc_debug_options debug_defaults_drv = {
87 .limit_ffe = 3,
88 .disable_dmcu = true,
89 .force_abm_enable = false,
90 .clock_trace = true,
91 .disable_pplib_clock_request = true,
92 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
93 .force_single_disp_pipe_split = false,
94 .disable_dcc = DCC_ENABLE,
95 .vsr_support = true,
96 .performance_trace = false,
97 .max_downscale_src_width = 7680,/*upto 8K*/
98 .disable_pplib_wm_range = false,
99 .scl_reset_length10 = true,
100 .sanity_checks = false,
101 .underflow_assert_delay_us = 0xFFFFFFFF,
102 .dwb_fi_phase = -1, // -1 = disable,
103 .dmub_command_table = true,
104 .use_max_lb = true,
105 .exit_idle_opt_for_cursor_updates = true,
106 .using_dml2 = false,
107 };
108
109 static const struct dc_check_config config_defaults = {
110 .enable_legacy_fast_update = false,
111 };
112
113 static const struct dc_panel_config panel_config_defaults = {
114 .psr = {
115 .disable_psr = false,
116 .disallow_psrsu = false,
117 .disallow_replay = false,
118 },
119 };
120
121 enum dcn302_clk_src_array_id {
122 DCN302_CLK_SRC_PLL0,
123 DCN302_CLK_SRC_PLL1,
124 DCN302_CLK_SRC_PLL2,
125 DCN302_CLK_SRC_PLL3,
126 DCN302_CLK_SRC_PLL4,
127 DCN302_CLK_SRC_TOTAL
128 };
129
130 static const struct resource_caps res_cap_dcn302 = {
131 .num_timing_generator = 5,
132 .num_opp = 5,
133 .num_video_plane = 5,
134 .num_audio = 5,
135 .num_stream_encoder = 5,
136 .num_hpo_frl = 1,
137 .num_dwb = 1,
138 .num_ddc = 5,
139 .num_vmid = 16,
140 .num_mpc_3dlut = 2,
141 .num_dsc = 5,
142 };
143
144 static const struct dc_plane_cap plane_cap = {
145 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
146 .per_pixel_alpha = true,
147 .pixel_format_support = {
148 .argb8888 = true,
149 .nv12 = true,
150 .fp16 = true,
151 .p010 = true,
152 .ayuv = false,
153 },
154 .max_upscale_factor = {
155 .argb8888 = 16000,
156 .nv12 = 16000,
157 .fp16 = 16000
158 },
159 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
160 .max_downscale_factor = {
161 .argb8888 = 167,
162 .nv12 = 167,
163 .fp16 = 167
164 },
165 16,
166 16
167 };
168
169 /* NBIO */
170 #define NBIO_BASE_INNER(seg) \
171 NBIO_BASE__INST0_SEG ## seg
172
173 #define NBIO_BASE(seg) \
174 NBIO_BASE_INNER(seg)
175
176 #define NBIO_SR(reg_name)\
177 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
178 mm ## reg_name
179
180 /* DCN */
181 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
182
183 #define BASE(seg) BASE_INNER(seg)
184
185 #define SR(reg_name)\
186 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
187
188 #define SF(reg_name, field_name, post_fix)\
189 .field_name = reg_name ## __ ## field_name ## post_fix
190
191 #define SRI(reg_name, block, id)\
192 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
193
194 #define SRI2(reg_name, block, id)\
195 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
196
197 #define SRII(reg_name, block, id)\
198 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
199 mm ## block ## id ## _ ## reg_name
200
201 #define DCCG_SRII(reg_name, block, id)\
202 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
203 mm ## block ## id ## _ ## reg_name
204
205 #define VUPDATE_SRII(reg_name, block, id)\
206 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
207 mm ## reg_name ## _ ## block ## id
208
209 #define SRII_DWB(reg_name, temp_name, block, id)\
210 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
211 mm ## block ## id ## _ ## temp_name
212
213 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
214 .field_name = reg_name ## __ ## field_name ## post_fix
215
216 #define SRII_MPC_RMU(reg_name, block, id)\
217 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
218 mm ## block ## id ## _ ## reg_name
219
220 static const struct dcn_hubbub_registers hubbub_reg = {
221 HUBBUB_REG_LIST_DCN30(0)
222 };
223
224 static const struct dcn_hubbub_shift hubbub_shift = {
225 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
226 };
227
228 static const struct dcn_hubbub_mask hubbub_mask = {
229 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
230 };
231
232 #define vmid_regs(id)\
233 [id] = { DCN20_VMID_REG_LIST(id) }
234
235 static const struct dcn_vmid_registers vmid_regs[] = {
236 vmid_regs(0),
237 vmid_regs(1),
238 vmid_regs(2),
239 vmid_regs(3),
240 vmid_regs(4),
241 vmid_regs(5),
242 vmid_regs(6),
243 vmid_regs(7),
244 vmid_regs(8),
245 vmid_regs(9),
246 vmid_regs(10),
247 vmid_regs(11),
248 vmid_regs(12),
249 vmid_regs(13),
250 vmid_regs(14),
251 vmid_regs(15)
252 };
253
254 static const struct dcn20_vmid_shift vmid_shifts = {
255 DCN20_VMID_MASK_SH_LIST(__SHIFT)
256 };
257
258 static const struct dcn20_vmid_mask vmid_masks = {
259 DCN20_VMID_MASK_SH_LIST(_MASK)
260 };
261
262 static const struct dcn_dio_registers dio_regs = {
263 DIO_REG_LIST_DCN10()
264 };
265
266 #define DIO_MASK_SH_LIST(mask_sh)\
267 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
268
269 static const struct dcn_dio_shift dio_shift = {
270 DIO_MASK_SH_LIST(__SHIFT)
271 };
272
273 static const struct dcn_dio_mask dio_mask = {
274 DIO_MASK_SH_LIST(_MASK)
275 };
276
dcn302_dio_create(struct dc_context * ctx)277 static struct dio *dcn302_dio_create(struct dc_context *ctx)
278 {
279 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
280
281 if (!dio10)
282 return NULL;
283
284 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
285
286 return &dio10->base;
287 }
288
dcn302_hubbub_create(struct dc_context * ctx)289 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
290 {
291 int i;
292
293 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
294
295 if (!hubbub3)
296 return NULL;
297
298 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
299
300 for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
301 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
302
303 vmid->ctx = ctx;
304
305 vmid->regs = &vmid_regs[i];
306 vmid->shifts = &vmid_shifts;
307 vmid->masks = &vmid_masks;
308 }
309
310 return &hubbub3->base;
311 }
312
313 #define vpg_regs(id)\
314 [id] = { VPG_DCN3_REG_LIST(id) }
315
316 static const struct dcn30_vpg_registers vpg_regs[] = {
317 vpg_regs(0),
318 vpg_regs(1),
319 vpg_regs(2),
320 vpg_regs(3),
321 vpg_regs(4),
322 vpg_regs(5)
323 };
324
325 static const struct dcn30_vpg_shift vpg_shift = {
326 DCN3_VPG_MASK_SH_LIST(__SHIFT)
327 };
328
329 static const struct dcn30_vpg_mask vpg_mask = {
330 DCN3_VPG_MASK_SH_LIST(_MASK)
331 };
332
dcn302_vpg_create(struct dc_context * ctx,uint32_t inst)333 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
334 {
335 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
336
337 if (!vpg3)
338 return NULL;
339
340 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
341
342 return &vpg3->base;
343 }
344
345 #define afmt_regs(id)\
346 [id] = { AFMT_DCN3_REG_LIST(id) }
347
348 static const struct dcn30_afmt_registers afmt_regs[] = {
349 afmt_regs(0),
350 afmt_regs(1),
351 afmt_regs(2),
352 afmt_regs(3),
353 afmt_regs(4),
354 afmt_regs(5)
355 };
356
357 static const struct dcn30_afmt_shift afmt_shift = {
358 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn30_afmt_mask afmt_mask = {
362 DCN3_AFMT_MASK_SH_LIST(_MASK)
363 };
364
dcn302_afmt_create(struct dc_context * ctx,uint32_t inst)365 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
366 {
367 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
368
369 if (!afmt3)
370 return NULL;
371
372 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
373
374 return &afmt3->base;
375 }
376
377 #define audio_regs(id)\
378 [id] = { AUD_COMMON_REG_LIST(id) }
379
380 static const struct dce_audio_registers audio_regs[] = {
381 audio_regs(0),
382 audio_regs(1),
383 audio_regs(2),
384 audio_regs(3),
385 audio_regs(4),
386 audio_regs(5),
387 audio_regs(6)
388 };
389
390 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
391 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
392 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
393 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
394
395 static const struct dce_audio_shift audio_shift = {
396 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
397 };
398
399 static const struct dce_audio_mask audio_mask = {
400 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
401 };
402
dcn302_create_audio(struct dc_context * ctx,unsigned int inst)403 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
404 {
405 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
406 }
407
408 #define stream_enc_regs(id)\
409 [id] = { SE_DCN3_REG_LIST(id) }
410
411 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
412 stream_enc_regs(0),
413 stream_enc_regs(1),
414 stream_enc_regs(2),
415 stream_enc_regs(3),
416 stream_enc_regs(4)
417 };
418
419 static const struct dcn10_stream_encoder_shift se_shift = {
420 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
421 };
422
423 static const struct dcn10_stream_encoder_mask se_mask = {
424 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
425 };
426
dcn302_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)427 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
428 {
429 struct dcn10_stream_encoder *enc1;
430 struct vpg *vpg;
431 struct afmt *afmt;
432 int vpg_inst;
433 int afmt_inst;
434
435 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
436 if (eng_id <= ENGINE_ID_DIGE) {
437 vpg_inst = eng_id;
438 afmt_inst = eng_id;
439 } else
440 return NULL;
441
442 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
443 vpg = dcn302_vpg_create(ctx, vpg_inst);
444 afmt = dcn302_afmt_create(ctx, afmt_inst);
445
446 if (!enc1 || !vpg || !afmt) {
447 kfree(enc1);
448 kfree(vpg);
449 kfree(afmt);
450 return NULL;
451 }
452
453 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
454 &se_shift, &se_mask);
455
456 return &enc1->base;
457 }
458
459 #define hpo_frl_stream_encoder_reg_list(id)\
460 [id] = { DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id) }
461
462 #define hpo_frl_stream_encoder_dme_reg_list(id)\
463 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 5)
464
465 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
466 hpo_frl_stream_encoder_reg_list(0),
467 hpo_frl_stream_encoder_dme_reg_list(5),
468 };
469
470 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
471 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
472 };
473
474 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
475 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
476 };
477
dcn302_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)478 static struct hpo_frl_stream_encoder *dcn302_hpo_frl_stream_encoder_create(enum engine_id eng_id,
479 struct dc_context *ctx)
480 {
481 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
482 struct vpg *vpg;
483 struct afmt *afmt;
484 int vpg_inst;
485 int afmt_inst;
486
487 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
488 if (eng_id == ENGINE_ID_HPO_0) {
489 vpg_inst = 5;
490 afmt_inst = 5;
491 } else
492 return NULL;
493
494 /* allocate HPO stream encoder and create VPG sub-block */
495 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
496 vpg = dcn302_vpg_create(ctx, vpg_inst);
497 afmt = dcn302_afmt_create(ctx, afmt_inst);
498
499 if (!hpo_enc3 || !vpg || !afmt) {
500 kfree(hpo_enc3);
501 kfree(vpg);
502 kfree(afmt);
503 return NULL;
504 }
505
506 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios, eng_id, vpg, afmt,
507 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0], &hpo_se_shift, &hpo_se_mask);
508
509 return &hpo_enc3->base;
510 }
511
512 #define hpo_frl_link_encoder_reg_list(id)\
513 [id] = { DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id) }
514
515 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
516 hpo_frl_link_encoder_reg_list(0),
517 };
518
519 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
520 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
521 };
522
523 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
524 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
525 };
526
dcn302_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)527 static struct hpo_frl_link_encoder *dcn302_hpo_frl_link_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
528 {
529 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
530
531 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
532
533 /* allocate HPO link encoder */
534 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
535 if (!hpo_enc3)
536 return NULL; /* out of memory */
537
538 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0,
539 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0], &hpo_le_shift, &hpo_le_mask);
540
541 return &hpo_enc3->base;
542 }
543
544 #define clk_src_regs(index, pllid)\
545 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
546
547 static const struct dce110_clk_src_regs clk_src_regs[] = {
548 clk_src_regs(0, A),
549 clk_src_regs(1, B),
550 clk_src_regs(2, C),
551 clk_src_regs(3, D),
552 clk_src_regs(4, E)
553 };
554
555 static const struct dce110_clk_src_shift cs_shift = {
556 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
557 };
558
559 static const struct dce110_clk_src_mask cs_mask = {
560 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
561 };
562
dcn302_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)563 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
564 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
565 {
566 struct dce110_clk_src *clk_src = kzalloc_obj(struct dce110_clk_src);
567
568 if (!clk_src)
569 return NULL;
570
571 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
572 clk_src->base.dp_clk_src = dp_clk_src;
573 return &clk_src->base;
574 }
575
576 kfree(clk_src);
577 BREAK_TO_DEBUGGER();
578 return NULL;
579 }
580
581 static const struct dce_hwseq_registers hwseq_reg = {
582 HWSEQ_DCN302_REG_LIST()
583 };
584
585 static const struct dce_hwseq_shift hwseq_shift = {
586 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
587 };
588
589 static const struct dce_hwseq_mask hwseq_mask = {
590 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
591 };
592
dcn302_hwseq_create(struct dc_context * ctx)593 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
594 {
595 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
596
597 if (hws) {
598 hws->ctx = ctx;
599 hws->regs = &hwseq_reg;
600 hws->shifts = &hwseq_shift;
601 hws->masks = &hwseq_mask;
602 }
603 return hws;
604 }
605
606 #define hubp_regs(id)\
607 [id] = { HUBP_REG_LIST_DCN30(id) }
608
609 static const struct dcn_hubp2_registers hubp_regs[] = {
610 hubp_regs(0),
611 hubp_regs(1),
612 hubp_regs(2),
613 hubp_regs(3),
614 hubp_regs(4)
615 };
616
617 static const struct dcn_hubp2_shift hubp_shift = {
618 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
619 };
620
621 static const struct dcn_hubp2_mask hubp_mask = {
622 HUBP_MASK_SH_LIST_DCN30(_MASK)
623 };
624
dcn302_hubp_create(struct dc_context * ctx,uint32_t inst)625 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
626 {
627 struct dcn20_hubp *hubp2 = kzalloc_obj(struct dcn20_hubp);
628
629 if (!hubp2)
630 return NULL;
631
632 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
633 return &hubp2->base;
634
635 BREAK_TO_DEBUGGER();
636 kfree(hubp2);
637 return NULL;
638 }
639
640 #define dpp_regs(id)\
641 [id] = { DPP_REG_LIST_DCN30(id) }
642
643 static const struct dcn3_dpp_registers dpp_regs[] = {
644 dpp_regs(0),
645 dpp_regs(1),
646 dpp_regs(2),
647 dpp_regs(3),
648 dpp_regs(4)
649 };
650
651 static const struct dcn3_dpp_shift tf_shift = {
652 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
653 };
654
655 static const struct dcn3_dpp_mask tf_mask = {
656 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
657 };
658
dcn302_dpp_create(struct dc_context * ctx,uint32_t inst)659 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
660 {
661 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
662
663 if (!dpp)
664 return NULL;
665
666 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
667 return &dpp->base;
668
669 BREAK_TO_DEBUGGER();
670 kfree(dpp);
671 return NULL;
672 }
673
674 #define opp_regs(id)\
675 [id] = { OPP_REG_LIST_DCN30(id) }
676
677 static const struct dcn20_opp_registers opp_regs[] = {
678 opp_regs(0),
679 opp_regs(1),
680 opp_regs(2),
681 opp_regs(3),
682 opp_regs(4)
683 };
684
685 static const struct dcn20_opp_shift opp_shift = {
686 OPP_MASK_SH_LIST_DCN20(__SHIFT)
687 };
688
689 static const struct dcn20_opp_mask opp_mask = {
690 OPP_MASK_SH_LIST_DCN20(_MASK)
691 };
692
dcn302_opp_create(struct dc_context * ctx,uint32_t inst)693 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
694 {
695 struct dcn20_opp *opp = kzalloc_obj(struct dcn20_opp);
696
697 if (!opp) {
698 BREAK_TO_DEBUGGER();
699 return NULL;
700 }
701
702 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
703 return &opp->base;
704 }
705
706 #define optc_regs(id)\
707 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
708
709 static const struct dcn_optc_registers optc_regs[] = {
710 optc_regs(0),
711 optc_regs(1),
712 optc_regs(2),
713 optc_regs(3),
714 optc_regs(4)
715 };
716
717 static const struct dcn_optc_shift optc_shift = {
718 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
719 };
720
721 static const struct dcn_optc_mask optc_mask = {
722 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
723 };
724
dcn302_timing_generator_create(struct dc_context * ctx,uint32_t instance)725 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
726 {
727 struct optc *tgn10 = kzalloc_obj(struct optc);
728
729 if (!tgn10)
730 return NULL;
731
732 tgn10->base.inst = instance;
733 tgn10->base.ctx = ctx;
734
735 tgn10->tg_regs = &optc_regs[instance];
736 tgn10->tg_shift = &optc_shift;
737 tgn10->tg_mask = &optc_mask;
738
739 dcn30_timing_generator_init(tgn10);
740
741 return &tgn10->base;
742 }
743
744 static const struct dcn30_mpc_registers mpc_regs = {
745 MPC_REG_LIST_DCN3_0(0),
746 MPC_REG_LIST_DCN3_0(1),
747 MPC_REG_LIST_DCN3_0(2),
748 MPC_REG_LIST_DCN3_0(3),
749 MPC_REG_LIST_DCN3_0(4),
750 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
751 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
752 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
753 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
754 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
755 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
756 MPC_RMU_REG_LIST_DCN3AG(0),
757 MPC_RMU_REG_LIST_DCN3AG(1),
758 MPC_RMU_REG_LIST_DCN3AG(2),
759 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
760 };
761
762 static const struct dcn30_mpc_shift mpc_shift = {
763 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
764 };
765
766 static const struct dcn30_mpc_mask mpc_mask = {
767 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
768 };
769
dcn302_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)770 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
771 {
772 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
773
774 if (!mpc30)
775 return NULL;
776
777 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
778
779 return &mpc30->base;
780 }
781
782 #define dsc_regsDCN20(id)\
783 [id] = { DSC_REG_LIST_DCN20(id) }
784
785 static const struct dcn20_dsc_registers dsc_regs[] = {
786 dsc_regsDCN20(0),
787 dsc_regsDCN20(1),
788 dsc_regsDCN20(2),
789 dsc_regsDCN20(3),
790 dsc_regsDCN20(4)
791 };
792
793 static const struct dcn20_dsc_shift dsc_shift = {
794 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
795 };
796
797 static const struct dcn20_dsc_mask dsc_mask = {
798 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
799 };
800
dcn302_dsc_create(struct dc_context * ctx,uint32_t inst)801 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
802 {
803 struct dcn20_dsc *dsc = kzalloc_obj(struct dcn20_dsc);
804
805 if (!dsc) {
806 BREAK_TO_DEBUGGER();
807 return NULL;
808 }
809
810 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
811 return &dsc->base;
812 }
813
814 #define dwbc_regs_dcn3(id)\
815 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
816
817 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
818 dwbc_regs_dcn3(0)
819 };
820
821 static const struct dcn30_dwbc_shift dwbc30_shift = {
822 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
823 };
824
825 static const struct dcn30_dwbc_mask dwbc30_mask = {
826 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
827 };
828
dcn302_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)829 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
830 {
831 unsigned int i;
832 uint32_t pipe_count = pool->res_cap->num_dwb;
833
834 for (i = 0; i < pipe_count; i++) {
835 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
836
837 if (!dwbc30) {
838 dm_error("DC: failed to create dwbc30!\n");
839 return false;
840 }
841
842 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
843
844 pool->dwbc[i] = &dwbc30->base;
845 }
846 return true;
847 }
848
849 #define mcif_wb_regs_dcn3(id)\
850 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
851
852 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
853 mcif_wb_regs_dcn3(0)
854 };
855
856 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
857 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
858 };
859
860 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
861 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
862 };
863
dcn302_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)864 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
865 {
866 unsigned int i;
867 uint32_t pipe_count = pool->res_cap->num_dwb;
868
869 for (i = 0; i < pipe_count; i++) {
870 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
871
872 if (!mcif_wb30) {
873 dm_error("DC: failed to create mcif_wb30!\n");
874 return false;
875 }
876
877 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
878
879 pool->mcif_wb[i] = &mcif_wb30->base;
880 }
881 return true;
882 }
883
884 #define aux_engine_regs(id)\
885 [id] = {\
886 AUX_COMMON_REG_LIST0(id), \
887 .AUXN_IMPCAL = 0, \
888 .AUXP_IMPCAL = 0, \
889 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
890 }
891
892 static const struct dce110_aux_registers aux_engine_regs[] = {
893 aux_engine_regs(0),
894 aux_engine_regs(1),
895 aux_engine_regs(2),
896 aux_engine_regs(3),
897 aux_engine_regs(4)
898 };
899
900 static const struct dce110_aux_registers_shift aux_shift = {
901 DCN_AUX_MASK_SH_LIST(__SHIFT)
902 };
903
904 static const struct dce110_aux_registers_mask aux_mask = {
905 DCN_AUX_MASK_SH_LIST(_MASK)
906 };
907
dcn302_aux_engine_create(struct dc_context * ctx,uint32_t inst)908 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
909 {
910 struct aux_engine_dce110 *aux_engine = kzalloc_obj(struct aux_engine_dce110);
911
912 if (!aux_engine)
913 return NULL;
914
915 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
916 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
917
918 return &aux_engine->base;
919 }
920
921 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
922
923 static const struct dce_i2c_registers i2c_hw_regs[] = {
924 i2c_inst_regs(1),
925 i2c_inst_regs(2),
926 i2c_inst_regs(3),
927 i2c_inst_regs(4),
928 i2c_inst_regs(5)
929 };
930
931 static const struct dce_i2c_shift i2c_shifts = {
932 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
933 };
934
935 static const struct dce_i2c_mask i2c_masks = {
936 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
937 };
938
dcn302_i2c_hw_create(struct dc_context * ctx,uint32_t inst)939 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
940 {
941 struct dce_i2c_hw *dce_i2c_hw = kzalloc_obj(struct dce_i2c_hw);
942
943 if (!dce_i2c_hw)
944 return NULL;
945
946 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
947
948 return dce_i2c_hw;
949 }
950
951 static const struct encoder_feature_support link_enc_feature = {
952 .max_hdmi_deep_color = COLOR_DEPTH_121212,
953 .max_hdmi_pixel_clock = 600000,
954 .hdmi_ycbcr420_supported = true,
955 .dp_ycbcr420_supported = true,
956 .fec_supported = true,
957 .flags.bits.IS_HBR2_CAPABLE = true,
958 .flags.bits.IS_HBR3_CAPABLE = true,
959 .flags.bits.IS_TPS3_CAPABLE = true,
960 .flags.bits.IS_TPS4_CAPABLE = true
961 };
962
963 #define link_regs(id, phyid)\
964 [id] = {\
965 LE_DCN3_REG_LIST(id), \
966 UNIPHY_DCN2_REG_LIST(phyid), \
967 DPCS_DCN2_REG_LIST(id), \
968 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
969 }
970
971 static const struct dcn10_link_enc_registers link_enc_regs[] = {
972 link_regs(0, A),
973 link_regs(1, B),
974 link_regs(2, C),
975 link_regs(3, D),
976 link_regs(4, E)
977 };
978
979 static const struct dcn10_link_enc_shift le_shift = {
980 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
981 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
982 };
983
984 static const struct dcn10_link_enc_mask le_mask = {
985 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
986 DPCS_DCN2_MASK_SH_LIST(_MASK)
987 };
988
989 #define aux_regs(id)\
990 [id] = { DCN2_AUX_REG_LIST(id) }
991
992 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
993 aux_regs(0),
994 aux_regs(1),
995 aux_regs(2),
996 aux_regs(3),
997 aux_regs(4)
998 };
999
1000 #define hpd_regs(id)\
1001 [id] = { HPD_REG_LIST(id) }
1002
1003 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1004 hpd_regs(0),
1005 hpd_regs(1),
1006 hpd_regs(2),
1007 hpd_regs(3),
1008 hpd_regs(4)
1009 };
1010
dcn302_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1011 static struct link_encoder *dcn302_link_encoder_create(
1012 struct dc_context *ctx,
1013 const struct encoder_init_data *enc_init_data)
1014 {
1015 (void)ctx;
1016 struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder);
1017
1018 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1019 return NULL;
1020
1021 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
1022 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
1023 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
1024
1025 return &enc20->enc10.base;
1026 }
1027
1028 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1029 { DCN_PANEL_CNTL_REG_LIST() }
1030 };
1031
1032 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1033 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1034 };
1035
1036 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1037 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1038 };
1039
dcn302_panel_cntl_create(const struct panel_cntl_init_data * init_data)1040 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1041 {
1042 struct dce_panel_cntl *panel_cntl = kzalloc_obj(struct dce_panel_cntl);
1043
1044 if (!panel_cntl)
1045 return NULL;
1046
1047 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
1048 &panel_cntl_shift, &panel_cntl_mask);
1049
1050 return &panel_cntl->base;
1051 }
1052
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1053 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
1054 {
1055 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1056 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1057 }
1058
1059 static const struct resource_create_funcs res_create_funcs = {
1060 .read_dce_straps = read_dce_straps,
1061 .create_audio = dcn302_create_audio,
1062 .create_stream_encoder = dcn302_stream_encoder_create,
1063 .create_hpo_frl_stream_encoder = dcn302_hpo_frl_stream_encoder_create,
1064 .create_hwseq = dcn302_hwseq_create,
1065 };
1066
is_soc_bounding_box_valid(struct dc * dc)1067 static bool is_soc_bounding_box_valid(struct dc *dc)
1068 {
1069 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1070
1071 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
1072 return true;
1073
1074 return false;
1075 }
1076
init_soc_bounding_box(struct dc * dc,struct resource_pool * pool)1077 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
1078 {
1079 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
1080 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
1081
1082 DC_LOGGER_INIT(dc->ctx->logger);
1083
1084 if (!is_soc_bounding_box_valid(dc)) {
1085 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1086 return false;
1087 }
1088
1089 loaded_ip->max_num_otg = pool->pipe_count;
1090 loaded_ip->max_num_dpp = pool->pipe_count;
1091 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1092 DC_FP_START();
1093 dcn20_patch_bounding_box(dc, loaded_bb);
1094 DC_FP_END();
1095
1096 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1097 struct bp_soc_bb_info bb_info = { 0 };
1098
1099 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
1100 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1101
1102 DC_FP_START();
1103 dcn302_fpu_init_soc_bounding_box(bb_info);
1104 DC_FP_END();
1105 }
1106 }
1107
1108 return true;
1109 }
1110
dcn302_resource_destruct(struct resource_pool * pool)1111 static void dcn302_resource_destruct(struct resource_pool *pool)
1112 {
1113 unsigned int i;
1114
1115 for (i = 0; i < pool->stream_enc_count; i++) {
1116 if (pool->stream_enc[i] != NULL) {
1117 if (pool->stream_enc[i]->vpg != NULL) {
1118 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1119 pool->stream_enc[i]->vpg = NULL;
1120 }
1121 if (pool->stream_enc[i]->afmt != NULL) {
1122 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1123 pool->stream_enc[i]->afmt = NULL;
1124 }
1125 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1126 pool->stream_enc[i] = NULL;
1127 }
1128 }
1129
1130 for (i = 0; i < pool->hpo_frl_stream_enc_count; i++) {
1131 if (pool->hpo_frl_stream_enc[i] != NULL) {
1132 if (pool->hpo_frl_stream_enc[i]->vpg != NULL) {
1133 kfree(DCN30_VPG_FROM_VPG(pool->hpo_frl_stream_enc[i]->vpg));
1134 pool->hpo_frl_stream_enc[i]->vpg = NULL;
1135 }
1136
1137 if (pool->hpo_frl_stream_enc[i]->afmt != NULL) {
1138 kfree(DCN30_AFMT_FROM_AFMT(pool->hpo_frl_stream_enc[i]->afmt));
1139 pool->hpo_frl_stream_enc[i]->afmt = NULL;
1140 }
1141
1142 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->hpo_frl_stream_enc[i]));
1143 pool->hpo_frl_stream_enc[i] = NULL;
1144 }
1145 }
1146
1147 for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) {
1148 if (pool->dscs[i] != NULL)
1149 dcn20_dsc_destroy(&pool->dscs[i]);
1150 }
1151
1152 if (pool->mpc != NULL) {
1153 kfree(TO_DCN20_MPC(pool->mpc));
1154 pool->mpc = NULL;
1155 }
1156
1157 if (pool->hubbub != NULL) {
1158 kfree(pool->hubbub);
1159 pool->hubbub = NULL;
1160 }
1161
1162 if (pool->dio != NULL) {
1163 kfree(TO_DCN10_DIO(pool->dio));
1164 pool->dio = NULL;
1165 }
1166
1167 for (i = 0; i < pool->pipe_count; i++) {
1168 if (pool->dpps[i] != NULL) {
1169 kfree(TO_DCN20_DPP(pool->dpps[i]));
1170 pool->dpps[i] = NULL;
1171 }
1172
1173 if (pool->hubps[i] != NULL) {
1174 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1175 pool->hubps[i] = NULL;
1176 }
1177
1178 if (pool->irqs != NULL)
1179 dal_irq_service_destroy(&pool->irqs);
1180 }
1181
1182 for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) {
1183 if (pool->engines[i] != NULL)
1184 dce110_engine_destroy(&pool->engines[i]);
1185 if (pool->hw_i2cs[i] != NULL) {
1186 kfree(pool->hw_i2cs[i]);
1187 pool->hw_i2cs[i] = NULL;
1188 }
1189 if (pool->sw_i2cs[i] != NULL) {
1190 kfree(pool->sw_i2cs[i]);
1191 pool->sw_i2cs[i] = NULL;
1192 }
1193 }
1194
1195 for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) {
1196 if (pool->opps[i] != NULL)
1197 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1198 }
1199
1200 for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) {
1201 if (pool->timing_generators[i] != NULL) {
1202 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1203 pool->timing_generators[i] = NULL;
1204 }
1205 }
1206
1207 for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) {
1208 if (pool->dwbc[i] != NULL) {
1209 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1210 pool->dwbc[i] = NULL;
1211 }
1212 if (pool->mcif_wb[i] != NULL) {
1213 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1214 pool->mcif_wb[i] = NULL;
1215 }
1216 }
1217
1218 for (i = 0; i < pool->audio_count; i++) {
1219 if (pool->audios[i])
1220 dce_aud_destroy(&pool->audios[i]);
1221 }
1222
1223 for (i = 0; i < pool->clk_src_count; i++) {
1224 if (pool->clock_sources[i] != NULL)
1225 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1226 }
1227
1228 if (pool->dp_clock_source != NULL)
1229 dcn20_clock_source_destroy(&pool->dp_clock_source);
1230
1231 for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) {
1232 if (pool->mpc_lut[i] != NULL) {
1233 dc_3dlut_func_release(pool->mpc_lut[i]);
1234 pool->mpc_lut[i] = NULL;
1235 }
1236 if (pool->mpc_shaper[i] != NULL) {
1237 dc_transfer_func_release(pool->mpc_shaper[i]);
1238 pool->mpc_shaper[i] = NULL;
1239 }
1240 }
1241
1242 for (i = 0; i < pool->pipe_count; i++) {
1243 if (pool->multiple_abms[i] != NULL)
1244 dce_abm_destroy(&pool->multiple_abms[i]);
1245 }
1246
1247 if (pool->psr != NULL)
1248 dmub_psr_destroy(&pool->psr);
1249
1250 if (pool->dccg != NULL)
1251 dcn_dccg_destroy(&pool->dccg);
1252
1253 if (pool->oem_device != NULL) {
1254 struct dc *dc = pool->oem_device->ctx->dc;
1255
1256 dc->link_srv->destroy_ddc_service(&pool->oem_device);
1257 }
1258 }
1259
dcn302_destroy_resource_pool(struct resource_pool ** pool)1260 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1261 {
1262 dcn302_resource_destruct(*pool);
1263 kfree(*pool);
1264 *pool = NULL;
1265 }
1266
dcn302_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1267 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1268 {
1269 DC_FP_START();
1270 dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1271 DC_FP_END();
1272 }
1273
dcn302_get_panel_config_defaults(struct dc_panel_config * panel_config)1274 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config)
1275 {
1276 *panel_config = panel_config_defaults;
1277 }
1278
1279 static struct resource_funcs dcn302_res_pool_funcs = {
1280 .destroy = dcn302_destroy_resource_pool,
1281 .link_enc_create = dcn302_link_encoder_create,
1282 .panel_cntl_create = dcn302_panel_cntl_create,
1283 .hpo_frl_link_enc_create = dcn302_hpo_frl_link_encoder_create,
1284 .validate_bandwidth = dcn30_validate_bandwidth,
1285 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1286 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1287 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1288 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1289 .release_pipe = dcn20_release_pipe,
1290 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1291 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1292 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1293 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1294 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1295 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1296 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1297 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1298 .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1299 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1300 .get_panel_config_defaults = dcn302_get_panel_config_defaults,
1301 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1302 .get_default_tiling_info = dcn10_get_default_tiling_info
1303 };
1304
1305 static struct dc_cap_funcs cap_funcs = {
1306 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1307 };
1308
1309 static const struct bios_registers bios_regs = {
1310 NBIO_SR(BIOS_SCRATCH_3),
1311 NBIO_SR(BIOS_SCRATCH_6)
1312 };
1313
1314 static const struct dccg_registers dccg_regs = {
1315 DCCG_REG_LIST_DCN3_02()
1316 };
1317
1318 static const struct dccg_shift dccg_shift = {
1319 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1320 };
1321
1322 static const struct dccg_mask dccg_mask = {
1323 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1324 };
1325
1326 #define abm_regs(id)\
1327 [id] = { ABM_DCN302_REG_LIST(id) }
1328
1329 static const struct dce_abm_registers abm_regs[] = {
1330 abm_regs(0),
1331 abm_regs(1),
1332 abm_regs(2),
1333 abm_regs(3),
1334 abm_regs(4)
1335 };
1336
1337 static const struct dce_abm_shift abm_shift = {
1338 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1339 };
1340
1341 static const struct dce_abm_mask abm_mask = {
1342 ABM_MASK_SH_LIST_DCN30(_MASK)
1343 };
1344
dcn302_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct resource_pool * pool)1345 static bool dcn302_resource_construct(
1346 uint8_t num_virtual_links,
1347 struct dc *dc,
1348 struct resource_pool *pool)
1349 {
1350 int i;
1351 struct dc_context *ctx = dc->ctx;
1352 struct irq_service_init_data init_data;
1353 struct ddc_service_init_data ddc_init_data = {0};
1354
1355 ctx->dc_bios->regs = &bios_regs;
1356
1357 pool->res_cap = &res_cap_dcn302;
1358
1359 pool->funcs = &dcn302_res_pool_funcs;
1360
1361 /*************************************************
1362 * Resource + asic cap harcoding *
1363 *************************************************/
1364 pool->underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1365 pool->pipe_count = pool->res_cap->num_timing_generator;
1366 pool->mpcc_count = pool->res_cap->num_timing_generator;
1367 dc->caps.max_downscale_ratio = 600;
1368 dc->caps.i2c_speed_in_khz = 100;
1369 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1370 dc->caps.max_cursor_size = 256;
1371 dc->caps.min_horizontal_blanking_period = 80;
1372 dc->caps.dmdata_alloc_size = 2048;
1373 dc->caps.mall_size_per_mem_channel = 4;
1374 /* total size = mall per channel * num channels * 1024 * 1024 */
1375 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1376 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1377 dc->caps.max_slave_planes = 2;
1378 dc->caps.max_slave_yuv_planes = 2;
1379 dc->caps.max_slave_rgb_planes = 2;
1380 dc->caps.post_blend_color_processing = true;
1381 dc->caps.force_dp_tps4_for_cp2520 = true;
1382 dc->caps.hdmi_hpo = true;
1383 dc->caps.extended_aux_timeout_support = true;
1384 dc->caps.dmcub_support = true;
1385 dc->caps.max_v_total = (1 << 15) - 1;
1386 dc->caps.vtotal_limited_by_fp2 = true;
1387
1388 /* Color pipeline capabilities */
1389 dc->caps.color.dpp.dcn_arch = 1;
1390 dc->caps.color.dpp.input_lut_shared = 0;
1391 dc->caps.color.dpp.icsc = 1;
1392 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1393 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1394 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1395 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1396 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1397 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1398 dc->caps.color.dpp.post_csc = 1;
1399 dc->caps.color.dpp.gamma_corr = 1;
1400 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1401 dc->caps.color.dpp.upsp_pre_scaler = 0;
1402
1403 dc->caps.color.dpp.hw_3d_lut = 1;
1404 dc->caps.color.dpp.ogam_ram = 1;
1405 // no OGAM ROM on DCN3
1406 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1407 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1408 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1409 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1410 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1411 dc->caps.color.dpp.ocsc = 0;
1412
1413 dc->caps.color.mpc.gamut_remap = 1;
1414 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;
1415 dc->caps.color.mpc.ogam_ram = 1;
1416 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1417 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1418 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1419 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1420 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1421 dc->caps.color.mpc.ocsc = 1;
1422 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
1423
1424 dc->caps.dp_hdmi21_pcon_support = true;
1425
1426 /* read VBIOS LTTPR caps */
1427 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1428 enum bp_result bp_query_result;
1429 uint8_t is_vbios_lttpr_enable = 0;
1430
1431 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1432 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1433 }
1434
1435 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1436 enum bp_result bp_query_result;
1437 uint8_t is_vbios_interop_enabled = 0;
1438
1439 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1440 &is_vbios_interop_enabled);
1441 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1442 }
1443 dc->check_config = config_defaults;
1444
1445 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1446 dc->debug = debug_defaults_drv;
1447
1448 // Init the vm_helper
1449 if (dc->vm_helper)
1450 vm_helper_init(dc->vm_helper, 16);
1451
1452 /*************************************************
1453 * Create resources *
1454 *************************************************/
1455
1456 /* Clock Sources for Pixel Clock*/
1457 pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1458 dcn302_clock_source_create(ctx, ctx->dc_bios,
1459 CLOCK_SOURCE_COMBO_PHY_PLL0,
1460 &clk_src_regs[0], false);
1461 pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1462 dcn302_clock_source_create(ctx, ctx->dc_bios,
1463 CLOCK_SOURCE_COMBO_PHY_PLL1,
1464 &clk_src_regs[1], false);
1465 pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1466 dcn302_clock_source_create(ctx, ctx->dc_bios,
1467 CLOCK_SOURCE_COMBO_PHY_PLL2,
1468 &clk_src_regs[2], false);
1469 pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1470 dcn302_clock_source_create(ctx, ctx->dc_bios,
1471 CLOCK_SOURCE_COMBO_PHY_PLL3,
1472 &clk_src_regs[3], false);
1473 pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1474 dcn302_clock_source_create(ctx, ctx->dc_bios,
1475 CLOCK_SOURCE_COMBO_PHY_PLL4,
1476 &clk_src_regs[4], false);
1477
1478 pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1479
1480 /* todo: not reuse phy_pll registers */
1481 pool->dp_clock_source =
1482 dcn302_clock_source_create(ctx, ctx->dc_bios,
1483 CLOCK_SOURCE_ID_DP_DTO,
1484 &clk_src_regs[0], true);
1485
1486 for (i = 0; i < (int)pool->clk_src_count; i++) {
1487 if (pool->clock_sources[i] == NULL) {
1488 dm_error("DC: failed to create clock sources!\n");
1489 BREAK_TO_DEBUGGER();
1490 goto create_fail;
1491 }
1492 }
1493
1494 /* DCCG */
1495 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1496 if (pool->dccg == NULL) {
1497 dm_error("DC: failed to create dccg!\n");
1498 BREAK_TO_DEBUGGER();
1499 goto create_fail;
1500 }
1501
1502 /* PP Lib and SMU interfaces */
1503 init_soc_bounding_box(dc, pool);
1504
1505 /* DML */
1506 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1507
1508 /* IRQ */
1509 init_data.ctx = dc->ctx;
1510 pool->irqs = dal_irq_service_dcn302_create(&init_data);
1511 if (!pool->irqs)
1512 goto create_fail;
1513
1514 /* HUBBUB */
1515 pool->hubbub = dcn302_hubbub_create(ctx);
1516 if (pool->hubbub == NULL) {
1517 BREAK_TO_DEBUGGER();
1518 dm_error("DC: failed to create hubbub!\n");
1519 goto create_fail;
1520 }
1521
1522 /* DIO */
1523 pool->dio = dcn302_dio_create(ctx);
1524 if (pool->dio == NULL) {
1525 BREAK_TO_DEBUGGER();
1526 dm_error("DC: failed to create dio!\n");
1527 goto create_fail;
1528 }
1529
1530 /* HUBPs, DPPs, OPPs and TGs */
1531 for (i = 0; i < (int)pool->pipe_count; i++) {
1532 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1533 if (pool->hubps[i] == NULL) {
1534 BREAK_TO_DEBUGGER();
1535 dm_error("DC: failed to create hubps!\n");
1536 goto create_fail;
1537 }
1538
1539 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1540 if (pool->dpps[i] == NULL) {
1541 BREAK_TO_DEBUGGER();
1542 dm_error("DC: failed to create dpps!\n");
1543 goto create_fail;
1544 }
1545 }
1546
1547 for (i = 0; i < pool->res_cap->num_opp; i++) {
1548 pool->opps[i] = dcn302_opp_create(ctx, i);
1549 if (pool->opps[i] == NULL) {
1550 BREAK_TO_DEBUGGER();
1551 dm_error("DC: failed to create output pixel processor!\n");
1552 goto create_fail;
1553 }
1554 }
1555
1556 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1557 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1558 if (pool->timing_generators[i] == NULL) {
1559 BREAK_TO_DEBUGGER();
1560 dm_error("DC: failed to create tg!\n");
1561 goto create_fail;
1562 }
1563 }
1564 pool->timing_generator_count = i;
1565
1566 /* PSR */
1567 pool->psr = dmub_psr_create(ctx);
1568 if (pool->psr == NULL) {
1569 dm_error("DC: failed to create psr!\n");
1570 BREAK_TO_DEBUGGER();
1571 goto create_fail;
1572 }
1573
1574 /* ABMs */
1575 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1576 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1577 if (pool->multiple_abms[i] == NULL) {
1578 dm_error("DC: failed to create abm for pipe %d!\n", i);
1579 BREAK_TO_DEBUGGER();
1580 goto create_fail;
1581 }
1582 }
1583
1584 /* MPC and DSC */
1585 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1586 if (pool->mpc == NULL) {
1587 BREAK_TO_DEBUGGER();
1588 dm_error("DC: failed to create mpc!\n");
1589 goto create_fail;
1590 }
1591
1592 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1593 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1594 if (pool->dscs[i] == NULL) {
1595 BREAK_TO_DEBUGGER();
1596 dm_error("DC: failed to create display stream compressor %d!\n", i);
1597 goto create_fail;
1598 }
1599 }
1600
1601 /* DWB and MMHUBBUB */
1602 if (!dcn302_dwbc_create(ctx, pool)) {
1603 BREAK_TO_DEBUGGER();
1604 dm_error("DC: failed to create dwbc!\n");
1605 goto create_fail;
1606 }
1607
1608 if (!dcn302_mmhubbub_create(ctx, pool)) {
1609 BREAK_TO_DEBUGGER();
1610 dm_error("DC: failed to create mcif_wb!\n");
1611 goto create_fail;
1612 }
1613
1614 /* AUX and I2C */
1615 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1616 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1617 if (pool->engines[i] == NULL) {
1618 BREAK_TO_DEBUGGER();
1619 dm_error("DC:failed to create aux engine!!\n");
1620 goto create_fail;
1621 }
1622 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1623 if (pool->hw_i2cs[i] == NULL) {
1624 BREAK_TO_DEBUGGER();
1625 dm_error("DC:failed to create hw i2c!!\n");
1626 goto create_fail;
1627 }
1628 pool->sw_i2cs[i] = NULL;
1629 }
1630
1631 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1632 if (!resource_construct(num_virtual_links, dc, pool,
1633 &res_create_funcs))
1634 goto create_fail;
1635
1636 /* HW Sequencer and Plane caps */
1637 dcn302_hw_sequencer_construct(dc);
1638
1639 dc->caps.max_planes = pool->pipe_count;
1640
1641 for (i = 0; i < (int)dc->caps.max_planes; ++i)
1642 dc->caps.planes[i] = plane_cap;
1643
1644 dc->caps.max_odm_combine_factor = 4;
1645
1646 dc->cap_funcs = cap_funcs;
1647
1648 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1649 ddc_init_data.ctx = dc->ctx;
1650 ddc_init_data.link = NULL;
1651 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1652 ddc_init_data.id.enum_id = 0;
1653 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1654 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1655 } else {
1656 pool->oem_device = NULL;
1657 }
1658
1659 return true;
1660
1661 create_fail:
1662
1663 dcn302_resource_destruct(pool);
1664
1665 return false;
1666 }
1667
dcn302_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1668 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1669 {
1670 struct resource_pool *pool = kzalloc_obj(struct resource_pool);
1671
1672 if (!pool)
1673 return NULL;
1674
1675 if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
1676 return pool;
1677
1678 BREAK_TO_DEBUGGER();
1679 kfree(pool);
1680 return NULL;
1681 }
1682