| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 502 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
524 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn31_calculate_wm_and_dlg_fp()
525 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn31_calculate_wm_and_dlg_fp()
526 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn31_calculate_wm_and_dlg_fp()
527 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dcn31_calculate_wm_and_dlg_fp()
528 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&cont… in dcn31_calculate_wm_and_dlg_fp()
529 …context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn31_calculate_wm_and_dlg_fp()
530 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn31_calculate_wm_and_dlg_fp()
531 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 807 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
808 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
809 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
810 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
811 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
812 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
813 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_c… in dml21_copy_clocks_to_dc_state()
814 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
815 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
816 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
533 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
778 …if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_K… in dcn32_override_min_req_dcfclk()
779 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ; in dcn32_override_min_req_dcfclk()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 60 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
1252 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_calculate_cab_allocation()
1380 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_prepare_bandwidth()
1386 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn401_prepare_bandwidth()
1391 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn401_prepare_bandwidth()
1405 &context->bw_ctx.bw.dcn.watermarks, in dcn401_prepare_bandwidth()
1410 …dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs,… in dcn401_prepare_bandwidth()
1415 compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; in dcn401_prepare_bandwidth()
1416 …dc->optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_size); in dcn401_prepare_bandwidth()
1427 if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { in dcn401_prepare_bandwidth()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 941 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * in dc_dmub_setup_subvp_dmub_command()
1817 …memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub… in dc_dmub_srv_rb_based_fams2_update_config()
1825 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { in dc_dmub_srv_rb_based_fams2_update_config()
1827 …struct dmub_rb_cmd_fams2 *stream_sub_state_cmd = &cmd[i+1+context->bw_ctx.bw.dcn.fams2_global_conf… in dc_dmub_srv_rb_based_fams2_update_config()
1842 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], in dc_dmub_srv_rb_based_fams2_update_config()
1846 &context->bw_ctx.bw.dcn.fams2_stream_sub_params[i], in dc_dmub_srv_rb_based_fams2_update_config()
1853 …global_cmd->config.global.features.bits.enable = enable && context->bw_ctx.bw.dcn.fams2_global_con… in dc_dmub_srv_rb_based_fams2_update_config()
1859 …cmd[2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pend… in dc_dmub_srv_rb_based_fams2_update_config()
1860 num_cmds += 2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams; in dc_dmub_srv_rb_based_fams2_update_config()
1885 memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config, in dc_dmub_srv_ib_based_fams2_update_config()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 233 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn32_calculate_cab_allocation()
758 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn32_initialize_min_clocks()
1799 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn32_prepare_bandwidth()
1803 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1805 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn32_prepare_bandwidth()
1810 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn32_prepare_bandwidth()
1815 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_prepare_bandwidth()
1818 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1822 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn32_prepare_bandwidth()
1856 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn32_program_outstanding_updates()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 432 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_auto_dpm_test_log()
1229 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1238 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1245 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context); in dcn401_update_clocks()
1342 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn401_set_hard_min_memclk()
1343 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz; in dcn401_set_hard_min_memclk()
1344 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_set_hard_min_memclk()
1364 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn401_get_hard_min_memclk()
1371 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz; in dcn401_get_hard_min_fclk()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 2368 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth()
2381 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth()
2391 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
2397 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth()
2405 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; in dcn20_prepare_bandwidth()
2406 dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); in dcn20_prepare_bandwidth()
2425 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth()
2432 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
2438 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn20_optimize_bandwidth()
2443 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn20_optimize_bandwidth()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 742 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
743 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_log_hw_state()
744 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
745 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
746 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()
747 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
748 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
1777 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dcn10_init_hw()
1778 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz; in dcn10_init_hw()
3021 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 450 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn30_set_writeback()
1172 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && in dcn30_hardware_release()
1193 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switchi… in dcn30_prepare_bandwidth()
1195 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn30_prepare_bandwidth()
1200 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn30_prepare_bandwidth()
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_helpers.c | 1349 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
1350 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()
1352 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 194 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rv1_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 528 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn32_auto_dpm_test_log()
626 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn32_update_clocks()
729 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_update_clocks()
|
| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 6 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
51 means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_state.c | 979 is_fams2_in_use |= state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; in dc_state_is_fams2_in_use()
982 is_fams2_in_use |= dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; in dc_state_is_fams2_in_use()
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 583 struct dcn_bw_output dcn; member
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_notify_host_router_bw()
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks()
1232 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks_fpga()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 198 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 638 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn351_decide_zstate_support()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 619 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn35_decide_zstate_support()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1397 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; in dcn30_set_mcif_arb_params()
1976 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch()
2016 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn30_setup_mclk_switch_using_fw_based_vblank_stretch()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks()
|