/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
H A D | dcn321_fpu.c | 109 .dcfclk_mhz = 1434.0, 164 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple() 165 …float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct… in get_optimal_ntuple() 173 …entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_i… in get_optimal_ntuple() 181 …entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ide… in get_optimal_ntuple() 197 …sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.p… in calculate_net_bw_in_kbytes_sec() 281 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) in sort_entries_with_same_bw() 323 if (max_clk_limit->dcfclk_mhz != 0) in override_max_clk_values() 324 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; in override_max_clk_values() 365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_policy.c | 33 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple() 34 …float bw_on_sdp = (float)(entry->dcfclk_mhz * socbb->return_bus_width_bytes * ((float)socbb->pct_i… in get_optimal_ntuple() 42 …entry->dcfclk_mhz = bw_on_fabric / (socbb->return_bus_width_bytes * ((float)socbb->pct_ideal_sdp_b… in get_optimal_ntuple() 50 …entry->dcfclk_mhz = bw_on_dram / (socbb->return_bus_width_bytes * ((float)socbb->pct_ideal_sdp_bw_… in get_optimal_ntuple() 62 …float sdp_bw_mbytes_sec = (float)(entry->dcfclk_mhz * socbb->return_bus_width_bytes * ((float)socb… in calculate_net_bw_in_mbytes_sec() 102 table->state_array[index].dcfclk_mhz = (int)entry->dcfclk_mhz; in insert_entry_into_table_sorted() 127 unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz; in dml2_policy_build_synthetic_soc_states() 137 if (p->in_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz) in dml2_policy_build_synthetic_soc_states() 138 max_dcfclk_mhz = (int) p->in_states->state_array[i].dcfclk_mhz; in dml2_policy_build_synthetic_soc_states() 178 s->entry.dcfclk_mhz = p->dcfclk_stas_mhz[i]; in dml2_policy_build_synthetic_soc_states() [all …]
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H A D | dml2_translation_helper.c | 364 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states() 386 p->in_states->state_array[1].dcfclk_mhz = 1564.0; in dml2_init_soc_states() 400 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states() 422 p->in_states->state_array[1].dcfclk_mhz = 1434.0; in dml2_init_soc_states() 435 p->in_states->state_array[0].dcfclk_mhz = 200; //300.0; in dml2_init_soc_states() 457 p->in_states->state_array[1].dcfclk_mhz = 1800; //1564.0; in dml2_init_soc_states() 503 p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; in dml2_init_soc_states() 507 p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz; in dml2_init_soc_states() 520 …p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dc… in dml2_init_soc_states() 523 p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz; in dml2_init_soc_states() [all …]
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H A D | dml2_wrapper.h | 155 unsigned int dcfclk_mhz; member
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
H A D | dcn302_fpu.c | 200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local 224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box() 225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 264 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box() 265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box() 288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box() 297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box() 303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
H A D | dcn303_fpu.c | 196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local 220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box() 221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 258 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box() 259 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 289 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box() 293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box() 303 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box() 309 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.c | 119 .dcfclk_mhz = 400.0, 131 .dcfclk_mhz = 400.0, 143 .dcfclk_mhz = 608.0, 155 .dcfclk_mhz = 676.0, 167 .dcfclk_mhz = 810.0, 304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel() 344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_fpu_update_bw_bounding_box() 351 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_fpu_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 226 .dcfclk_mhz = 560.0, 237 .dcfclk_mhz = 694.0, 248 .dcfclk_mhz = 875.0, 259 .dcfclk_mhz = 1000.0, 270 .dcfclk_mhz = 1200.0, 282 .dcfclk_mhz = 1200.0, 337 .dcfclk_mhz = 560.0, 348 .dcfclk_mhz = 694.0, 359 .dcfclk_mhz = 875.0, 370 .dcfclk_mhz = 1000.0, [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.c | 218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu() 231 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu() 233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu() 235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 130 .dcfclk_mhz = 1564.0, 195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu() 197 …nt16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu() 205 …entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu() 379 sdp_bw_kbytes_sec = entry->dcfclk_mhz * in calculate_net_bw_in_kbytes_sec() 396 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple() 397 …float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_i… in get_optimal_ntuple() 405 …entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ide… in get_optimal_ntuple() 413 …entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal… in get_optimal_ntuple() 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_set_phantom_stream_timing() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
H A D | dcn35_fpu.c | 258 if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <= in dcn35_update_bw_bounding_box_fpu() 259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu() 272 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu() 274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu() 275 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu() 277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu() 278 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu() 358 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu() 359 clock_limits[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp() 620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box() 629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box() 697 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box() 759 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box() 760 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box() 769 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn316_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/ |
H A D | dcn401_fpu.c | 22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu() 24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu() 32 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu() 200 if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz) in dcn401_update_bw_bounding_box_fpu() 201 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn401_update_bw_bounding_box_fpu() 202 dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz; in dcn401_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges() 407 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges() 504 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn315_clk_mgr_helper_populate_bw_params() 514 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn315_clk_mgr_helper_populate_bw_params() 526 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0]; in dcn315_clk_mgr_helper_populate_bw_params() 546 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params() 547 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params() 566 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn315_clk_mgr_helper_populate_bw_params()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges() 412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges() 497 .dcfclk_mhz = 400, 504 .dcfclk_mhz = 483, 511 .dcfclk_mhz = 602, 518 .dcfclk_mhz = 738, 593 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params() 598 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCF… in vg_clk_mgr_helper_populate_bw_params()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 477 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges() 479 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges() 581 .dcfclk_mhz = 400, 588 .dcfclk_mhz = 483, 595 .dcfclk_mhz = 602, 602 .dcfclk_mhz = 738, 670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 429 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg() 439 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg() 455 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg() 610 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk() 646 unsigned int *dcfclk_mhz, in dcn30_fpu_update_bw_bounding_box() argument 658 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box() 659 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
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H A D | dcn30_fpu.h | 63 unsigned int *dcfclk_mhz,
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
H A D | dcn35_clk_mgr.c | 683 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges() 686 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges() 864 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn35_clk_mgr_helper_populate_bw_params() 874 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn35_clk_mgr_helper_populate_bw_params() 893 bw_params->clk_table.entries[i].dcfclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params() 935 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params() 936 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params() 952 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn35_clk_mgr_helper_populate_bw_params()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
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/linux/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | display_mode_structs.h | 159 double dcfclk_mhz; member 553 double dcfclk_mhz; member
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
H A D | dcn201_resource.c | 143 .dcfclk_mhz = 1000.0, 154 .dcfclk_mhz = 1000.0, 165 .dcfclk_mhz = 1000.0, 176 .dcfclk_mhz = 1000.0, 188 .dcfclk_mhz = 1000.0,
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges() 369 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges() 535 bw_params->clk_table.entries[i].dcfclk_mhz = temp; in dcn316_clk_mgr_helper_populate_bw_params()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
H A D | dcn401_clk_mgr.c | 178 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table() 238 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn401_init_clocks() 240 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn401_init_clocks() 241 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks() 242 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz) in dcn401_init_clocks() 243 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0; in dcn401_init_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
H A D | dml_top_display_cfg_types.h | 461 double dcfclk_mhz; member
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