| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 225 .dcfclk_mhz = 560.0,
236 .dcfclk_mhz = 694.0,
247 .dcfclk_mhz = 875.0,
258 .dcfclk_mhz = 1000.0,
269 .dcfclk_mhz = 1200.0,
281 .dcfclk_mhz = 1200.0,
336 .dcfclk_mhz = 560.0,
347 .dcfclk_mhz = 694.0,
358 .dcfclk_mhz = 875.0,
369 .dcfclk_mhz = 1000.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 130 .dcfclk_mhz = 1564.0,
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
197 …nt16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
205 …entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
379 sdp_bw_kbytes_sec = entry->dcfclk_mhz * in calculate_net_bw_in_kbytes_sec()
396 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple()
397 …float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_i… in get_optimal_ntuple()
405 …entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ide… in get_optimal_ntuple()
413 …entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal… in get_optimal_ntuple()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_set_phantom_stream_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box_fpu()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box_fpu()
697 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box_fpu()
759 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box_fpu()
760 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box_fpu()
769 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn316_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 370 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
392 p->in_states->state_array[1].dcfclk_mhz = 1564.0; in dml2_init_soc_states()
406 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
428 p->in_states->state_array[1].dcfclk_mhz = 1434.0; in dml2_init_soc_states()
443 p->in_states->state_array[0].dcfclk_mhz = 200; //300.0; in dml2_init_soc_states()
465 p->in_states->state_array[1].dcfclk_mhz = 1800; //1564.0; in dml2_init_soc_states()
511 p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; in dml2_init_soc_states()
515 p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz; in dml2_init_soc_states()
529 …p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dc… in dml2_init_soc_states()
532 p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz; in dml2_init_soc_states()
[all …]
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| H A D | dml2_wrapper_fpu.c | 416 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; in dml2_validate_and_build_resource()
474 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; in dml2_validate_and_build_resource()
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| H A D | display_mode_util.c | 644 dml_print("DML: state_bbox: dcfclk_mhz = %f\n", state->dcfclk_mhz); in dml_print_soc_state_bounding_box()
707 dml_print("DML: clk_cfg: dcfclk_mhz = %f\n", clk_cfg->dcfclk_mhz); in dml_print_clk_cfg()
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| H A D | display_mode_core_structs.h | 285 dml_float_t dcfclk_mhz; member
669 dml_float_t dcfclk_mhz; member
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| H A D | display_mode_core.c | 7930 mode_lib->ms.DCFCLKState[j] = mode_lib->ms.state.dcfclk_mhz; in dml_core_mode_support()
8032 UseMinimumDCFCLK_params->DCFCLKPerState = mode_lib->ms.state.dcfclk_mhz; in dml_core_mode_support()
8348 locals->Dcfclk = clk_cfg->dcfclk_mhz; in dml_core_mode_programming()
10104 mode_lib->ms.DCFCLK = (dml_float_t)state->dcfclk_mhz; in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 159 double dcfclk_mhz; member
553 double dcfclk_mhz; member
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| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2139 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2162 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2163 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2200 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()
2201 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2232 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2236 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2245 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2251 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2257 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 144 .dcfclk_mhz = 1000.0,
155 .dcfclk_mhz = 1000.0,
166 .dcfclk_mhz = 1000.0,
177 .dcfclk_mhz = 1000.0,
189 .dcfclk_mhz = 1000.0,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/ |
| H A D | dml_top_display_cfg_types.h | 482 double dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/ |
| H A D | dcn42_soc_and_ip_translator.c | 56 dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 658 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn42_build_watermark_ranges()
661 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn42_build_watermark_ranges()
961 dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn42_get_smu_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 2675 double dcfclk_mhz, in dml_get_return_bandwidth_available() argument
2680 double ideal_sdp_bandwidth = (double)soc->return_bus_width_bytes * dcfclk_mhz; in dml_get_return_bandwidth_available()
2745 DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz); in dml_get_return_bandwidth_available()
2767 double dcfclk_mhz, in calculate_bandwidth_available() argument
2773 DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz); in calculate_bandwidth_available()
2786 dcfclk_mhz, in calculate_bandwidth_available()
2790 …n] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
2800 …m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 1, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
2801 …m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
|