Searched refs:dcfclk_mhz (Results 1 – 9 of 9) sorted by relevance
522 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn314_build_watermark_ranges()525 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()678 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()689 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn314_clk_mgr_helper_populate_bw_params()705 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK… in dcn314_clk_mgr_helper_populate_bw_params()734 if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()735 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()749 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn314_clk_mgr_helper_populate_bw_params()
29 uint32_t dcfclk_mhz; member
908 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn35_build_watermark_ranges()911 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()1106 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[entry_idx]) in dcn35_clk_mgr_helper_populate_bw_params()1116 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = clock_table->DcfClocks[entry_idx]; in dcn35_clk_mgr_helper_populate_bw_params()1136 bw_params->clk_table.entries[i].dcfclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()1178 if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()1179 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()1195 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn35_clk_mgr_helper_populate_bw_params()
159 double dcfclk_mhz; member553 double dcfclk_mhz; member
2267 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local2290 if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()2291 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()2328 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()2329 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()2360 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()2364 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2373 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()2379 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2385 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
451 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn31_build_watermark_ranges()454 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()616 …bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table… in dcn31_clk_mgr_helper_populate_bw_params()
416 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; in dml2_validate_and_build_resource()474 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; in dml2_validate_and_build_resource()
285 dml_float_t dcfclk_mhz; member669 dml_float_t dcfclk_mhz; member
502 dc_limit->dcfclk_mhz = dcn60_get_dc_mode_limit_mhz(&init_table->PPClocks[PPCLK_DCFCLK]); in dcn60_populate_dc_mode_limit()531 clk_table->entries[i].dcfclk_mhz = dpm_clk->Clocks[i]; in dcn60_populate_clk_table()