| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 101 .dcfclk_mhz = 400.0,
114 .dcfclk_mhz = 600.0,
127 .dcfclk_mhz = 738.0,
140 .dcfclk_mhz = 800.0,
153 .dcfclk_mhz = 873.0,
166 .dcfclk_mhz = 960.0,
179 .dcfclk_mhz = 1067.0,
192 .dcfclk_mhz = 1200.0,
292 if (dcn3_51_soc.clock_limits[j].dcfclk_mhz <= in dcn351_update_bw_bounding_box_fpu()
293 clk_table->entries[i].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 258 if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <= in dcn35_update_bw_bounding_box_fpu()
259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
272 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu()
275 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
278 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
358 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
359 clock_limits[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
697 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box()
759 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box()
760 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box()
769 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 477 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
479 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
581 .dcfclk_mhz = 400,
588 .dcfclk_mhz = 483,
595 .dcfclk_mhz = 602,
602 .dcfclk_mhz = 738,
670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 887 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges()
890 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
1084 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn35_clk_mgr_helper_populate_bw_params()
1094 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn35_clk_mgr_helper_populate_bw_params()
1113 bw_params->clk_table.entries[i].dcfclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1155 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1156 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1172 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn35_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 159 double dcfclk_mhz; member
553 double dcfclk_mhz; member
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| H A D | display_mode_lib.c | 281 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params()
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| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 186 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table()
245 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn401_init_clocks()
247 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, P… in dcn401_init_clocks()
248 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks()
249 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz) in dcn401_init_clocks()
250 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0; in dcn401_init_clocks()
320 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz) || in dcn401_is_dc_mode_present()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 117 unsigned int dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_util.c | 632 dml_print("DML: state_bbox: dcfclk_mhz = %f\n", state->dcfclk_mhz); in dml_print_soc_state_bounding_box()
693 dml_print("DML: clk_cfg: dcfclk_mhz = %f\n", clk_cfg->dcfclk_mhz); in dml_print_clk_cfg()
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| H A D | display_mode_core_structs.h | 285 dml_float_t dcfclk_mhz; member
669 dml_float_t dcfclk_mhz; member
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| H A D | display_mode_core.c | 7913 mode_lib->ms.DCFCLKState[j] = mode_lib->ms.state.dcfclk_mhz; in dml_core_mode_support()
8015 UseMinimumDCFCLK_params->DCFCLKPerState = mode_lib->ms.state.dcfclk_mhz; in dml_core_mode_support()
8331 locals->Dcfclk = clk_cfg->dcfclk_mhz; in dml_core_mode_programming()
10087 mode_lib->ms.DCFCLK = (dml_float_t)state->dcfclk_mhz; in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
194 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 761 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn32_initialize_min_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 2665 double dcfclk_mhz, in dml_get_return_bandwidth_available() argument
2670 double ideal_sdp_bandwidth = (double)soc->return_bus_width_bytes * dcfclk_mhz; in dml_get_return_bandwidth_available()
2735 DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz); in dml_get_return_bandwidth_available()
2757 double dcfclk_mhz, in calculate_bandwidth_available() argument
2763 DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz); in calculate_bandwidth_available()
2776 dcfclk_mhz, in calculate_bandwidth_available()
2780 …n] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
2790 …m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 1, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
2791 …m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_… in calculate_bandwidth_available()
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