Searched refs:dcfclk (Results 1 – 13 of 13) sorted by relevance
35 double *dcfclk) in get_minimum_clocks_for_latency() argument44 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; in get_minimum_clocks_for_latency()306 …ult = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.dcfclk_khz, &state_table->dcfclk); in map_soc_min_clocks_to_dpm_fine_grained()313 …round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch.dcfclk_khz, &state_table->dcfclk); in map_soc_min_clocks_to_dpm_fine_grained()320 …esult = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.dcfclk_khz, &state_table->dcfclk); in map_soc_min_clocks_to_dpm_fine_grained()328 …xt_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch_no_throttle.dcfclk_khz, &state_table->dcfclk) || in map_soc_min_clocks_to_dpm_fine_grained()347 …if (display_cfg->min_clocks.dcn4x.active.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()350 display_cfg->min_clocks.dcn4x.active.dcfclk_khz = state_table->dcfclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()361 if (display_cfg->min_clocks.dcn4x.idle.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()364 display_cfg->min_clocks.dcn4x.idle.dcfclk_khz = state_table->dcfclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()[all …]
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp() local494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()495 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()502 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
126 struct dml2_clk_table dcfclk; member
1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()1226 …v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1234 …if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1235 …->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_wi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1237 …v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1239 …byte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latenc… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1241 …v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1242 …if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1243 …->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_wi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()1245 …v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()[all …]
494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()577 v->dcfclk = v->dcfclkv_nom0p8;598 v->dcfclk = v->dcfclkv_max0p9;618 v->dcfclk = v->dcfclk_per_state[v->voltage_level];1163 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
184 uint32_t dcfclk; member
315 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in rn_dump_clk_registers()342 regs_and_bypass->dcfclk, in rn_dump_clk_registers()
38 unsigned int dcfclk; member
681 !dc->work_arounds.clock_update_disable_mask.dcfclk) { in dcn32_update_clocks()928 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
627 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in dcn35_save_clk_registers()652 regs_and_bypass->dcfclk, in dcn35_save_clk_registers()
379 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()511 clk_register_dump.dcfclk, in dcn401_auto_dpm_test_log()
382 uint8_t dcfclk : 1; member
7973 mode_lib->ms.MaxDCFCLK = (double)min_clk_table->max_clocks_khz.dcfclk / 1000; in dml_core_mode_support()