1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
3 *
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28
29
30 #include "stream_encoder.h"
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce120_resource.h"
34
35 #include "dce112/dce112_resource.h"
36
37 #include "dce110/dce110_resource.h"
38 #include "dio/virtual/virtual_stream_encoder.h"
39 #include "dce120/dce120_timing_generator.h"
40 #include "irq/dce120/irq_service_dce120.h"
41 #include "dce/dce_opp.h"
42 #include "dce/dce_clock_source.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_mem_input.h"
45 #include "dce/dce_panel_cntl.h"
46
47 #include "dce110/dce110_hwseq.h"
48 #include "dce120/dce120_hwseq.h"
49 #include "dce/dce_transform.h"
50 #include "clk_mgr.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_link_encoder.h"
53 #include "dce/dce_stream_encoder.h"
54 #include "dce/dce_hwseq.h"
55 #include "dce/dce_abm.h"
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_i2c.h"
59
60 #include "dce/dce_12_0_offset.h"
61 #include "dce/dce_12_0_sh_mask.h"
62 #include "soc15_hw_ip.h"
63 #include "vega10_ip_offset.h"
64 #include "nbio/nbio_6_1_offset.h"
65 #include "mmhub/mmhub_1_0_offset.h"
66 #include "mmhub/mmhub_1_0_sh_mask.h"
67 #include "reg_helper.h"
68
69 #include "dce100/dce100_resource.h"
70 #include "link_service.h"
71
72 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
74 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
76 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
78 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
80 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
82 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
84 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
86 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #endif
88
89 enum dce120_clk_src_array_id {
90 DCE120_CLK_SRC_PLL0,
91 DCE120_CLK_SRC_PLL1,
92 DCE120_CLK_SRC_PLL2,
93 DCE120_CLK_SRC_PLL3,
94 DCE120_CLK_SRC_PLL4,
95 DCE120_CLK_SRC_PLL5,
96
97 DCE120_CLK_SRC_TOTAL
98 };
99
100 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
101 {
102 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
103 },
104 {
105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
106 },
107 {
108 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
109 },
110 {
111 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
112 },
113 {
114 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
118 }
119 };
120
121 /* begin *********************
122 * macros to expend register list macro defined in HW object header file */
123
124 #define BASE_INNER(seg) \
125 DCE_BASE__INST0_SEG ## seg
126
127 #define NBIO_BASE_INNER(seg) \
128 NBIF_BASE__INST0_SEG ## seg
129
130 #define NBIO_BASE(seg) \
131 NBIO_BASE_INNER(seg)
132
133 /* compile time expand base address. */
134 #define BASE(seg) \
135 BASE_INNER(seg)
136
137 #define SR(reg_name)\
138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
139 mm ## reg_name
140
141 #define SRI(reg_name, block, id)\
142 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
144
145 /* MMHUB */
146 #define MMHUB_BASE_INNER(seg) \
147 MMHUB_BASE__INST0_SEG ## seg
148
149 #define MMHUB_BASE(seg) \
150 MMHUB_BASE_INNER(seg)
151
152 #define MMHUB_SR(reg_name)\
153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
154 mm ## reg_name
155
156 /* macros to expend register list macro defined in HW object header file
157 * end *********************/
158
159
160 static const struct dce_dmcu_registers dmcu_regs = {
161 DMCU_DCE110_COMMON_REG_LIST()
162 };
163
164 static const struct dce_dmcu_shift dmcu_shift = {
165 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
166 };
167
168 static const struct dce_dmcu_mask dmcu_mask = {
169 DMCU_MASK_SH_LIST_DCE110(_MASK)
170 };
171
172 static const struct dce_abm_registers abm_regs = {
173 ABM_DCE110_COMMON_REG_LIST()
174 };
175
176 static const struct dce_abm_shift abm_shift = {
177 ABM_MASK_SH_LIST_DCE110(__SHIFT)
178 };
179
180 static const struct dce_abm_mask abm_mask = {
181 ABM_MASK_SH_LIST_DCE110(_MASK)
182 };
183
184 #define ipp_regs(id)\
185 [id] = {\
186 IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188
189 static const struct dce_ipp_registers ipp_regs[] = {
190 ipp_regs(0),
191 ipp_regs(1),
192 ipp_regs(2),
193 ipp_regs(3),
194 ipp_regs(4),
195 ipp_regs(5)
196 };
197
198 static const struct dce_ipp_shift ipp_shift = {
199 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
200 };
201
202 static const struct dce_ipp_mask ipp_mask = {
203 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
204 };
205
206 #define transform_regs(id)\
207 [id] = {\
208 XFM_COMMON_REG_LIST_DCE110(id)\
209 }
210
211 static const struct dce_transform_registers xfm_regs[] = {
212 transform_regs(0),
213 transform_regs(1),
214 transform_regs(2),
215 transform_regs(3),
216 transform_regs(4),
217 transform_regs(5)
218 };
219
220 static const struct dce_transform_shift xfm_shift = {
221 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
222 };
223
224 static const struct dce_transform_mask xfm_mask = {
225 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
226 };
227
228 #define aux_regs(id)\
229 [id] = {\
230 AUX_REG_LIST(id)\
231 }
232
233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 aux_regs(0),
235 aux_regs(1),
236 aux_regs(2),
237 aux_regs(3),
238 aux_regs(4),
239 aux_regs(5)
240 };
241
242 #define hpd_regs(id)\
243 [id] = {\
244 HPD_REG_LIST(id)\
245 }
246
247 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
248 hpd_regs(0),
249 hpd_regs(1),
250 hpd_regs(2),
251 hpd_regs(3),
252 hpd_regs(4),
253 hpd_regs(5)
254 };
255
256 #define link_regs(id)\
257 [id] = {\
258 LE_DCE120_REG_LIST(id), \
259 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
260 }
261
262 static const struct dce110_link_enc_registers link_enc_regs[] = {
263 link_regs(0),
264 link_regs(1),
265 link_regs(2),
266 link_regs(3),
267 link_regs(4),
268 link_regs(5),
269 link_regs(6),
270 };
271
272
273 #define stream_enc_regs(id)\
274 [id] = {\
275 SE_COMMON_REG_LIST(id),\
276 .TMDS_CNTL = 0,\
277 }
278
279 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
280 stream_enc_regs(0),
281 stream_enc_regs(1),
282 stream_enc_regs(2),
283 stream_enc_regs(3),
284 stream_enc_regs(4),
285 stream_enc_regs(5)
286 };
287
288 static const struct dce_stream_encoder_shift se_shift = {
289 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
290 };
291
292 static const struct dce_stream_encoder_mask se_mask = {
293 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
294 };
295
296 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
297 { DCE_PANEL_CNTL_REG_LIST() }
298 };
299
300 static const struct dce_panel_cntl_shift panel_cntl_shift = {
301 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
302 };
303
304 static const struct dce_panel_cntl_mask panel_cntl_mask = {
305 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
306 };
307
308 static const struct dce110_aux_registers_shift aux_shift = {
309 DCE12_AUX_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dce110_aux_registers_mask aux_mask = {
313 DCE12_AUX_MASK_SH_LIST(_MASK)
314 };
315
316 #define opp_regs(id)\
317 [id] = {\
318 OPP_DCE_120_REG_LIST(id),\
319 }
320
321 static const struct dce_opp_registers opp_regs[] = {
322 opp_regs(0),
323 opp_regs(1),
324 opp_regs(2),
325 opp_regs(3),
326 opp_regs(4),
327 opp_regs(5)
328 };
329
330 static const struct dce_opp_shift opp_shift = {
331 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
332 };
333
334 static const struct dce_opp_mask opp_mask = {
335 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
336 };
337 #define aux_engine_regs(id)\
338 [id] = {\
339 AUX_COMMON_REG_LIST(id), \
340 .AUX_RESET_MASK = 0 \
341 }
342
343 static const struct dce110_aux_registers aux_engine_regs[] = {
344 aux_engine_regs(0),
345 aux_engine_regs(1),
346 aux_engine_regs(2),
347 aux_engine_regs(3),
348 aux_engine_regs(4),
349 aux_engine_regs(5)
350 };
351
352 #define audio_regs(id)\
353 [id] = {\
354 AUD_COMMON_REG_LIST(id)\
355 }
356
357 static const struct dce_audio_registers audio_regs[] = {
358 audio_regs(0),
359 audio_regs(1),
360 audio_regs(2),
361 audio_regs(3),
362 audio_regs(4),
363 audio_regs(5),
364 audio_regs(6),
365 };
366
367 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
370 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
371
372 static const struct dce_audio_shift audio_shift = {
373 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
374 };
375
376 static const struct dce_audio_mask audio_mask = {
377 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
378 };
379
map_transmitter_id_to_phy_instance(enum transmitter transmitter)380 static int map_transmitter_id_to_phy_instance(
381 enum transmitter transmitter)
382 {
383 switch (transmitter) {
384 case TRANSMITTER_UNIPHY_A:
385 return 0;
386 case TRANSMITTER_UNIPHY_B:
387 return 1;
388 case TRANSMITTER_UNIPHY_C:
389 return 2;
390 case TRANSMITTER_UNIPHY_D:
391 return 3;
392 case TRANSMITTER_UNIPHY_E:
393 return 4;
394 case TRANSMITTER_UNIPHY_F:
395 return 5;
396 case TRANSMITTER_UNIPHY_G:
397 return 6;
398 default:
399 ASSERT(0);
400 return 0;
401 }
402 }
403
404 #define clk_src_regs(index, id)\
405 [index] = {\
406 CS_COMMON_REG_LIST_DCE_112(id),\
407 }
408
409 static const struct dce110_clk_src_regs clk_src_regs[] = {
410 clk_src_regs(0, A),
411 clk_src_regs(1, B),
412 clk_src_regs(2, C),
413 clk_src_regs(3, D),
414 clk_src_regs(4, E),
415 clk_src_regs(5, F)
416 };
417
418 static const struct dce110_clk_src_shift cs_shift = {
419 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
420 };
421
422 static const struct dce110_clk_src_mask cs_mask = {
423 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
424 };
425
dce120_opp_create(struct dc_context * ctx,uint32_t inst)426 static struct output_pixel_processor *dce120_opp_create(
427 struct dc_context *ctx,
428 uint32_t inst)
429 {
430 struct dce110_opp *opp =
431 kzalloc_obj(struct dce110_opp);
432
433 if (!opp)
434 return NULL;
435
436 dce110_opp_construct(opp,
437 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
438 return &opp->base;
439 }
dce120_aux_engine_create(struct dc_context * ctx,uint32_t inst)440 static struct dce_aux *dce120_aux_engine_create(
441 struct dc_context *ctx,
442 uint32_t inst)
443 {
444 struct aux_engine_dce110 *aux_engine =
445 kzalloc_obj(struct aux_engine_dce110);
446
447 if (!aux_engine)
448 return NULL;
449
450 dce110_aux_engine_construct(aux_engine, ctx, inst,
451 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
452 &aux_engine_regs[inst],
453 &aux_mask,
454 &aux_shift,
455 ctx->dc->caps.extended_aux_timeout_support);
456
457 return &aux_engine->base;
458 }
459 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
460
461 static const struct dce_i2c_registers i2c_hw_regs[] = {
462 i2c_inst_regs(1),
463 i2c_inst_regs(2),
464 i2c_inst_regs(3),
465 i2c_inst_regs(4),
466 i2c_inst_regs(5),
467 i2c_inst_regs(6),
468 };
469
470 static const struct dce_i2c_shift i2c_shifts = {
471 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
472 };
473
474 static const struct dce_i2c_mask i2c_masks = {
475 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
476 };
477
dce120_i2c_hw_create(struct dc_context * ctx,uint32_t inst)478 static struct dce_i2c_hw *dce120_i2c_hw_create(
479 struct dc_context *ctx,
480 uint32_t inst)
481 {
482 struct dce_i2c_hw *dce_i2c_hw =
483 kzalloc_obj(struct dce_i2c_hw);
484
485 if (!dce_i2c_hw)
486 return NULL;
487
488 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
489 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
490
491 return dce_i2c_hw;
492 }
493 static const struct bios_registers bios_regs = {
494 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX),
495 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
496 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
497 };
498
499 static const struct resource_caps res_cap = {
500 .num_timing_generator = 6,
501 .num_audio = 7,
502 .num_stream_encoder = 6,
503 .num_pll = 6,
504 .num_ddc = 6,
505 };
506
507 static const struct dc_plane_cap plane_cap = {
508 .type = DC_PLANE_TYPE_DCE_RGB,
509
510 .pixel_format_support = {
511 .argb8888 = true,
512 .nv12 = false,
513 .fp16 = true
514 },
515
516 .max_upscale_factor = {
517 .argb8888 = 16000,
518 .nv12 = 1,
519 .fp16 = 1
520 },
521
522 .max_downscale_factor = {
523 .argb8888 = 250,
524 .nv12 = 1,
525 .fp16 = 1
526 }
527 };
528
529 static const struct dc_debug_options debug_defaults = {
530 .disable_clock_gate = true,
531 };
532
533 static const struct dc_check_config config_defaults = {
534 .enable_legacy_fast_update = true,
535 };
536
dce120_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)537 static struct clock_source *dce120_clock_source_create(
538 struct dc_context *ctx,
539 struct dc_bios *bios,
540 enum clock_source_id id,
541 const struct dce110_clk_src_regs *regs,
542 bool dp_clk_src)
543 {
544 struct dce110_clk_src *clk_src = kzalloc_obj(*clk_src);
545
546 if (!clk_src)
547 return NULL;
548
549 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
550 regs, &cs_shift, &cs_mask)) {
551 clk_src->base.dp_clk_src = dp_clk_src;
552 return &clk_src->base;
553 }
554
555 kfree(clk_src);
556 BREAK_TO_DEBUGGER();
557 return NULL;
558 }
559
dce120_clock_source_destroy(struct clock_source ** clk_src)560 static void dce120_clock_source_destroy(struct clock_source **clk_src)
561 {
562 kfree(TO_DCE110_CLK_SRC(*clk_src));
563 *clk_src = NULL;
564 }
565
566
dce120_hw_sequencer_create(struct dc * dc)567 static bool dce120_hw_sequencer_create(struct dc *dc)
568 {
569 /* All registers used by dce11.2 match those in dce11 in offset and
570 * structure
571 */
572 dce120_hw_sequencer_construct(dc);
573
574 /*TODO Move to separate file and Override what is needed */
575
576 return true;
577 }
578
dce120_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)579 static struct timing_generator *dce120_timing_generator_create(
580 struct dc_context *ctx,
581 uint32_t instance,
582 const struct dce110_timing_generator_offsets *offsets)
583 {
584 struct dce110_timing_generator *tg110 =
585 kzalloc_obj(struct dce110_timing_generator);
586
587 if (!tg110)
588 return NULL;
589
590 dce120_timing_generator_construct(tg110, ctx, instance, offsets);
591 return &tg110->base;
592 }
593
dce120_transform_destroy(struct transform ** xfm)594 static void dce120_transform_destroy(struct transform **xfm)
595 {
596 kfree(TO_DCE_TRANSFORM(*xfm));
597 *xfm = NULL;
598 }
599
dce120_resource_destruct(struct dce110_resource_pool * pool)600 static void dce120_resource_destruct(struct dce110_resource_pool *pool)
601 {
602 unsigned int i;
603
604 for (i = 0; i < pool->base.pipe_count; i++) {
605 if (pool->base.opps[i] != NULL)
606 dce110_opp_destroy(&pool->base.opps[i]);
607
608 if (pool->base.transforms[i] != NULL)
609 dce120_transform_destroy(&pool->base.transforms[i]);
610
611 if (pool->base.ipps[i] != NULL)
612 dce_ipp_destroy(&pool->base.ipps[i]);
613
614 if (pool->base.mis[i] != NULL) {
615 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
616 pool->base.mis[i] = NULL;
617 }
618
619 if (pool->base.irqs != NULL) {
620 dal_irq_service_destroy(&pool->base.irqs);
621 }
622
623 if (pool->base.timing_generators[i] != NULL) {
624 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
625 pool->base.timing_generators[i] = NULL;
626 }
627 }
628
629 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
630 if (pool->base.engines[i] != NULL)
631 dce110_engine_destroy(&pool->base.engines[i]);
632 if (pool->base.hw_i2cs[i] != NULL) {
633 kfree(pool->base.hw_i2cs[i]);
634 pool->base.hw_i2cs[i] = NULL;
635 }
636 if (pool->base.sw_i2cs[i] != NULL) {
637 kfree(pool->base.sw_i2cs[i]);
638 pool->base.sw_i2cs[i] = NULL;
639 }
640 }
641
642 for (i = 0; i < pool->base.audio_count; i++) {
643 if (pool->base.audios[i])
644 dce_aud_destroy(&pool->base.audios[i]);
645 }
646
647 for (i = 0; i < pool->base.stream_enc_count; i++) {
648 if (pool->base.stream_enc[i] != NULL)
649 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
650 }
651
652 for (i = 0; i < pool->base.clk_src_count; i++) {
653 if (pool->base.clock_sources[i] != NULL)
654 dce120_clock_source_destroy(
655 &pool->base.clock_sources[i]);
656 }
657
658 if (pool->base.dp_clock_source != NULL)
659 dce120_clock_source_destroy(&pool->base.dp_clock_source);
660
661 if (pool->base.abm != NULL)
662 dce_abm_destroy(&pool->base.abm);
663
664 if (pool->base.dmcu != NULL)
665 dce_dmcu_destroy(&pool->base.dmcu);
666
667 if (pool->base.oem_device != NULL) {
668 struct dc *dc = pool->base.oem_device->ctx->dc;
669
670 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
671 }
672 }
673
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)674 static void read_dce_straps(
675 struct dc_context *ctx,
676 struct resource_straps *straps)
677 {
678 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
679
680 straps->audio_stream_number = get_reg_field_value(reg_val,
681 CC_DC_MISC_STRAPS,
682 AUDIO_STREAM_NUMBER);
683 straps->hdmi_disable = get_reg_field_value(reg_val,
684 CC_DC_MISC_STRAPS,
685 HDMI_DISABLE);
686
687 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
688 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
689 DC_PINSTRAPS,
690 DC_PINSTRAPS_AUDIO);
691 }
692
create_audio(struct dc_context * ctx,unsigned int inst)693 static struct audio *create_audio(
694 struct dc_context *ctx, unsigned int inst)
695 {
696 return dce_audio_create(ctx, inst,
697 &audio_regs[inst], &audio_shift, &audio_mask);
698 }
699
700 static const struct encoder_feature_support link_enc_feature = {
701 .max_hdmi_deep_color = COLOR_DEPTH_121212,
702 .max_hdmi_pixel_clock = 600000,
703 .hdmi_ycbcr420_supported = true,
704 .dp_ycbcr420_supported = false,
705 .flags.bits.IS_HBR2_CAPABLE = true,
706 .flags.bits.IS_HBR3_CAPABLE = true,
707 .flags.bits.IS_TPS3_CAPABLE = true,
708 .flags.bits.IS_TPS4_CAPABLE = true,
709 };
710
dce120_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)711 static struct link_encoder *dce120_link_encoder_create(
712 struct dc_context *ctx,
713 const struct encoder_init_data *enc_init_data)
714 {
715 struct dce110_link_encoder *enc110 =
716 kzalloc_obj(struct dce110_link_encoder);
717 int link_regs_id;
718
719 if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
720 return NULL;
721
722 link_regs_id =
723 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
724
725 dce110_link_encoder_construct(enc110,
726 enc_init_data,
727 &link_enc_feature,
728 &link_enc_regs[link_regs_id],
729 &link_enc_aux_regs[enc_init_data->channel - 1],
730 &link_enc_hpd_regs[enc_init_data->hpd_source]);
731
732 return &enc110->base;
733 }
734
dce120_panel_cntl_create(const struct panel_cntl_init_data * init_data)735 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
736 {
737 struct dce_panel_cntl *panel_cntl =
738 kzalloc_obj(struct dce_panel_cntl);
739
740 if (!panel_cntl)
741 return NULL;
742
743 dce_panel_cntl_construct(panel_cntl,
744 init_data,
745 &panel_cntl_regs[init_data->inst],
746 &panel_cntl_shift,
747 &panel_cntl_mask);
748
749 return &panel_cntl->base;
750 }
751
dce120_ipp_create(struct dc_context * ctx,uint32_t inst)752 static struct input_pixel_processor *dce120_ipp_create(
753 struct dc_context *ctx, uint32_t inst)
754 {
755 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
756
757 if (!ipp) {
758 BREAK_TO_DEBUGGER();
759 return NULL;
760 }
761
762 dce_ipp_construct(ipp, ctx, inst,
763 &ipp_regs[inst], &ipp_shift, &ipp_mask);
764 return &ipp->base;
765 }
766
dce120_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)767 static struct stream_encoder *dce120_stream_encoder_create(
768 enum engine_id eng_id,
769 struct dc_context *ctx)
770 {
771 struct dce110_stream_encoder *enc110 =
772 kzalloc_obj(struct dce110_stream_encoder);
773
774 if (!enc110)
775 return NULL;
776
777 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
778 &stream_enc_regs[eng_id],
779 &se_shift, &se_mask);
780 return &enc110->base;
781 }
782
783 #define SRII(reg_name, block, id)\
784 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
785 mm ## block ## id ## _ ## reg_name
786
787 static const struct dce_hwseq_registers hwseq_reg = {
788 HWSEQ_DCE120_REG_LIST()
789 };
790
791 static const struct dce_hwseq_shift hwseq_shift = {
792 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
793 };
794
795 static const struct dce_hwseq_mask hwseq_mask = {
796 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
797 };
798
799 /* HWSEQ regs for VG20 */
800 static const struct dce_hwseq_registers dce121_hwseq_reg = {
801 HWSEQ_VG20_REG_LIST()
802 };
803
804 static const struct dce_hwseq_shift dce121_hwseq_shift = {
805 HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
806 };
807
808 static const struct dce_hwseq_mask dce121_hwseq_mask = {
809 HWSEQ_VG20_MASK_SH_LIST(_MASK)
810 };
811
dce120_hwseq_create(struct dc_context * ctx)812 static struct dce_hwseq *dce120_hwseq_create(
813 struct dc_context *ctx)
814 {
815 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
816
817 if (hws) {
818 hws->ctx = ctx;
819 hws->regs = &hwseq_reg;
820 hws->shifts = &hwseq_shift;
821 hws->masks = &hwseq_mask;
822 }
823 return hws;
824 }
825
dce121_hwseq_create(struct dc_context * ctx)826 static struct dce_hwseq *dce121_hwseq_create(
827 struct dc_context *ctx)
828 {
829 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
830
831 if (hws) {
832 hws->ctx = ctx;
833 hws->regs = &dce121_hwseq_reg;
834 hws->shifts = &dce121_hwseq_shift;
835 hws->masks = &dce121_hwseq_mask;
836 }
837 return hws;
838 }
839
840 static const struct resource_create_funcs res_create_funcs = {
841 .read_dce_straps = read_dce_straps,
842 .create_audio = create_audio,
843 .create_stream_encoder = dce120_stream_encoder_create,
844 .create_hwseq = dce120_hwseq_create,
845 };
846
847 static const struct resource_create_funcs dce121_res_create_funcs = {
848 .read_dce_straps = read_dce_straps,
849 .create_audio = create_audio,
850 .create_stream_encoder = dce120_stream_encoder_create,
851 .create_hwseq = dce121_hwseq_create,
852 };
853
854
855 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
856 static const struct dce_mem_input_registers mi_regs[] = {
857 mi_inst_regs(0),
858 mi_inst_regs(1),
859 mi_inst_regs(2),
860 mi_inst_regs(3),
861 mi_inst_regs(4),
862 mi_inst_regs(5),
863 };
864
865 static const struct dce_mem_input_shift mi_shifts = {
866 MI_DCE12_MASK_SH_LIST(__SHIFT)
867 };
868
869 static const struct dce_mem_input_mask mi_masks = {
870 MI_DCE12_MASK_SH_LIST(_MASK)
871 };
872
dce120_mem_input_create(struct dc_context * ctx,uint32_t inst)873 static struct mem_input *dce120_mem_input_create(
874 struct dc_context *ctx,
875 uint32_t inst)
876 {
877 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
878
879 if (!dce_mi) {
880 BREAK_TO_DEBUGGER();
881 return NULL;
882 }
883
884 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
885 return &dce_mi->base;
886 }
887
dce120_transform_create(struct dc_context * ctx,uint32_t inst)888 static struct transform *dce120_transform_create(
889 struct dc_context *ctx,
890 uint32_t inst)
891 {
892 struct dce_transform *transform =
893 kzalloc_obj(struct dce_transform);
894
895 if (!transform)
896 return NULL;
897
898 dce_transform_construct(transform, ctx, inst,
899 &xfm_regs[inst], &xfm_shift, &xfm_mask);
900 transform->lb_memory_size = 0x1404; /*5124*/
901 return &transform->base;
902 }
903
dce120_destroy_resource_pool(struct resource_pool ** pool)904 static void dce120_destroy_resource_pool(struct resource_pool **pool)
905 {
906 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
907
908 dce120_resource_destruct(dce110_pool);
909 kfree(dce110_pool);
910 *pool = NULL;
911 }
912
913 static const struct resource_funcs dce120_res_pool_funcs = {
914 .destroy = dce120_destroy_resource_pool,
915 .link_enc_create = dce120_link_encoder_create,
916 .panel_cntl_create = dce120_panel_cntl_create,
917 .validate_bandwidth = dce112_validate_bandwidth,
918 .validate_plane = dce100_validate_plane,
919 .add_stream_to_ctx = dce112_add_stream_to_ctx,
920 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
921 };
922
bw_calcs_data_update_from_pplib(struct dc * dc)923 static void bw_calcs_data_update_from_pplib(struct dc *dc)
924 {
925 struct dm_pp_clock_levels_with_latency eng_clks = {0};
926 struct dm_pp_clock_levels_with_latency mem_clks = {0};
927 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
928 int i;
929 unsigned int clk;
930 unsigned int latency;
931 /*original logic in dal3*/
932 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
933
934 /*do system clock*/
935 if (!dm_pp_get_clock_levels_by_type_with_latency(
936 dc->ctx,
937 DM_PP_CLOCK_TYPE_ENGINE_CLK,
938 &eng_clks) || eng_clks.num_levels == 0) {
939
940 eng_clks.num_levels = 8;
941 clk = 300000;
942
943 for (i = 0; i < eng_clks.num_levels; i++) {
944 eng_clks.data[i].clocks_in_khz = clk;
945 clk += 100000;
946 }
947 }
948
949 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
950 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
951 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
952 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
953 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
954 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
955 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
956 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
957 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
958 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
959 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
960 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
961 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
962 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
963 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
964 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
965 eng_clks.data[0].clocks_in_khz, 1000);
966
967 /*do memory clock*/
968 if (!dm_pp_get_clock_levels_by_type_with_latency(
969 dc->ctx,
970 DM_PP_CLOCK_TYPE_MEMORY_CLK,
971 &mem_clks) || mem_clks.num_levels == 0) {
972
973 mem_clks.num_levels = 3;
974 clk = 250000;
975 latency = 45;
976
977 for (i = 0; i < eng_clks.num_levels; i++) {
978 mem_clks.data[i].clocks_in_khz = clk;
979 mem_clks.data[i].latency_in_us = latency;
980 clk += 500000;
981 latency -= 5;
982 }
983
984 }
985
986 /* we don't need to call PPLIB for validation clock since they
987 * also give us the highest sclk and highest mclk (UMA clock).
988 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
989 * YCLK = UMACLK*m_memoryTypeMultiplier
990 */
991 if (dc->bw_vbios->memory_type == bw_def_hbm)
992 memory_type_multiplier = MEMORY_TYPE_HBM;
993
994 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
995 (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
996 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
997 (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
998 1000);
999 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1000 (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1001 1000);
1002
1003 /* Now notify PPLib/SMU about which Watermarks sets they should select
1004 * depending on DPM state they are in. And update BW MGR GFX Engine and
1005 * Memory clock member variables for Watermarks calculations for each
1006 * Watermark Set
1007 */
1008 clk_ranges.num_wm_sets = 4;
1009 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1010 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1011 eng_clks.data[0].clocks_in_khz;
1012 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1013 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1014 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1015 mem_clks.data[0].clocks_in_khz;
1016 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1017 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1018
1019 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1020 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1021 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1022 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1023 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1024 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1025 mem_clks.data[0].clocks_in_khz;
1026 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1027 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1028
1029 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1030 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1031 eng_clks.data[0].clocks_in_khz;
1032 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1033 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1034 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1035 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1036 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1037 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1038
1039 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1040 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1041 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1042 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1043 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1044 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1045 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1046 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1047 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1048
1049 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1050 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1051 }
1052
read_pipe_fuses(struct dc_context * ctx)1053 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1054 {
1055 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1056 /* VG20 support max 6 pipes */
1057 value = value & 0x3f;
1058 return value;
1059 }
1060
dce120_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1061 static bool dce120_resource_construct(
1062 uint8_t num_virtual_links,
1063 struct dc *dc,
1064 struct dce110_resource_pool *pool)
1065 {
1066 struct ddc_service_init_data ddc_init_data = {0};
1067 unsigned int i;
1068 int j;
1069 struct dc_context *ctx = dc->ctx;
1070 struct irq_service_init_data irq_init_data;
1071 static const struct resource_create_funcs *res_funcs;
1072 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1073 uint32_t pipe_fuses = 0;
1074
1075 ctx->dc_bios->regs = &bios_regs;
1076
1077 pool->base.res_cap = &res_cap;
1078 pool->base.funcs = &dce120_res_pool_funcs;
1079
1080 /* TODO: Fill more data from GreenlandAsicCapability.cpp */
1081 pool->base.pipe_count = res_cap.num_timing_generator;
1082 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1083 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1084
1085 dc->caps.max_downscale_ratio = 200;
1086 dc->caps.i2c_speed_in_khz = 100;
1087 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1088 dc->caps.max_cursor_size = 128;
1089 dc->caps.min_horizontal_blanking_period = 80;
1090 dc->caps.dual_link_dvi = true;
1091 dc->caps.psp_setup_panel_mode = true;
1092 dc->caps.extended_aux_timeout_support = false;
1093 dc->debug = debug_defaults;
1094 dc->check_config = config_defaults;
1095
1096 /*************************************************
1097 * Create resources *
1098 *************************************************/
1099
1100 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1101 dce120_clock_source_create(ctx, ctx->dc_bios,
1102 CLOCK_SOURCE_COMBO_PHY_PLL0,
1103 &clk_src_regs[0], false);
1104 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1105 dce120_clock_source_create(ctx, ctx->dc_bios,
1106 CLOCK_SOURCE_COMBO_PHY_PLL1,
1107 &clk_src_regs[1], false);
1108 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1109 dce120_clock_source_create(ctx, ctx->dc_bios,
1110 CLOCK_SOURCE_COMBO_PHY_PLL2,
1111 &clk_src_regs[2], false);
1112 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1113 dce120_clock_source_create(ctx, ctx->dc_bios,
1114 CLOCK_SOURCE_COMBO_PHY_PLL3,
1115 &clk_src_regs[3], false);
1116 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1117 dce120_clock_source_create(ctx, ctx->dc_bios,
1118 CLOCK_SOURCE_COMBO_PHY_PLL4,
1119 &clk_src_regs[4], false);
1120 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1121 dce120_clock_source_create(ctx, ctx->dc_bios,
1122 CLOCK_SOURCE_COMBO_PHY_PLL5,
1123 &clk_src_regs[5], false);
1124 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1125
1126 pool->base.dp_clock_source =
1127 dce120_clock_source_create(ctx, ctx->dc_bios,
1128 CLOCK_SOURCE_ID_DP_DTO,
1129 &clk_src_regs[0], true);
1130
1131 for (i = 0; i < pool->base.clk_src_count; i++) {
1132 if (pool->base.clock_sources[i] == NULL) {
1133 dm_error("DC: failed to create clock sources!\n");
1134 BREAK_TO_DEBUGGER();
1135 goto clk_src_create_fail;
1136 }
1137 }
1138
1139 pool->base.dmcu = dce_dmcu_create(ctx,
1140 &dmcu_regs,
1141 &dmcu_shift,
1142 &dmcu_mask);
1143 if (pool->base.dmcu == NULL) {
1144 dm_error("DC: failed to create dmcu!\n");
1145 BREAK_TO_DEBUGGER();
1146 goto res_create_fail;
1147 }
1148
1149 pool->base.abm = dce_abm_create(ctx,
1150 &abm_regs,
1151 &abm_shift,
1152 &abm_mask);
1153 if (pool->base.abm == NULL) {
1154 dm_error("DC: failed to create abm!\n");
1155 BREAK_TO_DEBUGGER();
1156 goto res_create_fail;
1157 }
1158
1159
1160 irq_init_data.ctx = dc->ctx;
1161 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1162 if (!pool->base.irqs)
1163 goto irqs_create_fail;
1164
1165 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1166 if (is_vg20)
1167 pipe_fuses = read_pipe_fuses(ctx);
1168
1169 /* index to valid pipe resource */
1170 j = 0;
1171 for (i = 0; i < pool->base.pipe_count; i++) {
1172 if (is_vg20) {
1173 if ((pipe_fuses & (1 << i)) != 0) {
1174 dm_error("DC: skip invalid pipe %d!\n", i);
1175 continue;
1176 }
1177 }
1178
1179 pool->base.timing_generators[j] =
1180 dce120_timing_generator_create(
1181 ctx,
1182 i,
1183 &dce120_tg_offsets[i]);
1184 if (pool->base.timing_generators[j] == NULL) {
1185 BREAK_TO_DEBUGGER();
1186 dm_error("DC: failed to create tg!\n");
1187 goto controller_create_fail;
1188 }
1189
1190 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1191
1192 if (pool->base.mis[j] == NULL) {
1193 BREAK_TO_DEBUGGER();
1194 dm_error(
1195 "DC: failed to create memory input!\n");
1196 goto controller_create_fail;
1197 }
1198
1199 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1200 if (pool->base.ipps[i] == NULL) {
1201 BREAK_TO_DEBUGGER();
1202 dm_error(
1203 "DC: failed to create input pixel processor!\n");
1204 goto controller_create_fail;
1205 }
1206
1207 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1208 if (pool->base.transforms[i] == NULL) {
1209 BREAK_TO_DEBUGGER();
1210 dm_error(
1211 "DC: failed to create transform!\n");
1212 goto res_create_fail;
1213 }
1214
1215 pool->base.opps[j] = dce120_opp_create(
1216 ctx,
1217 i);
1218 if (pool->base.opps[j] == NULL) {
1219 BREAK_TO_DEBUGGER();
1220 dm_error(
1221 "DC: failed to create output pixel processor!\n");
1222 }
1223
1224 /* check next valid pipe */
1225 j++;
1226 }
1227
1228 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1229 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1230 if (pool->base.engines[i] == NULL) {
1231 BREAK_TO_DEBUGGER();
1232 dm_error(
1233 "DC:failed to create aux engine!!\n");
1234 goto res_create_fail;
1235 }
1236 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1237 if (pool->base.hw_i2cs[i] == NULL) {
1238 BREAK_TO_DEBUGGER();
1239 dm_error(
1240 "DC:failed to create i2c engine!!\n");
1241 goto res_create_fail;
1242 }
1243 pool->base.sw_i2cs[i] = NULL;
1244 }
1245
1246 /* valid pipe num */
1247 pool->base.pipe_count = j;
1248 pool->base.timing_generator_count = j;
1249
1250 if (is_vg20)
1251 res_funcs = &dce121_res_create_funcs;
1252 else
1253 res_funcs = &res_create_funcs;
1254
1255 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1256 goto res_create_fail;
1257
1258 /* Create hardware sequencer */
1259 if (!dce120_hw_sequencer_create(dc))
1260 goto controller_create_fail;
1261
1262 dc->caps.max_planes = pool->base.pipe_count;
1263
1264 for (i = 0; i < dc->caps.max_planes; ++i)
1265 dc->caps.planes[i] = plane_cap;
1266
1267 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1268
1269 bw_calcs_data_update_from_pplib(dc);
1270
1271 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1272 ddc_init_data.ctx = dc->ctx;
1273 ddc_init_data.link = NULL;
1274 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1275 ddc_init_data.id.enum_id = 0;
1276 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1277 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1278 }
1279
1280 return true;
1281
1282 irqs_create_fail:
1283 controller_create_fail:
1284 clk_src_create_fail:
1285 res_create_fail:
1286
1287 dce120_resource_destruct(pool);
1288
1289 return false;
1290 }
1291
dce120_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1292 struct resource_pool *dce120_create_resource_pool(
1293 uint8_t num_virtual_links,
1294 struct dc *dc)
1295 {
1296 struct dce110_resource_pool *pool =
1297 kzalloc_obj(struct dce110_resource_pool);
1298
1299 if (!pool)
1300 return NULL;
1301
1302 if (dce120_resource_construct(num_virtual_links, dc, pool))
1303 return &pool->base;
1304
1305 kfree(pool);
1306 BREAK_TO_DEBUGGER();
1307 return NULL;
1308 }
1309