1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel Dollar Cove TI PMIC GPADC Driver
4 *
5 * Copyright (C) 2014 Intel Corporation (Ramakrishna Pallala <ramakrishna.pallala@intel.com>)
6 * Copyright (C) 2024 - 2025 Hans de Goede <hansg@kernel.org>
7 */
8
9 #include <linux/bits.h>
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/cleanup.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/mfd/intel_soc_pmic.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/wait.h>
22
23 #include <linux/iio/driver.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/machine.h>
26
27 #define DC_TI_ADC_CNTL_REG 0x50
28 #define DC_TI_ADC_START BIT(0)
29 #define DC_TI_ADC_CH_SEL GENMASK(2, 1)
30 #define DC_TI_ADC_EN BIT(5)
31 #define DC_TI_ADC_EN_EXT_BPTH_BIAS BIT(6)
32
33 #define DC_TI_VBAT_ZSE_GE_REG 0x53
34 #define DC_TI_VBAT_GE GENMASK(3, 0)
35 #define DC_TI_VBAT_ZSE GENMASK(7, 4)
36
37 /* VBAT GE gain correction is in 0.0015 increments, ZSE is in 1.0 increments */
38 #define DC_TI_VBAT_GE_STEP 15
39 #define DC_TI_VBAT_GE_DIV 10000
40
41 #define DC_TI_ADC_DATA_REG_CH(x) (0x54 + 2 * (x))
42
43 enum dc_ti_adc_id {
44 DC_TI_ADC_VBAT,
45 DC_TI_ADC_PMICTEMP,
46 DC_TI_ADC_BATTEMP,
47 DC_TI_ADC_SYSTEMP0,
48 };
49
50 struct dc_ti_adc_info {
51 struct mutex lock; /* Protects against concurrent accesses to the ADC */
52 wait_queue_head_t wait;
53 struct device *dev;
54 struct regmap *regmap;
55 int vbat_zse;
56 int vbat_ge;
57 bool conversion_done;
58 };
59
60 static const struct iio_chan_spec dc_ti_adc_channels[] = {
61 {
62 .indexed = 1,
63 .type = IIO_VOLTAGE,
64 .channel = DC_TI_ADC_VBAT,
65 .address = DC_TI_ADC_DATA_REG_CH(0),
66 .datasheet_name = "CH0",
67 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
68 BIT(IIO_CHAN_INFO_SCALE) |
69 BIT(IIO_CHAN_INFO_PROCESSED),
70 }, {
71 .indexed = 1,
72 .type = IIO_TEMP,
73 .channel = DC_TI_ADC_PMICTEMP,
74 .address = DC_TI_ADC_DATA_REG_CH(1),
75 .datasheet_name = "CH1",
76 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
77 }, {
78 .indexed = 1,
79 .type = IIO_TEMP,
80 .channel = DC_TI_ADC_BATTEMP,
81 .address = DC_TI_ADC_DATA_REG_CH(2),
82 .datasheet_name = "CH2",
83 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
84 }, {
85 .indexed = 1,
86 .type = IIO_TEMP,
87 .channel = DC_TI_ADC_SYSTEMP0,
88 .address = DC_TI_ADC_DATA_REG_CH(3),
89 .datasheet_name = "CH3",
90 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
91 }
92 };
93
94 static struct iio_map dc_ti_adc_default_maps[] = {
95 IIO_MAP("CH0", "chtdc_ti_battery", "VBAT"),
96 IIO_MAP("CH1", "chtdc_ti_battery", "PMICTEMP"),
97 IIO_MAP("CH2", "chtdc_ti_battery", "BATTEMP"),
98 IIO_MAP("CH3", "chtdc_ti_battery", "SYSTEMP0"),
99 { }
100 };
101
dc_ti_adc_isr(int irq,void * data)102 static irqreturn_t dc_ti_adc_isr(int irq, void *data)
103 {
104 struct dc_ti_adc_info *info = data;
105
106 info->conversion_done = true;
107 wake_up(&info->wait);
108 return IRQ_HANDLED;
109 }
110
dc_ti_adc_scale(struct dc_ti_adc_info * info,struct iio_chan_spec const * chan,int * val,int * val2)111 static int dc_ti_adc_scale(struct dc_ti_adc_info *info,
112 struct iio_chan_spec const *chan,
113 int *val, int *val2)
114 {
115 if (chan->channel != DC_TI_ADC_VBAT)
116 return -EINVAL;
117
118 /* Vbat ADC scale is 4.6875 mV / unit */
119 *val = 4;
120 *val2 = 687500;
121
122 return IIO_VAL_INT_PLUS_MICRO;
123 }
124
dc_ti_adc_raw_to_processed(struct dc_ti_adc_info * info,struct iio_chan_spec const * chan,int raw,int * val,int * val2)125 static int dc_ti_adc_raw_to_processed(struct dc_ti_adc_info *info,
126 struct iio_chan_spec const *chan,
127 int raw, int *val, int *val2)
128 {
129 if (chan->channel != DC_TI_ADC_VBAT)
130 return -EINVAL;
131
132 /* Apply calibration */
133 raw -= info->vbat_zse;
134 raw = raw * (DC_TI_VBAT_GE_DIV - info->vbat_ge * DC_TI_VBAT_GE_STEP) /
135 DC_TI_VBAT_GE_DIV;
136 /* Vbat ADC scale is 4.6875 mV / unit */
137 raw *= 46875;
138
139 /* raw is now in 10000 units / mV, convert to milli + milli/1e6 */
140 *val = raw / 10000;
141 *val2 = (raw % 10000) * 100;
142
143 return IIO_VAL_INT_PLUS_MICRO;
144 }
145
dc_ti_adc_sample(struct dc_ti_adc_info * info,struct iio_chan_spec const * chan,int * val)146 static int dc_ti_adc_sample(struct dc_ti_adc_info *info,
147 struct iio_chan_spec const *chan, int *val)
148 {
149 int ret, ch = chan->channel;
150 __be16 buf;
151
152 info->conversion_done = false;
153
154 /*
155 * As per TI (PMIC Vendor), the ADC enable and ADC start commands should
156 * not be sent together. Hence send the commands separately.
157 */
158 ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG, DC_TI_ADC_EN);
159 if (ret)
160 return ret;
161
162 ret = regmap_update_bits(info->regmap, DC_TI_ADC_CNTL_REG,
163 DC_TI_ADC_CH_SEL,
164 FIELD_PREP(DC_TI_ADC_CH_SEL, ch));
165 if (ret)
166 return ret;
167
168 /*
169 * As per PMIC Vendor, a minimum of 50 ųs delay is required between ADC
170 * Enable and ADC START commands. This is also recommended by Intel
171 * Hardware team after the timing analysis of GPADC signals. Since the
172 * I2C Write transaction to set the channel number also imparts 25 ųs
173 * delay, we need to wait for another 25 ųs before issuing ADC START.
174 */
175 fsleep(25);
176
177 ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG,
178 DC_TI_ADC_START);
179 if (ret)
180 return ret;
181
182 /* TI (PMIC Vendor) recommends 5 s timeout for conversion */
183 ret = wait_event_timeout(info->wait, info->conversion_done, 5 * HZ);
184 if (ret == 0) {
185 ret = -ETIMEDOUT;
186 goto disable_adc;
187 }
188
189 ret = regmap_bulk_read(info->regmap, chan->address, &buf, sizeof(buf));
190 if (ret)
191 goto disable_adc;
192
193 /* The ADC values are 10 bits wide */
194 *val = be16_to_cpu(buf) & GENMASK(9, 0);
195
196 disable_adc:
197 regmap_clear_bits(info->regmap, DC_TI_ADC_CNTL_REG,
198 DC_TI_ADC_START | DC_TI_ADC_EN);
199 return ret;
200 }
201
dc_ti_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)202 static int dc_ti_adc_read_raw(struct iio_dev *indio_dev,
203 struct iio_chan_spec const *chan,
204 int *val, int *val2, long mask)
205 {
206 struct dc_ti_adc_info *info = iio_priv(indio_dev);
207 int ret;
208
209 if (mask == IIO_CHAN_INFO_SCALE)
210 return dc_ti_adc_scale(info, chan, val, val2);
211
212 guard(mutex)(&info->lock);
213
214 /*
215 * If channel BPTHERM has been selected, first enable the BPTHERM BIAS
216 * which provides the VREF Voltage reference to convert BPTHERM Input
217 * voltage to temperature.
218 */
219 if (chan->channel == DC_TI_ADC_BATTEMP) {
220 ret = regmap_set_bits(info->regmap, DC_TI_ADC_CNTL_REG,
221 DC_TI_ADC_EN_EXT_BPTH_BIAS);
222 if (ret)
223 return ret;
224 /*
225 * As per PMIC Vendor specifications, BPTHERM BIAS should be
226 * enabled 35 ms before ADC_EN command.
227 */
228 msleep(35);
229 }
230
231 ret = dc_ti_adc_sample(info, chan, val);
232
233 if (chan->channel == DC_TI_ADC_BATTEMP)
234 regmap_clear_bits(info->regmap, DC_TI_ADC_CNTL_REG,
235 DC_TI_ADC_EN_EXT_BPTH_BIAS);
236
237 if (ret)
238 return ret;
239
240 switch (mask) {
241 case IIO_CHAN_INFO_RAW:
242 return IIO_VAL_INT;
243 case IIO_CHAN_INFO_PROCESSED:
244 return dc_ti_adc_raw_to_processed(info, chan, *val, val, val2);
245 }
246
247 return -EINVAL;
248 }
249
250 static const struct iio_info dc_ti_adc_iio_info = {
251 .read_raw = dc_ti_adc_read_raw,
252 };
253
dc_ti_adc_probe(struct platform_device * pdev)254 static int dc_ti_adc_probe(struct platform_device *pdev)
255 {
256 struct device *dev = &pdev->dev;
257 struct intel_soc_pmic *pmic = dev_get_drvdata(dev->parent);
258 struct dc_ti_adc_info *info;
259 struct iio_dev *indio_dev;
260 unsigned int val;
261 int irq, ret;
262
263 irq = platform_get_irq(pdev, 0);
264 if (irq < 0)
265 return irq;
266
267 indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
268 if (!indio_dev)
269 return -ENOMEM;
270
271 info = iio_priv(indio_dev);
272
273 ret = devm_mutex_init(dev, &info->lock);
274 if (ret)
275 return ret;
276
277 init_waitqueue_head(&info->wait);
278
279 info->dev = dev;
280 info->regmap = pmic->regmap;
281
282 indio_dev->name = "dc_ti_adc";
283 indio_dev->channels = dc_ti_adc_channels;
284 indio_dev->num_channels = ARRAY_SIZE(dc_ti_adc_channels);
285 indio_dev->info = &dc_ti_adc_iio_info;
286 indio_dev->modes = INDIO_DIRECT_MODE;
287
288 ret = regmap_read(info->regmap, DC_TI_VBAT_ZSE_GE_REG, &val);
289 if (ret)
290 return ret;
291
292 info->vbat_zse = FIELD_GET_SIGNED(DC_TI_VBAT_ZSE, val);
293 info->vbat_ge = FIELD_GET_SIGNED(DC_TI_VBAT_GE, val);
294
295 dev_dbg(dev, "vbat-zse %d vbat-ge %d\n", info->vbat_zse, info->vbat_ge);
296
297 ret = devm_iio_map_array_register(dev, indio_dev, dc_ti_adc_default_maps);
298 if (ret)
299 return ret;
300
301 ret = devm_request_threaded_irq(dev, irq, NULL, dc_ti_adc_isr,
302 IRQF_ONESHOT, indio_dev->name, info);
303 if (ret)
304 return ret;
305
306 return devm_iio_device_register(dev, indio_dev);
307 }
308
309 static const struct platform_device_id dc_ti_adc_ids[] = {
310 { .name = "chtdc_ti_adc" },
311 { }
312 };
313 MODULE_DEVICE_TABLE(platform, dc_ti_adc_ids);
314
315 static struct platform_driver dc_ti_adc_driver = {
316 .driver = {
317 .name = "dc_ti_adc",
318 },
319 .probe = dc_ti_adc_probe,
320 .id_table = dc_ti_adc_ids,
321 };
322 module_platform_driver(dc_ti_adc_driver);
323
324 MODULE_AUTHOR("Ramakrishna Pallala (Intel)");
325 MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>");
326 MODULE_DESCRIPTION("Intel Dollar Cove (TI) GPADC Driver");
327 MODULE_LICENSE("GPL");
328