1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2024 NXP
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/jiffies.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/units.h>
16
17 #include <drm/drm_modes.h>
18
19 #include "dc-de.h"
20 #include "dc-drv.h"
21
22 #define FGSTCTRL 0x8
23 #define FGSYNCMODE_MASK GENMASK(2, 1)
24 #define FGSYNCMODE(x) FIELD_PREP(FGSYNCMODE_MASK, (x))
25 #define SHDEN BIT(0)
26
27 #define HTCFG1 0xc
28 #define HTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
29 #define HACT(x) FIELD_PREP(GENMASK(13, 0), (x))
30
31 #define HTCFG2 0x10
32 #define HSEN BIT(31)
33 #define HSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
34 #define HSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))
35
36 #define VTCFG1 0x14
37 #define VTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
38 #define VACT(x) FIELD_PREP(GENMASK(13, 0), (x))
39
40 #define VTCFG2 0x18
41 #define VSEN BIT(31)
42 #define VSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
43 #define VSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))
44
45 #define PKICKCONFIG 0x2c
46 #define SKICKCONFIG 0x30
47 #define EN BIT(31)
48 #define ROW(x) FIELD_PREP(GENMASK(29, 16), (x))
49 #define COL(x) FIELD_PREP(GENMASK(13, 0), (x))
50
51 #define PACFG 0x54
52 #define SACFG 0x58
53 #define STARTY(x) FIELD_PREP(GENMASK(29, 16), ((x) + 1))
54 #define STARTX(x) FIELD_PREP(GENMASK(13, 0), ((x) + 1))
55
56 #define FGINCTRL 0x5c
57 #define FGINCTRLPANIC 0x60
58 #define ENSECALPHA BIT(4)
59 #define ENPRIMALPHA BIT(3)
60 #define FGDM_MASK GENMASK(2, 0)
61
62 #define FGCCR 0x64
63 #define CCGREEN(x) FIELD_PREP(GENMASK(19, 10), (x))
64
65 #define FGENABLE 0x68
66 #define FGEN BIT(0)
67
68 #define FGSLR 0x6c
69 #define SHDTOKGEN BIT(0)
70
71 #define FGTIMESTAMP 0x74
72 #define FRAMEINDEX(x) FIELD_GET(GENMASK(31, 14), (x))
73 #define LINEINDEX(x) FIELD_GET(GENMASK(13, 0), (x))
74
75 #define FGCHSTAT 0x78
76 #define SECSYNCSTAT BIT(24)
77 #define SFIFOEMPTY BIT(16)
78
79 #define FGCHSTATCLR 0x7c
80 #define CLRSECSTAT BIT(16)
81
82 enum dc_fg_syncmode {
83 FG_SYNCMODE_OFF, /* No side-by-side synchronization. */
84 };
85
86 enum dc_fg_dm {
87 FG_DM_CONSTCOL = 0x1, /* Constant Color Background is shown. */
88 FG_DM_SEC_ON_TOP = 0x5, /* Both inputs overlaid with secondary on top. */
89 };
90
91 static const struct dc_subdev_info dc_fg_info[] = {
92 { .reg_start = 0x5618b800, .id = 0, },
93 { .reg_start = 0x5618d400, .id = 1, },
94 };
95
96 static const struct regmap_range dc_fg_regmap_write_ranges[] = {
97 regmap_reg_range(FGSTCTRL, VTCFG2),
98 regmap_reg_range(PKICKCONFIG, SKICKCONFIG),
99 regmap_reg_range(PACFG, FGSLR),
100 regmap_reg_range(FGCHSTATCLR, FGCHSTATCLR),
101 };
102
103 static const struct regmap_range dc_fg_regmap_read_ranges[] = {
104 regmap_reg_range(FGSTCTRL, VTCFG2),
105 regmap_reg_range(PKICKCONFIG, SKICKCONFIG),
106 regmap_reg_range(PACFG, FGENABLE),
107 regmap_reg_range(FGTIMESTAMP, FGCHSTAT),
108 };
109
110 static const struct regmap_access_table dc_fg_regmap_write_table = {
111 .yes_ranges = dc_fg_regmap_write_ranges,
112 .n_yes_ranges = ARRAY_SIZE(dc_fg_regmap_write_ranges),
113 };
114
115 static const struct regmap_access_table dc_fg_regmap_read_table = {
116 .yes_ranges = dc_fg_regmap_read_ranges,
117 .n_yes_ranges = ARRAY_SIZE(dc_fg_regmap_read_ranges),
118 };
119
120 static const struct regmap_config dc_fg_regmap_config = {
121 .reg_bits = 32,
122 .reg_stride = 4,
123 .val_bits = 32,
124 .fast_io = true,
125 .wr_table = &dc_fg_regmap_write_table,
126 .rd_table = &dc_fg_regmap_read_table,
127 .max_register = FGCHSTATCLR,
128 };
129
dc_fg_enable_shden(struct dc_fg * fg)130 static inline void dc_fg_enable_shden(struct dc_fg *fg)
131 {
132 regmap_write_bits(fg->reg, FGSTCTRL, SHDEN, SHDEN);
133 }
134
dc_fg_syncmode(struct dc_fg * fg,enum dc_fg_syncmode mode)135 static inline void dc_fg_syncmode(struct dc_fg *fg, enum dc_fg_syncmode mode)
136 {
137 regmap_write_bits(fg->reg, FGSTCTRL, FGSYNCMODE_MASK, FGSYNCMODE(mode));
138 }
139
dc_fg_cfg_videomode(struct dc_fg * fg,struct drm_display_mode * m)140 void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m)
141 {
142 u32 hact, htotal, hsync, hsbp;
143 u32 vact, vtotal, vsync, vsbp;
144 u32 kick_row, kick_col;
145 int ret;
146
147 hact = m->crtc_hdisplay;
148 htotal = m->crtc_htotal;
149 hsync = m->crtc_hsync_end - m->crtc_hsync_start;
150 hsbp = m->crtc_htotal - m->crtc_hsync_start;
151
152 vact = m->crtc_vdisplay;
153 vtotal = m->crtc_vtotal;
154 vsync = m->crtc_vsync_end - m->crtc_vsync_start;
155 vsbp = m->crtc_vtotal - m->crtc_vsync_start;
156
157 /* video mode */
158 regmap_write(fg->reg, HTCFG1, HACT(hact) | HTOTAL(htotal));
159 regmap_write(fg->reg, HTCFG2, HSYNC(hsync) | HSBP(hsbp) | HSEN);
160 regmap_write(fg->reg, VTCFG1, VACT(vact) | VTOTAL(vtotal));
161 regmap_write(fg->reg, VTCFG2, VSYNC(vsync) | VSBP(vsbp) | VSEN);
162
163 kick_col = hact + 1;
164 kick_row = vact;
165
166 /* pkickconfig */
167 regmap_write(fg->reg, PKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
168
169 /* skikconfig */
170 regmap_write(fg->reg, SKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
171
172 /* primary and secondary area position configuration */
173 regmap_write(fg->reg, PACFG, STARTX(0) | STARTY(0));
174 regmap_write(fg->reg, SACFG, STARTX(0) | STARTY(0));
175
176 /* alpha */
177 regmap_write_bits(fg->reg, FGINCTRL, ENPRIMALPHA | ENSECALPHA, 0);
178 regmap_write_bits(fg->reg, FGINCTRLPANIC, ENPRIMALPHA | ENSECALPHA, 0);
179
180 /* constant color is green(used in panic mode) */
181 regmap_write(fg->reg, FGCCR, CCGREEN(0x3ff));
182
183 ret = clk_set_rate(fg->clk_disp, m->clock * HZ_PER_KHZ);
184 if (ret < 0)
185 dev_err(fg->dev, "failed to set display clock rate: %d\n", ret);
186 }
187
dc_fg_displaymode(struct dc_fg * fg,enum dc_fg_dm mode)188 static inline void dc_fg_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
189 {
190 regmap_write_bits(fg->reg, FGINCTRL, FGDM_MASK, mode);
191 }
192
dc_fg_panic_displaymode(struct dc_fg * fg,enum dc_fg_dm mode)193 static inline void dc_fg_panic_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
194 {
195 regmap_write_bits(fg->reg, FGINCTRLPANIC, FGDM_MASK, mode);
196 }
197
dc_fg_enable(struct dc_fg * fg)198 void dc_fg_enable(struct dc_fg *fg)
199 {
200 regmap_write(fg->reg, FGENABLE, FGEN);
201 }
202
dc_fg_disable(struct dc_fg * fg)203 void dc_fg_disable(struct dc_fg *fg)
204 {
205 regmap_write(fg->reg, FGENABLE, 0);
206 }
207
dc_fg_shdtokgen(struct dc_fg * fg)208 void dc_fg_shdtokgen(struct dc_fg *fg)
209 {
210 regmap_write(fg->reg, FGSLR, SHDTOKGEN);
211 }
212
dc_fg_get_frame_index(struct dc_fg * fg)213 u32 dc_fg_get_frame_index(struct dc_fg *fg)
214 {
215 u32 val;
216
217 regmap_read(fg->reg, FGTIMESTAMP, &val);
218
219 return FRAMEINDEX(val);
220 }
221
dc_fg_get_line_index(struct dc_fg * fg)222 u32 dc_fg_get_line_index(struct dc_fg *fg)
223 {
224 u32 val;
225
226 regmap_read(fg->reg, FGTIMESTAMP, &val);
227
228 return LINEINDEX(val);
229 }
230
dc_fg_wait_for_frame_index_moving(struct dc_fg * fg)231 bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg)
232 {
233 unsigned long timeout = jiffies + msecs_to_jiffies(100);
234 u32 frame_index, last_frame_index;
235
236 frame_index = dc_fg_get_frame_index(fg);
237 do {
238 last_frame_index = frame_index;
239 frame_index = dc_fg_get_frame_index(fg);
240 } while (last_frame_index == frame_index &&
241 time_before(jiffies, timeout));
242
243 return last_frame_index != frame_index;
244 }
245
dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg * fg)246 bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg)
247 {
248 u32 val;
249
250 regmap_read(fg->reg, FGCHSTAT, &val);
251
252 return !!(val & SFIFOEMPTY);
253 }
254
dc_fg_secondary_clear_channel_status(struct dc_fg * fg)255 void dc_fg_secondary_clear_channel_status(struct dc_fg *fg)
256 {
257 regmap_write(fg->reg, FGCHSTATCLR, CLRSECSTAT);
258 }
259
dc_fg_wait_for_secondary_syncup(struct dc_fg * fg)260 int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg)
261 {
262 unsigned int val;
263
264 return regmap_read_poll_timeout(fg->reg, FGCHSTAT, val,
265 val & SECSYNCSTAT, 5, 100000);
266 }
267
dc_fg_enable_clock(struct dc_fg * fg)268 void dc_fg_enable_clock(struct dc_fg *fg)
269 {
270 int ret;
271
272 ret = clk_prepare_enable(fg->clk_disp);
273 if (ret)
274 dev_err(fg->dev, "failed to enable display clock: %d\n", ret);
275 }
276
dc_fg_disable_clock(struct dc_fg * fg)277 void dc_fg_disable_clock(struct dc_fg *fg)
278 {
279 clk_disable_unprepare(fg->clk_disp);
280 }
281
dc_fg_check_clock(struct dc_fg * fg,int clk_khz)282 enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz)
283 {
284 unsigned long rounded_rate;
285
286 rounded_rate = clk_round_rate(fg->clk_disp, clk_khz * HZ_PER_KHZ);
287
288 if (rounded_rate != clk_khz * HZ_PER_KHZ)
289 return MODE_NOCLOCK;
290
291 return MODE_OK;
292 }
293
dc_fg_init(struct dc_fg * fg)294 void dc_fg_init(struct dc_fg *fg)
295 {
296 dc_fg_enable_shden(fg);
297 dc_fg_syncmode(fg, FG_SYNCMODE_OFF);
298 dc_fg_displaymode(fg, FG_DM_SEC_ON_TOP);
299 dc_fg_panic_displaymode(fg, FG_DM_CONSTCOL);
300 }
301
dc_fg_bind(struct device * dev,struct device * master,void * data)302 static int dc_fg_bind(struct device *dev, struct device *master, void *data)
303 {
304 struct platform_device *pdev = to_platform_device(dev);
305 struct dc_drm_device *dc_drm = data;
306 struct resource *res;
307 void __iomem *base;
308 struct dc_fg *fg;
309 int id;
310
311 fg = devm_kzalloc(dev, sizeof(*fg), GFP_KERNEL);
312 if (!fg)
313 return -ENOMEM;
314
315 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
316 if (IS_ERR(base))
317 return PTR_ERR(base);
318
319 fg->reg = devm_regmap_init_mmio(dev, base, &dc_fg_regmap_config);
320 if (IS_ERR(fg->reg))
321 return PTR_ERR(fg->reg);
322
323 fg->clk_disp = devm_clk_get(dev, NULL);
324 if (IS_ERR(fg->clk_disp))
325 return dev_err_probe(dev, PTR_ERR(fg->clk_disp),
326 "failed to get display clock\n");
327
328 id = dc_subdev_get_id(dc_fg_info, ARRAY_SIZE(dc_fg_info), res);
329 if (id < 0) {
330 dev_err(dev, "failed to get instance number: %d\n", id);
331 return id;
332 }
333
334 fg->dev = dev;
335 dc_drm->fg[id] = fg;
336
337 return 0;
338 }
339
340 static const struct component_ops dc_fg_ops = {
341 .bind = dc_fg_bind,
342 };
343
dc_fg_probe(struct platform_device * pdev)344 static int dc_fg_probe(struct platform_device *pdev)
345 {
346 int ret;
347
348 ret = component_add(&pdev->dev, &dc_fg_ops);
349 if (ret)
350 return dev_err_probe(&pdev->dev, ret,
351 "failed to add component\n");
352
353 return 0;
354 }
355
dc_fg_remove(struct platform_device * pdev)356 static void dc_fg_remove(struct platform_device *pdev)
357 {
358 component_del(&pdev->dev, &dc_fg_ops);
359 }
360
361 static const struct of_device_id dc_fg_dt_ids[] = {
362 { .compatible = "fsl,imx8qxp-dc-framegen" },
363 { /* sentinel */ }
364 };
365 MODULE_DEVICE_TABLE(of, dc_fg_dt_ids);
366
367 struct platform_driver dc_fg_driver = {
368 .probe = dc_fg_probe,
369 .remove = dc_fg_remove,
370 .driver = {
371 .name = "imx8-dc-framegen",
372 .suppress_bind_attrs = true,
373 .of_match_table = dc_fg_dt_ids,
374 },
375 };
376