| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 42 bool dcn31_are_clock_states_equal(struct dc_clocks *a,
43 struct dc_clocks *b);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 49 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
50 struct dc_clocks *b);
|
| H A D | dcn35_clk_mgr.c | 344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_notify_host_router_bw()
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks()
571 bool dcn35_are_clock_states_equal(struct dc_clocks *a, in dcn35_are_clock_states_equal()
572 struct dc_clocks *b) in dcn35_are_clock_states_equal()
723 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in init_clk_states()
1232 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks_fpga()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 36 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
39 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_c… in rv1_determine_dppclk_threshold()
88 struct dc_clocks *new_clocks, in ramp_up_dispclk_with_dpp()
194 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rv1_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 307 bool (*are_clock_states_equal) (struct dc_clocks *a,
308 struct dc_clocks *b);
348 struct dc_clocks clks;
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
405 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn2_init_clocks()
469 static bool dcn2_are_clock_states_equal(struct dc_clocks *a, in dcn2_are_clock_states_equal()
470 struct dc_clocks *b) in dcn2_are_clock_states_equal()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 114 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
198 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks()
436 static bool dcn3_are_clock_states_equal(struct dc_clocks *a, in dcn3_are_clock_states_equal()
437 struct dc_clocks *b) in dcn3_are_clock_states_equal()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks()
297 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *ne… in dcn32_update_dppclk_dispclk_freq()
506 struct dc_clocks *new_clocks, in dcn32_auto_dpm_test_log()
626 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn32_update_clocks()
1069 static bool dcn32_are_clock_states_equal(struct dc_clocks *a, in dcn32_are_clock_states_equal()
1070 struct dc_clocks *b) in dcn32_are_clock_states_equal()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks()
447 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rn_init_clocks()
528 static bool rn_are_clock_states_equal(struct dc_clocks *a, in rn_are_clock_states_equal()
529 struct dc_clocks *b) in rn_are_clock_states_equal()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 227 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn401_init_clocks()
411 struct dc_clocks *new_clocks, in dcn401_auto_dpm_test_log()
767 struct dc_clocks *new_clocks, in dcn401_build_update_bandwidth_clocks_sequence()
1080 struct dc_clocks *new_clocks, in dcn401_build_update_display_clocks_sequence()
1332 struct dc_clocks new_clocks; in dcn401_set_hard_min_memclk()
1339 memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks)); in dcn401_set_hard_min_memclk()
1428 static bool dcn401_are_clock_states_equal(struct dc_clocks *a, in dcn401_are_clock_states_equal()
1429 struct dc_clocks *b) in dcn401_are_clock_states_equal()
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_helpers.h | 192 struct dc_clocks *clks);
|
| H A D | dc.h | 680 struct dc_clocks { struct
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 563 struct dc_clocks clk;
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_helpers.c | 1119 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) in dm_set_dcn_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 758 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn32_initialize_min_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 4065 struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk; in dcn10_set_clock()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 60 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 7161 const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk; in dc_get_qos_info()
|