Searched refs:ctrl_2 (Results 1 – 5 of 5) sorted by relevance
46 pdu->ctrl_2 = (pdu->ctrl_2 & 0xFE) | bit_value; in llc_pdu_set_pf_bit()74 *pf_bit = pdu->ctrl_2 & LLC_S_PF_BIT_MASK; in llc_pdu_decode_pf_bit()112 pdu->ctrl_2 = 0; in llc_pdu_init_as_i_cmd()113 pdu->ctrl_2 |= (p_bit & LLC_I_PF_BIT_MASK); /* p/f bit */ in llc_pdu_init_as_i_cmd()115 pdu->ctrl_2 |= (nr << 1) & 0xFE; /* set N(R) in bits 10..16 */ in llc_pdu_init_as_i_cmd()132 pdu->ctrl_2 = 0; in llc_pdu_init_as_rej_cmd()133 pdu->ctrl_2 |= p_bit & LLC_S_PF_BIT_MASK; in llc_pdu_init_as_rej_cmd()135 pdu->ctrl_2 |= (nr << 1) & 0xFE; /* set N(R) in bits 10..16 */ in llc_pdu_init_as_rej_cmd()152 pdu->ctrl_2 = 0; in llc_pdu_init_as_rnr_cmd()153 pdu->ctrl_2 |= p_bit & LLC_S_PF_BIT_MASK; in llc_pdu_init_as_rnr_cmd()[all …]
123 #define LLC_I_GET_NR(pdu) (u8)((pdu->ctrl_2 & 0xFE) >> 1)127 #define LLC_I_PF_IS_0(pdu) ((!(pdu->ctrl_2 & LLC_I_PF_BIT_MASK)) ? 1 : 0)128 #define LLC_I_PF_IS_1(pdu) ((pdu->ctrl_2 & LLC_I_PF_BIT_MASK) ? 1 : 0)144 #define LLC_S_PF_IS_0(pdu) ((!(pdu->ctrl_2 & LLC_S_PF_BIT_MASK)) ? 1 : 0)145 #define LLC_S_PF_IS_1(pdu) ((pdu->ctrl_2 & LLC_S_PF_BIT_MASK) ? 1 : 0)147 #define PDU_SUPV_GET_Nr(pdu) ((pdu->ctrl_2 & 0xFE) >> 1)203 u8 ctrl_2; member
492 u16 ctrl, ctrl_2; in dwcmshc_set_uhs_signaling() local494 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()496 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; in dwcmshc_set_uhs_signaling()499 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; in dwcmshc_set_uhs_signaling()501 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; in dwcmshc_set_uhs_signaling()504 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; in dwcmshc_set_uhs_signaling()506 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; in dwcmshc_set_uhs_signaling()509 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; in dwcmshc_set_uhs_signaling()516 ctrl_2 |= DWCMSHC_CTRL_HS400; in dwcmshc_set_uhs_signaling()520 ctrl_2 |= SDHCI_CTRL_VDD_180; in dwcmshc_set_uhs_signaling()[all …]
1707 u16 ctrl_2; in sdhci_set_gl9763e_signaling() local1709 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()1710 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; in sdhci_set_gl9763e_signaling()1712 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; in sdhci_set_gl9763e_signaling()1714 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; in sdhci_set_gl9763e_signaling()1716 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; in sdhci_set_gl9763e_signaling()1718 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; in sdhci_set_gl9763e_signaling()1720 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
97 __u8 ctrl_2; /* control byte #2 */ member