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Searched refs:ctr1 (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/dma/stm32/
H A Dstm32-dma3.c245 u32 ctr1; member
386 dev_dbg(chan2dev(chan), "| C%dTR1: %08x\n", chan->id, hwdesc->ctr1); in stm32_dma3_chan_dump_hwdesc()
472 u32 ctr1 = readl_relaxed(ddata->base + STM32_DMA3_CTR1(chan->id)); in stm32_dma3_check_user_setting() local
478 u32 sdw = 1 << FIELD_GET(CTR1_SDW_LOG2, ctr1); in stm32_dma3_check_user_setting()
479 u32 ddw = 1 << FIELD_GET(CTR1_DDW_LOG2, ctr1); in stm32_dma3_check_user_setting()
480 u32 sap = FIELD_GET(CTR1_SAP, ctr1); in stm32_dma3_check_user_setting()
481 u32 dap = FIELD_GET(CTR1_DAP, ctr1); in stm32_dma3_check_user_setting()
487 if (FIELD_GET(CTR1_PAM, ctr1) == CTR1_PAM_PACK_UNPACK && bndt % ddw) in stm32_dma3_check_user_setting()
502 u32 ctr1, u32 ctr2, bool is_last, bool is_cyclic) in stm32_dma3_chan_prep_hwdesc() argument
509 hwdesc->ctr1 = ctr1; in stm32_dma3_chan_prep_hwdesc()
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/linux/drivers/clk/renesas/
H A Dr9a09g077-cpg.c586 u32 ctr0, ctr1; in r9a09g077_cpg_pll3_clk_recalc_rate() local
593 ctr1 = readl(CPG_PLL3_VCO_CTR1(pll_clk->reg)); in r9a09g077_cpg_pll3_clk_recalc_rate()
597 kdiv = (s16)FIELD_GET(CPG_PLL3_VCO_CTR1_KDIV, ctr1); in r9a09g077_cpg_pll3_clk_recalc_rate()
598 sdiv = FIELD_GET(CPG_PLL3_VCO_CTR1_SDIV, ctr1); in r9a09g077_cpg_pll3_clk_recalc_rate()