1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
4 *
5 * IDT PCIe-switch NTB Linux driver
6 *
7 * Contact Information:
8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
9 */
10 /*
11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
12 * This driver primarily is developed to have an access to EEPROM device of
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
14 * operations from/to EEPROM, which is located at private (so called Master)
15 * SMBus of switches. Using that interface this the driver creates a simple
16 * binary sysfs-file in the device directory:
17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
18 * In case if read-only flag is specified in the dts-node of device desription,
19 * User-space applications won't be able to write to the EEPROM sysfs-node.
20 * Additionally IDT 89HPESx SMBus interface has an ability to write/read
21 * data of device CSRs. This driver exposes debugf-file to perform simple IO
22 * operations using that ability for just basic debug purpose. Particularly
23 * next file is created in the specific debugfs-directory:
24 * /sys/kernel/debug/idt_csr/
25 * Format of the debugfs-node is:
26 * $ cat /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
27 * <CSR address>:<CSR value>
28 * So reading the content of the file gives current CSR address and it value.
29 * If User-space application wishes to change current CSR address,
30 * it can just write a proper value to the sysfs-file:
31 * $ echo "<CSR address>" > /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>
32 * If it wants to change the CSR value as well, the format of the write
33 * operation is:
34 * $ echo "<CSR address>:<CSR value>" > \
35 * /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
36 * CSR address and value can be any of hexadecimal, decimal or octal format.
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/init.h>
41 #include <linux/module.h>
42 #include <linux/types.h>
43 #include <linux/sizes.h>
44 #include <linux/slab.h>
45 #include <linux/mutex.h>
46 #include <linux/sysfs.h>
47 #include <linux/debugfs.h>
48 #include <linux/property.h>
49 #include <linux/i2c.h>
50 #include <linux/pci_ids.h>
51 #include <linux/delay.h>
52
53 #define IDT_NAME "89hpesx"
54 #define IDT_89HPESX_DESC "IDT 89HPESx SMBus-slave interface driver"
55 #define IDT_89HPESX_VER "1.0"
56
57 MODULE_DESCRIPTION(IDT_89HPESX_DESC);
58 MODULE_VERSION(IDT_89HPESX_VER);
59 MODULE_LICENSE("GPL v2");
60 MODULE_AUTHOR("T-platforms");
61
62 /*
63 * struct idt_89hpesx_dev - IDT 89HPESx device data structure
64 * @eesize: Size of EEPROM in bytes (calculated from "idt,eecompatible")
65 * @eero: EEPROM Read-only flag
66 * @eeaddr: EEPROM custom address
67 *
68 * @inieecmd: Initial cmd value for EEPROM read/write operations
69 * @inicsrcmd: Initial cmd value for CSR read/write operations
70 * @iniccode: Initialial command code value for IO-operations
71 *
72 * @csr: CSR address to perform read operation
73 *
74 * @smb_write: SMBus write method
75 * @smb_read: SMBus read method
76 * @smb_mtx: SMBus mutex
77 *
78 * @client: i2c client used to perform IO operations
79 *
80 * @ee_file: EEPROM read/write sysfs-file
81 */
82 struct idt_smb_seq;
83 struct idt_89hpesx_dev {
84 u32 eesize;
85 bool eero;
86 u8 eeaddr;
87
88 u8 inieecmd;
89 u8 inicsrcmd;
90 u8 iniccode;
91
92 u16 csr;
93
94 int (*smb_write)(struct idt_89hpesx_dev *, const struct idt_smb_seq *);
95 int (*smb_read)(struct idt_89hpesx_dev *, struct idt_smb_seq *);
96 struct mutex smb_mtx;
97
98 struct i2c_client *client;
99
100 struct bin_attribute *ee_file;
101 struct dentry *csr_dir;
102 };
103
104 /*
105 * struct idt_smb_seq - sequence of data to be read/written from/to IDT 89HPESx
106 * @ccode: SMBus command code
107 * @bytecnt: Byte count of operation
108 * @data: Data to by written
109 */
110 struct idt_smb_seq {
111 u8 ccode;
112 u8 bytecnt;
113 u8 *data;
114 };
115
116 /*
117 * struct idt_eeprom_seq - sequence of data to be read/written from/to EEPROM
118 * @cmd: Transaction CMD
119 * @eeaddr: EEPROM custom address
120 * @memaddr: Internal memory address of EEPROM
121 * @data: Data to be written at the memory address
122 */
123 struct idt_eeprom_seq {
124 u8 cmd;
125 u8 eeaddr;
126 __le16 memaddr;
127 u8 data;
128 } __packed;
129
130 /*
131 * struct idt_csr_seq - sequence of data to be read/written from/to CSR
132 * @cmd: Transaction CMD
133 * @csraddr: Internal IDT device CSR address
134 * @data: Data to be read/written from/to the CSR address
135 */
136 struct idt_csr_seq {
137 u8 cmd;
138 __le16 csraddr;
139 __le32 data;
140 } __packed;
141
142 /*
143 * SMBus command code macros
144 * @CCODE_END: Indicates the end of transaction
145 * @CCODE_START: Indicates the start of transaction
146 * @CCODE_CSR: CSR read/write transaction
147 * @CCODE_EEPROM: EEPROM read/write transaction
148 * @CCODE_BYTE: Supplied data has BYTE length
149 * @CCODE_WORD: Supplied data has WORD length
150 * @CCODE_BLOCK: Supplied data has variable length passed in bytecnt
151 * byte right following CCODE byte
152 */
153 #define CCODE_END ((u8)0x01)
154 #define CCODE_START ((u8)0x02)
155 #define CCODE_CSR ((u8)0x00)
156 #define CCODE_EEPROM ((u8)0x04)
157 #define CCODE_BYTE ((u8)0x00)
158 #define CCODE_WORD ((u8)0x20)
159 #define CCODE_BLOCK ((u8)0x40)
160 #define CCODE_PEC ((u8)0x80)
161
162 /*
163 * EEPROM command macros
164 * @EEPROM_OP_WRITE: EEPROM write operation
165 * @EEPROM_OP_READ: EEPROM read operation
166 * @EEPROM_USA: Use specified address of EEPROM
167 * @EEPROM_NAERR: EEPROM device is not ready to respond
168 * @EEPROM_LAERR: EEPROM arbitration loss error
169 * @EEPROM_MSS: EEPROM misplace start & stop bits error
170 * @EEPROM_WR_CNT: Bytes count to perform write operation
171 * @EEPROM_WRRD_CNT: Bytes count to write before reading
172 * @EEPROM_RD_CNT: Bytes count to perform read operation
173 * @EEPROM_DEF_SIZE: Fall back size of EEPROM
174 * @EEPROM_DEF_ADDR: Defatul EEPROM address
175 * @EEPROM_TOUT: Timeout before retry read operation if eeprom is busy
176 */
177 #define EEPROM_OP_WRITE ((u8)0x00)
178 #define EEPROM_OP_READ ((u8)0x01)
179 #define EEPROM_USA ((u8)0x02)
180 #define EEPROM_NAERR ((u8)0x08)
181 #define EEPROM_LAERR ((u8)0x10)
182 #define EEPROM_MSS ((u8)0x20)
183 #define EEPROM_WR_CNT ((u8)5)
184 #define EEPROM_WRRD_CNT ((u8)4)
185 #define EEPROM_RD_CNT ((u8)5)
186 #define EEPROM_DEF_SIZE ((u16)4096)
187 #define EEPROM_DEF_ADDR ((u8)0x50)
188 #define EEPROM_TOUT (100)
189
190 /*
191 * CSR command macros
192 * @CSR_DWE: Enable all four bytes of the operation
193 * @CSR_OP_WRITE: CSR write operation
194 * @CSR_OP_READ: CSR read operation
195 * @CSR_RERR: Read operation error
196 * @CSR_WERR: Write operation error
197 * @CSR_WR_CNT: Bytes count to perform write operation
198 * @CSR_WRRD_CNT: Bytes count to write before reading
199 * @CSR_RD_CNT: Bytes count to perform read operation
200 * @CSR_MAX: Maximum CSR address
201 * @CSR_DEF: Default CSR address
202 * @CSR_REAL_ADDR: CSR real unshifted address
203 */
204 #define CSR_DWE ((u8)0x0F)
205 #define CSR_OP_WRITE ((u8)0x00)
206 #define CSR_OP_READ ((u8)0x10)
207 #define CSR_RERR ((u8)0x40)
208 #define CSR_WERR ((u8)0x80)
209 #define CSR_WR_CNT ((u8)7)
210 #define CSR_WRRD_CNT ((u8)3)
211 #define CSR_RD_CNT ((u8)7)
212 #define CSR_MAX ((u32)0x3FFFF)
213 #define CSR_DEF ((u16)0x0000)
214 #define CSR_REAL_ADDR(val) ((unsigned int)val << 2)
215
216 /*
217 * IDT 89HPESx basic register
218 * @IDT_VIDDID_CSR: PCIe VID and DID of IDT 89HPESx
219 * @IDT_VID_MASK: Mask of VID
220 */
221 #define IDT_VIDDID_CSR ((u32)0x0000)
222 #define IDT_VID_MASK ((u32)0xFFFF)
223
224 /*
225 * IDT 89HPESx can send NACK when new command is sent before previous one
226 * fininshed execution. In this case driver retries operation
227 * certain times.
228 * @RETRY_CNT: Number of retries before giving up and fail
229 * @idt_smb_safe: Generate a retry loop on corresponding SMBus method
230 */
231 #define RETRY_CNT (128)
232 #define idt_smb_safe(ops, args...) ({ \
233 int __retry = RETRY_CNT; \
234 s32 __sts; \
235 do { \
236 __sts = i2c_smbus_ ## ops ## _data(args); \
237 } while (__retry-- && __sts < 0); \
238 __sts; \
239 })
240
241 /*===========================================================================
242 * i2c bus level IO-operations
243 *===========================================================================
244 */
245
246 /*
247 * idt_smb_write_byte() - SMBus write method when I2C_SMBUS_BYTE_DATA operation
248 * is only available
249 * @pdev: Pointer to the driver data
250 * @seq: Sequence of data to be written
251 */
idt_smb_write_byte(struct idt_89hpesx_dev * pdev,const struct idt_smb_seq * seq)252 static int idt_smb_write_byte(struct idt_89hpesx_dev *pdev,
253 const struct idt_smb_seq *seq)
254 {
255 s32 sts;
256 u8 ccode;
257 int idx;
258
259 /* Loop over the supplied data sending byte one-by-one */
260 for (idx = 0; idx < seq->bytecnt; idx++) {
261 /* Collect the command code byte */
262 ccode = seq->ccode | CCODE_BYTE;
263 if (idx == 0)
264 ccode |= CCODE_START;
265 if (idx == seq->bytecnt - 1)
266 ccode |= CCODE_END;
267
268 /* Send data to the device */
269 sts = idt_smb_safe(write_byte, pdev->client, ccode,
270 seq->data[idx]);
271 if (sts != 0)
272 return (int)sts;
273 }
274
275 return 0;
276 }
277
278 /*
279 * idt_smb_read_byte() - SMBus read method when I2C_SMBUS_BYTE_DATA operation
280 * is only available
281 * @pdev: Pointer to the driver data
282 * @seq: Buffer to read data to
283 */
idt_smb_read_byte(struct idt_89hpesx_dev * pdev,struct idt_smb_seq * seq)284 static int idt_smb_read_byte(struct idt_89hpesx_dev *pdev,
285 struct idt_smb_seq *seq)
286 {
287 s32 sts;
288 u8 ccode;
289 int idx;
290
291 /* Loop over the supplied buffer receiving byte one-by-one */
292 for (idx = 0; idx < seq->bytecnt; idx++) {
293 /* Collect the command code byte */
294 ccode = seq->ccode | CCODE_BYTE;
295 if (idx == 0)
296 ccode |= CCODE_START;
297 if (idx == seq->bytecnt - 1)
298 ccode |= CCODE_END;
299
300 /* Read data from the device */
301 sts = idt_smb_safe(read_byte, pdev->client, ccode);
302 if (sts < 0)
303 return (int)sts;
304
305 seq->data[idx] = (u8)sts;
306 }
307
308 return 0;
309 }
310
311 /*
312 * idt_smb_write_word() - SMBus write method when I2C_SMBUS_BYTE_DATA and
313 * I2C_FUNC_SMBUS_WORD_DATA operations are available
314 * @pdev: Pointer to the driver data
315 * @seq: Sequence of data to be written
316 */
idt_smb_write_word(struct idt_89hpesx_dev * pdev,const struct idt_smb_seq * seq)317 static int idt_smb_write_word(struct idt_89hpesx_dev *pdev,
318 const struct idt_smb_seq *seq)
319 {
320 s32 sts;
321 u8 ccode;
322 int idx, evencnt;
323
324 /* Calculate the even count of data to send */
325 evencnt = seq->bytecnt - (seq->bytecnt % 2);
326
327 /* Loop over the supplied data sending two bytes at a time */
328 for (idx = 0; idx < evencnt; idx += 2) {
329 /* Collect the command code byte */
330 ccode = seq->ccode | CCODE_WORD;
331 if (idx == 0)
332 ccode |= CCODE_START;
333 if (idx == evencnt - 2)
334 ccode |= CCODE_END;
335
336 /* Send word data to the device */
337 sts = idt_smb_safe(write_word, pdev->client, ccode,
338 *(u16 *)&seq->data[idx]);
339 if (sts != 0)
340 return (int)sts;
341 }
342
343 /* If there is odd number of bytes then send just one last byte */
344 if (seq->bytecnt != evencnt) {
345 /* Collect the command code byte */
346 ccode = seq->ccode | CCODE_BYTE | CCODE_END;
347 if (idx == 0)
348 ccode |= CCODE_START;
349
350 /* Send byte data to the device */
351 sts = idt_smb_safe(write_byte, pdev->client, ccode,
352 seq->data[idx]);
353 if (sts != 0)
354 return (int)sts;
355 }
356
357 return 0;
358 }
359
360 /*
361 * idt_smb_read_word() - SMBus read method when I2C_SMBUS_BYTE_DATA and
362 * I2C_FUNC_SMBUS_WORD_DATA operations are available
363 * @pdev: Pointer to the driver data
364 * @seq: Buffer to read data to
365 */
idt_smb_read_word(struct idt_89hpesx_dev * pdev,struct idt_smb_seq * seq)366 static int idt_smb_read_word(struct idt_89hpesx_dev *pdev,
367 struct idt_smb_seq *seq)
368 {
369 s32 sts;
370 u8 ccode;
371 int idx, evencnt;
372
373 /* Calculate the even count of data to send */
374 evencnt = seq->bytecnt - (seq->bytecnt % 2);
375
376 /* Loop over the supplied data reading two bytes at a time */
377 for (idx = 0; idx < evencnt; idx += 2) {
378 /* Collect the command code byte */
379 ccode = seq->ccode | CCODE_WORD;
380 if (idx == 0)
381 ccode |= CCODE_START;
382 if (idx == evencnt - 2)
383 ccode |= CCODE_END;
384
385 /* Read word data from the device */
386 sts = idt_smb_safe(read_word, pdev->client, ccode);
387 if (sts < 0)
388 return (int)sts;
389
390 *(u16 *)&seq->data[idx] = (u16)sts;
391 }
392
393 /* If there is odd number of bytes then receive just one last byte */
394 if (seq->bytecnt != evencnt) {
395 /* Collect the command code byte */
396 ccode = seq->ccode | CCODE_BYTE | CCODE_END;
397 if (idx == 0)
398 ccode |= CCODE_START;
399
400 /* Read last data byte from the device */
401 sts = idt_smb_safe(read_byte, pdev->client, ccode);
402 if (sts < 0)
403 return (int)sts;
404
405 seq->data[idx] = (u8)sts;
406 }
407
408 return 0;
409 }
410
411 /*
412 * idt_smb_write_block() - SMBus write method when I2C_SMBUS_BLOCK_DATA
413 * operation is available
414 * @pdev: Pointer to the driver data
415 * @seq: Sequence of data to be written
416 */
idt_smb_write_block(struct idt_89hpesx_dev * pdev,const struct idt_smb_seq * seq)417 static int idt_smb_write_block(struct idt_89hpesx_dev *pdev,
418 const struct idt_smb_seq *seq)
419 {
420 u8 ccode;
421
422 /* Return error if too much data passed to send */
423 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
424 return -EINVAL;
425
426 /* Collect the command code byte */
427 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
428
429 /* Send block of data to the device */
430 return idt_smb_safe(write_block, pdev->client, ccode, seq->bytecnt,
431 seq->data);
432 }
433
434 /*
435 * idt_smb_read_block() - SMBus read method when I2C_SMBUS_BLOCK_DATA
436 * operation is available
437 * @pdev: Pointer to the driver data
438 * @seq: Buffer to read data to
439 */
idt_smb_read_block(struct idt_89hpesx_dev * pdev,struct idt_smb_seq * seq)440 static int idt_smb_read_block(struct idt_89hpesx_dev *pdev,
441 struct idt_smb_seq *seq)
442 {
443 s32 sts;
444 u8 ccode;
445
446 /* Return error if too much data passed to send */
447 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
448 return -EINVAL;
449
450 /* Collect the command code byte */
451 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
452
453 /* Read block of data from the device */
454 sts = idt_smb_safe(read_block, pdev->client, ccode, seq->data);
455 if (sts != seq->bytecnt)
456 return (sts < 0 ? sts : -ENODATA);
457
458 return 0;
459 }
460
461 /*
462 * idt_smb_write_i2c_block() - SMBus write method when I2C_SMBUS_I2C_BLOCK_DATA
463 * operation is available
464 * @pdev: Pointer to the driver data
465 * @seq: Sequence of data to be written
466 *
467 * NOTE It's usual SMBus write block operation, except the actual data length is
468 * sent as first byte of data
469 */
idt_smb_write_i2c_block(struct idt_89hpesx_dev * pdev,const struct idt_smb_seq * seq)470 static int idt_smb_write_i2c_block(struct idt_89hpesx_dev *pdev,
471 const struct idt_smb_seq *seq)
472 {
473 u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
474
475 /* Return error if too much data passed to send */
476 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
477 return -EINVAL;
478
479 /* Collect the data to send. Length byte must be added prior the data */
480 buf[0] = seq->bytecnt;
481 memcpy(&buf[1], seq->data, seq->bytecnt);
482
483 /* Collect the command code byte */
484 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
485
486 /* Send length and block of data to the device */
487 return idt_smb_safe(write_i2c_block, pdev->client, ccode,
488 seq->bytecnt + 1, buf);
489 }
490
491 /*
492 * idt_smb_read_i2c_block() - SMBus read method when I2C_SMBUS_I2C_BLOCK_DATA
493 * operation is available
494 * @pdev: Pointer to the driver data
495 * @seq: Buffer to read data to
496 *
497 * NOTE It's usual SMBus read block operation, except the actual data length is
498 * retrieved as first byte of data
499 */
idt_smb_read_i2c_block(struct idt_89hpesx_dev * pdev,struct idt_smb_seq * seq)500 static int idt_smb_read_i2c_block(struct idt_89hpesx_dev *pdev,
501 struct idt_smb_seq *seq)
502 {
503 u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
504 s32 sts;
505
506 /* Return error if too much data passed to send */
507 if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
508 return -EINVAL;
509
510 /* Collect the command code byte */
511 ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
512
513 /* Read length and block of data from the device */
514 sts = idt_smb_safe(read_i2c_block, pdev->client, ccode,
515 seq->bytecnt + 1, buf);
516 if (sts != seq->bytecnt + 1)
517 return (sts < 0 ? sts : -ENODATA);
518 if (buf[0] != seq->bytecnt)
519 return -ENODATA;
520
521 /* Copy retrieved data to the output data buffer */
522 memcpy(seq->data, &buf[1], seq->bytecnt);
523
524 return 0;
525 }
526
527 /*===========================================================================
528 * EEPROM IO-operations
529 *===========================================================================
530 */
531
532 /*
533 * idt_eeprom_read_byte() - read just one byte from EEPROM
534 * @pdev: Pointer to the driver data
535 * @memaddr: Start EEPROM memory address
536 * @data: Data to be written to EEPROM
537 */
idt_eeprom_read_byte(struct idt_89hpesx_dev * pdev,u16 memaddr,u8 * data)538 static int idt_eeprom_read_byte(struct idt_89hpesx_dev *pdev, u16 memaddr,
539 u8 *data)
540 {
541 struct device *dev = &pdev->client->dev;
542 struct idt_eeprom_seq eeseq;
543 struct idt_smb_seq smbseq;
544 int ret, retry;
545
546 /* Initialize SMBus sequence fields */
547 smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
548 smbseq.data = (u8 *)&eeseq;
549
550 /*
551 * Sometimes EEPROM may respond with NACK if it's busy with previous
552 * operation, so we need to perform a few attempts of read cycle
553 */
554 retry = RETRY_CNT;
555 do {
556 /* Send EEPROM memory address to read data from */
557 smbseq.bytecnt = EEPROM_WRRD_CNT;
558 eeseq.cmd = pdev->inieecmd | EEPROM_OP_READ;
559 eeseq.eeaddr = pdev->eeaddr;
560 eeseq.memaddr = cpu_to_le16(memaddr);
561 ret = pdev->smb_write(pdev, &smbseq);
562 if (ret != 0) {
563 dev_err(dev, "Failed to init eeprom addr 0x%02x",
564 memaddr);
565 break;
566 }
567
568 /* Perform read operation */
569 smbseq.bytecnt = EEPROM_RD_CNT;
570 ret = pdev->smb_read(pdev, &smbseq);
571 if (ret != 0) {
572 dev_err(dev, "Failed to read eeprom data 0x%02x",
573 memaddr);
574 break;
575 }
576
577 /* Restart read operation if the device is busy */
578 if (retry && (eeseq.cmd & EEPROM_NAERR)) {
579 dev_dbg(dev, "EEPROM busy, retry reading after %d ms",
580 EEPROM_TOUT);
581 msleep(EEPROM_TOUT);
582 continue;
583 }
584
585 /* Check whether IDT successfully read data from EEPROM */
586 if (eeseq.cmd & (EEPROM_NAERR | EEPROM_LAERR | EEPROM_MSS)) {
587 dev_err(dev,
588 "Communication with eeprom failed, cmd 0x%hhx",
589 eeseq.cmd);
590 ret = -EREMOTEIO;
591 break;
592 }
593
594 /* Save retrieved data and exit the loop */
595 *data = eeseq.data;
596 break;
597 } while (retry--);
598
599 /* Return the status of operation */
600 return ret;
601 }
602
603 /*
604 * idt_eeprom_write() - EEPROM write operation
605 * @pdev: Pointer to the driver data
606 * @memaddr: Start EEPROM memory address
607 * @len: Length of data to be written
608 * @data: Data to be written to EEPROM
609 */
idt_eeprom_write(struct idt_89hpesx_dev * pdev,u16 memaddr,u16 len,const u8 * data)610 static int idt_eeprom_write(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
611 const u8 *data)
612 {
613 struct device *dev = &pdev->client->dev;
614 struct idt_eeprom_seq eeseq;
615 struct idt_smb_seq smbseq;
616 int ret;
617 u16 idx;
618
619 /* Initialize SMBus sequence fields */
620 smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
621 smbseq.data = (u8 *)&eeseq;
622
623 /* Send data byte-by-byte, checking if it is successfully written */
624 for (idx = 0; idx < len; idx++, memaddr++) {
625 /* Lock IDT SMBus device */
626 mutex_lock(&pdev->smb_mtx);
627
628 /* Perform write operation */
629 smbseq.bytecnt = EEPROM_WR_CNT;
630 eeseq.cmd = pdev->inieecmd | EEPROM_OP_WRITE;
631 eeseq.eeaddr = pdev->eeaddr;
632 eeseq.memaddr = cpu_to_le16(memaddr);
633 eeseq.data = data[idx];
634 ret = pdev->smb_write(pdev, &smbseq);
635 if (ret != 0) {
636 dev_err(dev,
637 "Failed to write 0x%04hx:0x%02hhx to eeprom",
638 memaddr, data[idx]);
639 goto err_mutex_unlock;
640 }
641
642 /*
643 * Check whether the data is successfully written by reading
644 * from the same EEPROM memory address.
645 */
646 eeseq.data = ~data[idx];
647 ret = idt_eeprom_read_byte(pdev, memaddr, &eeseq.data);
648 if (ret != 0)
649 goto err_mutex_unlock;
650
651 /* Check whether the read byte is the same as written one */
652 if (eeseq.data != data[idx]) {
653 dev_err(dev, "Values don't match 0x%02hhx != 0x%02hhx",
654 eeseq.data, data[idx]);
655 ret = -EREMOTEIO;
656 goto err_mutex_unlock;
657 }
658
659 /* Unlock IDT SMBus device */
660 err_mutex_unlock:
661 mutex_unlock(&pdev->smb_mtx);
662 if (ret != 0)
663 return ret;
664 }
665
666 return 0;
667 }
668
669 /*
670 * idt_eeprom_read() - EEPROM read operation
671 * @pdev: Pointer to the driver data
672 * @memaddr: Start EEPROM memory address
673 * @len: Length of data to read
674 * @buf: Buffer to read data to
675 */
idt_eeprom_read(struct idt_89hpesx_dev * pdev,u16 memaddr,u16 len,u8 * buf)676 static int idt_eeprom_read(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
677 u8 *buf)
678 {
679 int ret;
680 u16 idx;
681
682 /* Read data byte-by-byte, retrying if it wasn't successful */
683 for (idx = 0; idx < len; idx++, memaddr++) {
684 /* Lock IDT SMBus device */
685 mutex_lock(&pdev->smb_mtx);
686
687 /* Just read the byte to the buffer */
688 ret = idt_eeprom_read_byte(pdev, memaddr, &buf[idx]);
689
690 /* Unlock IDT SMBus device */
691 mutex_unlock(&pdev->smb_mtx);
692
693 /* Return error if read operation failed */
694 if (ret != 0)
695 return ret;
696 }
697
698 return 0;
699 }
700
701 /*===========================================================================
702 * CSR IO-operations
703 *===========================================================================
704 */
705
706 /*
707 * idt_csr_write() - CSR write operation
708 * @pdev: Pointer to the driver data
709 * @csraddr: CSR address (with no two LS bits)
710 * @data: Data to be written to CSR
711 */
idt_csr_write(struct idt_89hpesx_dev * pdev,u16 csraddr,const u32 data)712 static int idt_csr_write(struct idt_89hpesx_dev *pdev, u16 csraddr,
713 const u32 data)
714 {
715 struct device *dev = &pdev->client->dev;
716 struct idt_csr_seq csrseq;
717 struct idt_smb_seq smbseq;
718 int ret;
719
720 /* Initialize SMBus sequence fields */
721 smbseq.ccode = pdev->iniccode | CCODE_CSR;
722 smbseq.data = (u8 *)&csrseq;
723
724 /* Lock IDT SMBus device */
725 mutex_lock(&pdev->smb_mtx);
726
727 /* Perform write operation */
728 smbseq.bytecnt = CSR_WR_CNT;
729 csrseq.cmd = pdev->inicsrcmd | CSR_OP_WRITE;
730 csrseq.csraddr = cpu_to_le16(csraddr);
731 csrseq.data = cpu_to_le32(data);
732 ret = pdev->smb_write(pdev, &smbseq);
733 if (ret != 0) {
734 dev_err(dev, "Failed to write 0x%04x: 0x%04x to csr",
735 CSR_REAL_ADDR(csraddr), data);
736 goto err_mutex_unlock;
737 }
738
739 /* Send CSR address to read data from */
740 smbseq.bytecnt = CSR_WRRD_CNT;
741 csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
742 ret = pdev->smb_write(pdev, &smbseq);
743 if (ret != 0) {
744 dev_err(dev, "Failed to init csr address 0x%04x",
745 CSR_REAL_ADDR(csraddr));
746 goto err_mutex_unlock;
747 }
748
749 /* Perform read operation */
750 smbseq.bytecnt = CSR_RD_CNT;
751 ret = pdev->smb_read(pdev, &smbseq);
752 if (ret != 0) {
753 dev_err(dev, "Failed to read csr 0x%04x",
754 CSR_REAL_ADDR(csraddr));
755 goto err_mutex_unlock;
756 }
757
758 /* Check whether IDT successfully retrieved CSR data */
759 if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
760 dev_err(dev, "IDT failed to perform CSR r/w");
761 ret = -EREMOTEIO;
762 goto err_mutex_unlock;
763 }
764
765 /* Unlock IDT SMBus device */
766 err_mutex_unlock:
767 mutex_unlock(&pdev->smb_mtx);
768
769 return ret;
770 }
771
772 /*
773 * idt_csr_read() - CSR read operation
774 * @pdev: Pointer to the driver data
775 * @csraddr: CSR address (with no two LS bits)
776 * @data: Data to be written to CSR
777 */
idt_csr_read(struct idt_89hpesx_dev * pdev,u16 csraddr,u32 * data)778 static int idt_csr_read(struct idt_89hpesx_dev *pdev, u16 csraddr, u32 *data)
779 {
780 struct device *dev = &pdev->client->dev;
781 struct idt_csr_seq csrseq;
782 struct idt_smb_seq smbseq;
783 int ret;
784
785 /* Initialize SMBus sequence fields */
786 smbseq.ccode = pdev->iniccode | CCODE_CSR;
787 smbseq.data = (u8 *)&csrseq;
788
789 /* Lock IDT SMBus device */
790 mutex_lock(&pdev->smb_mtx);
791
792 /* Send CSR register address before reading it */
793 smbseq.bytecnt = CSR_WRRD_CNT;
794 csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
795 csrseq.csraddr = cpu_to_le16(csraddr);
796 ret = pdev->smb_write(pdev, &smbseq);
797 if (ret != 0) {
798 dev_err(dev, "Failed to init csr address 0x%04x",
799 CSR_REAL_ADDR(csraddr));
800 goto err_mutex_unlock;
801 }
802
803 /* Perform read operation */
804 smbseq.bytecnt = CSR_RD_CNT;
805 ret = pdev->smb_read(pdev, &smbseq);
806 if (ret != 0) {
807 dev_err(dev, "Failed to read csr 0x%04x",
808 CSR_REAL_ADDR(csraddr));
809 goto err_mutex_unlock;
810 }
811
812 /* Check whether IDT successfully retrieved CSR data */
813 if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
814 dev_err(dev, "IDT failed to perform CSR r/w");
815 ret = -EREMOTEIO;
816 goto err_mutex_unlock;
817 }
818
819 /* Save data retrieved from IDT */
820 *data = le32_to_cpu(csrseq.data);
821
822 /* Unlock IDT SMBus device */
823 err_mutex_unlock:
824 mutex_unlock(&pdev->smb_mtx);
825
826 return ret;
827 }
828
829 /*===========================================================================
830 * Sysfs/debugfs-nodes IO-operations
831 *===========================================================================
832 */
833
834 /*
835 * eeprom_write() - EEPROM sysfs-node write callback
836 * @filep: Pointer to the file system node
837 * @kobj: Pointer to the kernel object related to the sysfs-node
838 * @attr: Attributes of the file
839 * @buf: Buffer to write data to
840 * @off: Offset at which data should be written to
841 * @count: Number of bytes to write
842 */
eeprom_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * attr,char * buf,loff_t off,size_t count)843 static ssize_t eeprom_write(struct file *filp, struct kobject *kobj,
844 const struct bin_attribute *attr,
845 char *buf, loff_t off, size_t count)
846 {
847 struct idt_89hpesx_dev *pdev;
848 int ret;
849
850 /* Retrieve driver data */
851 pdev = dev_get_drvdata(kobj_to_dev(kobj));
852
853 /* Perform EEPROM write operation */
854 ret = idt_eeprom_write(pdev, (u16)off, (u16)count, (u8 *)buf);
855 return (ret != 0 ? ret : count);
856 }
857
858 /*
859 * eeprom_read() - EEPROM sysfs-node read callback
860 * @filep: Pointer to the file system node
861 * @kobj: Pointer to the kernel object related to the sysfs-node
862 * @attr: Attributes of the file
863 * @buf: Buffer to write data to
864 * @off: Offset at which data should be written to
865 * @count: Number of bytes to write
866 */
eeprom_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * attr,char * buf,loff_t off,size_t count)867 static ssize_t eeprom_read(struct file *filp, struct kobject *kobj,
868 const struct bin_attribute *attr,
869 char *buf, loff_t off, size_t count)
870 {
871 struct idt_89hpesx_dev *pdev;
872 int ret;
873
874 /* Retrieve driver data */
875 pdev = dev_get_drvdata(kobj_to_dev(kobj));
876
877 /* Perform EEPROM read operation */
878 ret = idt_eeprom_read(pdev, (u16)off, (u16)count, (u8 *)buf);
879 return (ret != 0 ? ret : count);
880 }
881
882 /*
883 * idt_dbgfs_csr_write() - CSR debugfs-node write callback
884 * @filep: Pointer to the file system file descriptor
885 * @buf: Buffer to read data from
886 * @count: Size of the buffer
887 * @offp: Offset within the file
888 *
889 * It accepts either "0x<reg addr>:0x<value>" for saving register address
890 * and writing value to specified DWORD register or "0x<reg addr>" for
891 * just saving register address in order to perform next read operation.
892 *
893 * WARNING No spaces are allowed. Incoming string must be strictly formated as:
894 * "<reg addr>:<value>". Register address must be aligned within 4 bytes
895 * (one DWORD).
896 */
idt_dbgfs_csr_write(struct file * filep,const char __user * ubuf,size_t count,loff_t * offp)897 static ssize_t idt_dbgfs_csr_write(struct file *filep, const char __user *ubuf,
898 size_t count, loff_t *offp)
899 {
900 struct idt_89hpesx_dev *pdev = filep->private_data;
901 char *colon_ch, *csraddr_str, *csrval_str;
902 int ret;
903 u32 csraddr, csrval;
904 char *buf;
905
906 if (*offp)
907 return 0;
908
909 /* Copy data from User-space */
910 buf = memdup_user_nul(ubuf, count);
911 if (IS_ERR(buf))
912 return PTR_ERR(buf);
913
914 /* Find position of colon in the buffer */
915 colon_ch = strnchr(buf, count, ':');
916
917 /*
918 * If there is colon passed then new CSR value should be parsed as
919 * well, so allocate buffer for CSR address substring.
920 * If no colon is found, then string must have just one number with
921 * no new CSR value
922 */
923 if (colon_ch != NULL) {
924 /* Copy the register address to the substring buffer */
925 csraddr_str = kmemdup_nul(buf, colon_ch - buf, GFP_KERNEL);
926 if (csraddr_str == NULL) {
927 ret = -ENOMEM;
928 goto free_buf;
929 }
930 /* Register value must follow the colon */
931 csrval_str = colon_ch + 1;
932 } else /* if (str_colon == NULL) */ {
933 csraddr_str = (char *)buf; /* Just to shut warning up */
934 csrval_str = NULL;
935 }
936
937 /* Convert CSR address to u32 value */
938 ret = kstrtou32(csraddr_str, 0, &csraddr);
939 if (ret != 0)
940 goto free_csraddr_str;
941
942 /* Check whether passed register address is valid */
943 if (csraddr > CSR_MAX || !IS_ALIGNED(csraddr, SZ_4)) {
944 ret = -EINVAL;
945 goto free_csraddr_str;
946 }
947
948 /* Shift register address to the right so to have u16 address */
949 pdev->csr = (csraddr >> 2);
950
951 /* Parse new CSR value and send it to IDT, if colon has been found */
952 if (colon_ch != NULL) {
953 ret = kstrtou32(csrval_str, 0, &csrval);
954 if (ret != 0)
955 goto free_csraddr_str;
956
957 ret = idt_csr_write(pdev, pdev->csr, csrval);
958 if (ret != 0)
959 goto free_csraddr_str;
960 }
961
962 /* Free memory only if colon has been found */
963 free_csraddr_str:
964 if (colon_ch != NULL)
965 kfree(csraddr_str);
966
967 /* Free buffer allocated for data retrieved from User-space */
968 free_buf:
969 kfree(buf);
970
971 return (ret != 0 ? ret : count);
972 }
973
974 /*
975 * idt_dbgfs_csr_read() - CSR debugfs-node read callback
976 * @filep: Pointer to the file system file descriptor
977 * @buf: Buffer to write data to
978 * @count: Size of the buffer
979 * @offp: Offset within the file
980 *
981 * It just prints the pair "0x<reg addr>:0x<value>" to passed buffer.
982 */
983 #define CSRBUF_SIZE ((size_t)32)
idt_dbgfs_csr_read(struct file * filep,char __user * ubuf,size_t count,loff_t * offp)984 static ssize_t idt_dbgfs_csr_read(struct file *filep, char __user *ubuf,
985 size_t count, loff_t *offp)
986 {
987 struct idt_89hpesx_dev *pdev = filep->private_data;
988 u32 csraddr, csrval;
989 char buf[CSRBUF_SIZE];
990 int ret, size;
991
992 /* Perform CSR read operation */
993 ret = idt_csr_read(pdev, pdev->csr, &csrval);
994 if (ret != 0)
995 return ret;
996
997 /* Shift register address to the left so to have real address */
998 csraddr = ((u32)pdev->csr << 2);
999
1000 /* Print the "0x<reg addr>:0x<value>" to buffer */
1001 size = snprintf(buf, CSRBUF_SIZE, "0x%05x:0x%08x\n",
1002 (unsigned int)csraddr, (unsigned int)csrval);
1003
1004 /* Copy data to User-space */
1005 return simple_read_from_buffer(ubuf, count, offp, buf, size);
1006 }
1007
1008 /*
1009 * eeprom_attribute - EEPROM sysfs-node attributes
1010 *
1011 * NOTE Size will be changed in compliance with OF node. EEPROM attribute will
1012 * be read-only as well if the corresponding flag is specified in OF node.
1013 */
1014 static const BIN_ATTR_RW(eeprom, EEPROM_DEF_SIZE);
1015
1016 /*
1017 * csr_dbgfs_ops - CSR debugfs-node read/write operations
1018 */
1019 static const struct file_operations csr_dbgfs_ops = {
1020 .owner = THIS_MODULE,
1021 .open = simple_open,
1022 .write = idt_dbgfs_csr_write,
1023 .read = idt_dbgfs_csr_read
1024 };
1025
1026 /*===========================================================================
1027 * Driver init/deinit methods
1028 *===========================================================================
1029 */
1030
1031 /*
1032 * idt_set_defval() - disable EEPROM access by default
1033 * @pdev: Pointer to the driver data
1034 */
idt_set_defval(struct idt_89hpesx_dev * pdev)1035 static void idt_set_defval(struct idt_89hpesx_dev *pdev)
1036 {
1037 /* If OF info is missing then use next values */
1038 pdev->eesize = 0;
1039 pdev->eero = true;
1040 pdev->inieecmd = 0;
1041 pdev->eeaddr = 0;
1042 }
1043
1044 static const struct i2c_device_id ee_ids[];
1045
1046 /*
1047 * idt_ee_match_id() - check whether the node belongs to compatible EEPROMs
1048 */
idt_ee_match_id(struct fwnode_handle * fwnode)1049 static const struct i2c_device_id *idt_ee_match_id(struct fwnode_handle *fwnode)
1050 {
1051 const struct i2c_device_id *id = ee_ids;
1052 const char *compatible, *p;
1053 char devname[I2C_NAME_SIZE];
1054 int ret;
1055
1056 ret = fwnode_property_read_string(fwnode, "compatible", &compatible);
1057 if (ret)
1058 return NULL;
1059
1060 p = strchr(compatible, ',');
1061 strscpy(devname, p ? p + 1 : compatible, sizeof(devname));
1062 /* Search through the device name */
1063 while (id->name[0]) {
1064 if (strcmp(devname, id->name) == 0)
1065 return id;
1066 id++;
1067 }
1068 return NULL;
1069 }
1070
1071 /*
1072 * idt_get_fw_data() - get IDT i2c-device parameters from device tree
1073 * @pdev: Pointer to the driver data
1074 */
idt_get_fw_data(struct idt_89hpesx_dev * pdev)1075 static void idt_get_fw_data(struct idt_89hpesx_dev *pdev)
1076 {
1077 struct device *dev = &pdev->client->dev;
1078 struct fwnode_handle *fwnode;
1079 const struct i2c_device_id *ee_id = NULL;
1080 u32 eeprom_addr;
1081 int ret;
1082
1083 device_for_each_child_node(dev, fwnode) {
1084 ee_id = idt_ee_match_id(fwnode);
1085 if (ee_id)
1086 break;
1087
1088 dev_warn(dev, "Skip unsupported EEPROM device %pfw\n", fwnode);
1089 }
1090
1091 /* If there is no fwnode EEPROM device, then set zero size */
1092 if (!ee_id) {
1093 dev_warn(dev, "No fwnode, EEPROM access disabled");
1094 idt_set_defval(pdev);
1095 return;
1096 }
1097
1098 /* Retrieve EEPROM size */
1099 pdev->eesize = (u32)ee_id->driver_data;
1100
1101 /* Get custom EEPROM address from 'reg' attribute */
1102 ret = fwnode_property_read_u32(fwnode, "reg", &eeprom_addr);
1103 if (ret || (eeprom_addr == 0)) {
1104 dev_warn(dev, "No EEPROM reg found, use default address 0x%x",
1105 EEPROM_DEF_ADDR);
1106 pdev->inieecmd = 0;
1107 pdev->eeaddr = EEPROM_DEF_ADDR << 1;
1108 } else {
1109 pdev->inieecmd = EEPROM_USA;
1110 pdev->eeaddr = eeprom_addr << 1;
1111 }
1112
1113 /* Check EEPROM 'read-only' flag */
1114 if (fwnode_property_read_bool(fwnode, "read-only"))
1115 pdev->eero = true;
1116 else /* if (!fwnode_property_read_bool(node, "read-only")) */
1117 pdev->eero = false;
1118
1119 fwnode_handle_put(fwnode);
1120 dev_info(dev, "EEPROM of %d bytes found by 0x%x",
1121 pdev->eesize, pdev->eeaddr);
1122 }
1123
1124 /*
1125 * idt_create_pdev() - create and init data structure of the driver
1126 * @client: i2c client of IDT PCIe-switch device
1127 */
idt_create_pdev(struct i2c_client * client)1128 static struct idt_89hpesx_dev *idt_create_pdev(struct i2c_client *client)
1129 {
1130 struct idt_89hpesx_dev *pdev;
1131
1132 /* Allocate memory for driver data */
1133 pdev = devm_kmalloc(&client->dev, sizeof(struct idt_89hpesx_dev),
1134 GFP_KERNEL);
1135 if (pdev == NULL)
1136 return ERR_PTR(-ENOMEM);
1137
1138 /* Initialize basic fields of the data */
1139 pdev->client = client;
1140 i2c_set_clientdata(client, pdev);
1141
1142 /* Read firmware nodes information */
1143 idt_get_fw_data(pdev);
1144
1145 /* Initialize basic CSR CMD field - use full DWORD-sized r/w ops */
1146 pdev->inicsrcmd = CSR_DWE;
1147 pdev->csr = CSR_DEF;
1148
1149 /* Enable Packet Error Checking if it's supported by adapter */
1150 if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_PEC)) {
1151 pdev->iniccode = CCODE_PEC;
1152 client->flags |= I2C_CLIENT_PEC;
1153 } else /* PEC is unsupported */ {
1154 pdev->iniccode = 0;
1155 }
1156
1157 return pdev;
1158 }
1159
1160 /*
1161 * idt_free_pdev() - free data structure of the driver
1162 * @pdev: Pointer to the driver data
1163 */
idt_free_pdev(struct idt_89hpesx_dev * pdev)1164 static void idt_free_pdev(struct idt_89hpesx_dev *pdev)
1165 {
1166 /* Clear driver data from device private field */
1167 i2c_set_clientdata(pdev->client, NULL);
1168 }
1169
1170 /*
1171 * idt_set_smbus_ops() - set supported SMBus operations
1172 * @pdev: Pointer to the driver data
1173 * Return status of smbus check operations
1174 */
idt_set_smbus_ops(struct idt_89hpesx_dev * pdev)1175 static int idt_set_smbus_ops(struct idt_89hpesx_dev *pdev)
1176 {
1177 struct i2c_adapter *adapter = pdev->client->adapter;
1178 struct device *dev = &pdev->client->dev;
1179
1180 /* Check i2c adapter read functionality */
1181 if (i2c_check_functionality(adapter,
1182 I2C_FUNC_SMBUS_READ_BLOCK_DATA)) {
1183 pdev->smb_read = idt_smb_read_block;
1184 dev_dbg(dev, "SMBus block-read op chosen");
1185 } else if (i2c_check_functionality(adapter,
1186 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1187 pdev->smb_read = idt_smb_read_i2c_block;
1188 dev_dbg(dev, "SMBus i2c-block-read op chosen");
1189 } else if (i2c_check_functionality(adapter,
1190 I2C_FUNC_SMBUS_READ_WORD_DATA) &&
1191 i2c_check_functionality(adapter,
1192 I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1193 pdev->smb_read = idt_smb_read_word;
1194 dev_warn(dev, "Use slow word/byte SMBus read ops");
1195 } else if (i2c_check_functionality(adapter,
1196 I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1197 pdev->smb_read = idt_smb_read_byte;
1198 dev_warn(dev, "Use slow byte SMBus read op");
1199 } else /* no supported smbus read operations */ {
1200 dev_err(dev, "No supported SMBus read op");
1201 return -EPFNOSUPPORT;
1202 }
1203
1204 /* Check i2c adapter write functionality */
1205 if (i2c_check_functionality(adapter,
1206 I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)) {
1207 pdev->smb_write = idt_smb_write_block;
1208 dev_dbg(dev, "SMBus block-write op chosen");
1209 } else if (i2c_check_functionality(adapter,
1210 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
1211 pdev->smb_write = idt_smb_write_i2c_block;
1212 dev_dbg(dev, "SMBus i2c-block-write op chosen");
1213 } else if (i2c_check_functionality(adapter,
1214 I2C_FUNC_SMBUS_WRITE_WORD_DATA) &&
1215 i2c_check_functionality(adapter,
1216 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1217 pdev->smb_write = idt_smb_write_word;
1218 dev_warn(dev, "Use slow word/byte SMBus write op");
1219 } else if (i2c_check_functionality(adapter,
1220 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1221 pdev->smb_write = idt_smb_write_byte;
1222 dev_warn(dev, "Use slow byte SMBus write op");
1223 } else /* no supported smbus write operations */ {
1224 dev_err(dev, "No supported SMBus write op");
1225 return -EPFNOSUPPORT;
1226 }
1227
1228 /* Initialize IDT SMBus slave interface mutex */
1229 mutex_init(&pdev->smb_mtx);
1230
1231 return 0;
1232 }
1233
1234 /*
1235 * idt_check_dev() - check whether it's really IDT 89HPESx device
1236 * @pdev: Pointer to the driver data
1237 * Return status of i2c adapter check operation
1238 */
idt_check_dev(struct idt_89hpesx_dev * pdev)1239 static int idt_check_dev(struct idt_89hpesx_dev *pdev)
1240 {
1241 struct device *dev = &pdev->client->dev;
1242 u32 viddid;
1243 int ret;
1244
1245 /* Read VID and DID directly from IDT memory space */
1246 ret = idt_csr_read(pdev, IDT_VIDDID_CSR, &viddid);
1247 if (ret != 0) {
1248 dev_err(dev, "Failed to read VID/DID");
1249 return ret;
1250 }
1251
1252 /* Check whether it's IDT device */
1253 if ((viddid & IDT_VID_MASK) != PCI_VENDOR_ID_IDT) {
1254 dev_err(dev, "Got unsupported VID/DID: 0x%08x", viddid);
1255 return -ENODEV;
1256 }
1257
1258 dev_info(dev, "Found IDT 89HPES device VID:0x%04x, DID:0x%04x",
1259 (viddid & IDT_VID_MASK), (viddid >> 16));
1260
1261 return 0;
1262 }
1263
1264 /*
1265 * idt_create_sysfs_files() - create sysfs attribute files
1266 * @pdev: Pointer to the driver data
1267 * Return status of operation
1268 */
idt_create_sysfs_files(struct idt_89hpesx_dev * pdev)1269 static int idt_create_sysfs_files(struct idt_89hpesx_dev *pdev)
1270 {
1271 struct device *dev = &pdev->client->dev;
1272 int ret;
1273
1274 /* Don't do anything if EEPROM isn't accessible */
1275 if (pdev->eesize == 0) {
1276 dev_dbg(dev, "Skip creating sysfs-files");
1277 return 0;
1278 }
1279
1280 /*
1281 * Allocate memory for attribute file and copy the declared EEPROM attr
1282 * structure to change some of fields
1283 */
1284 pdev->ee_file = devm_kmemdup(dev, &bin_attr_eeprom,
1285 sizeof(*pdev->ee_file), GFP_KERNEL);
1286 if (!pdev->ee_file)
1287 return -ENOMEM;
1288
1289 /* In case of read-only EEPROM get rid of write ability */
1290 if (pdev->eero) {
1291 pdev->ee_file->attr.mode &= ~0200;
1292 pdev->ee_file->write = NULL;
1293 }
1294 /* Create EEPROM sysfs file */
1295 pdev->ee_file->size = pdev->eesize;
1296 ret = sysfs_create_bin_file(&dev->kobj, pdev->ee_file);
1297 if (ret != 0) {
1298 dev_err(dev, "Failed to create EEPROM sysfs-node");
1299 return ret;
1300 }
1301
1302 return 0;
1303 }
1304
1305 /*
1306 * idt_remove_sysfs_files() - remove sysfs attribute files
1307 * @pdev: Pointer to the driver data
1308 */
idt_remove_sysfs_files(struct idt_89hpesx_dev * pdev)1309 static void idt_remove_sysfs_files(struct idt_89hpesx_dev *pdev)
1310 {
1311 struct device *dev = &pdev->client->dev;
1312
1313 /* Don't do anything if EEPROM wasn't accessible */
1314 if (pdev->eesize == 0)
1315 return;
1316
1317 /* Remove EEPROM sysfs file */
1318 sysfs_remove_bin_file(&dev->kobj, pdev->ee_file);
1319 }
1320
1321 /*
1322 * idt_probe() - IDT 89HPESx driver probe() callback method
1323 */
idt_probe(struct i2c_client * client)1324 static int idt_probe(struct i2c_client *client)
1325 {
1326 struct idt_89hpesx_dev *pdev;
1327 int ret;
1328
1329 /* Create driver data */
1330 pdev = idt_create_pdev(client);
1331 if (IS_ERR(pdev))
1332 return PTR_ERR(pdev);
1333
1334 /* Set SMBus operations */
1335 ret = idt_set_smbus_ops(pdev);
1336 if (ret != 0)
1337 goto err_free_pdev;
1338
1339 /* Check whether it is truly IDT 89HPESx device */
1340 ret = idt_check_dev(pdev);
1341 if (ret != 0)
1342 goto err_free_pdev;
1343
1344 /* Create sysfs files */
1345 ret = idt_create_sysfs_files(pdev);
1346 if (ret != 0)
1347 goto err_free_pdev;
1348
1349 /* Create debugfs files */
1350 debugfs_create_file(pdev->client->name, 0600, client->debugfs, pdev, &csr_dbgfs_ops);
1351
1352 return 0;
1353
1354 err_free_pdev:
1355 idt_free_pdev(pdev);
1356
1357 return ret;
1358 }
1359
1360 /*
1361 * idt_remove() - IDT 89HPESx driver remove() callback method
1362 */
idt_remove(struct i2c_client * client)1363 static void idt_remove(struct i2c_client *client)
1364 {
1365 struct idt_89hpesx_dev *pdev = i2c_get_clientdata(client);
1366
1367 /* Remove sysfs files */
1368 idt_remove_sysfs_files(pdev);
1369
1370 /* Discard driver data structure */
1371 idt_free_pdev(pdev);
1372 }
1373
1374 /*
1375 * ee_ids - array of supported EEPROMs
1376 */
1377 static const struct i2c_device_id ee_ids[] = {
1378 { .name = "24c32", .driver_data = 4096 },
1379 { .name = "24c64", .driver_data = 8192 },
1380 { .name = "24c128", .driver_data = 16384 },
1381 { .name = "24c256", .driver_data = 32768 },
1382 { .name = "24c512", .driver_data = 65536 },
1383 { }
1384 };
1385 MODULE_DEVICE_TABLE(i2c, ee_ids);
1386
1387 /*
1388 * idt_ids - supported IDT 89HPESx devices
1389 */
1390 static const struct i2c_device_id idt_ids[] = {
1391 { .name = "89hpes8nt2" },
1392 { .name = "89hpes12nt3" },
1393
1394 { .name = "89hpes24nt6ag2" },
1395 { .name = "89hpes32nt8ag2" },
1396 { .name = "89hpes32nt8bg2" },
1397 { .name = "89hpes12nt12g2" },
1398 { .name = "89hpes16nt16g2" },
1399 { .name = "89hpes24nt24g2" },
1400 { .name = "89hpes32nt24ag2" },
1401 { .name = "89hpes32nt24bg2" },
1402
1403 { .name = "89hpes12n3" },
1404 { .name = "89hpes12n3a" },
1405 { .name = "89hpes24n3" },
1406 { .name = "89hpes24n3a" },
1407
1408 { .name = "89hpes32h8" },
1409 { .name = "89hpes32h8g2" },
1410 { .name = "89hpes48h12" },
1411 { .name = "89hpes48h12g2" },
1412 { .name = "89hpes48h12ag2" },
1413 { .name = "89hpes16h16" },
1414 { .name = "89hpes22h16" },
1415 { .name = "89hpes22h16g2" },
1416 { .name = "89hpes34h16" },
1417 { .name = "89hpes34h16g2" },
1418 { .name = "89hpes64h16" },
1419 { .name = "89hpes64h16g2" },
1420 { .name = "89hpes64h16ag2" },
1421
1422 /* { .name = "89hpes3t3" }, // No SMBus-slave iface */
1423 { .name = "89hpes12t3g2" },
1424 { .name = "89hpes24t3g2" },
1425 /* { .name = "89hpes4t4" }, // No SMBus-slave iface */
1426 { .name = "89hpes16t4" },
1427 { .name = "89hpes4t4g2" },
1428 { .name = "89hpes10t4g2" },
1429 { .name = "89hpes16t4g2" },
1430 { .name = "89hpes16t4ag2" },
1431 { .name = "89hpes5t5" },
1432 { .name = "89hpes6t5" },
1433 { .name = "89hpes8t5" },
1434 { .name = "89hpes8t5a" },
1435 { .name = "89hpes24t6" },
1436 { .name = "89hpes6t6g2" },
1437 { .name = "89hpes24t6g2" },
1438 { .name = "89hpes16t7" },
1439 { .name = "89hpes32t8" },
1440 { .name = "89hpes32t8g2" },
1441 { .name = "89hpes48t12" },
1442 { .name = "89hpes48t12g2" },
1443 { /* END OF LIST */ }
1444 };
1445 MODULE_DEVICE_TABLE(i2c, idt_ids);
1446
1447 static const struct of_device_id idt_of_match[] = {
1448 { .compatible = "idt,89hpes8nt2" },
1449 { .compatible = "idt,89hpes12nt3" },
1450
1451 { .compatible = "idt,89hpes24nt6ag2" },
1452 { .compatible = "idt,89hpes32nt8ag2" },
1453 { .compatible = "idt,89hpes32nt8bg2" },
1454 { .compatible = "idt,89hpes12nt12g2" },
1455 { .compatible = "idt,89hpes16nt16g2" },
1456 { .compatible = "idt,89hpes24nt24g2" },
1457 { .compatible = "idt,89hpes32nt24ag2" },
1458 { .compatible = "idt,89hpes32nt24bg2" },
1459
1460 { .compatible = "idt,89hpes12n3" },
1461 { .compatible = "idt,89hpes12n3a" },
1462 { .compatible = "idt,89hpes24n3" },
1463 { .compatible = "idt,89hpes24n3a" },
1464
1465 { .compatible = "idt,89hpes32h8" },
1466 { .compatible = "idt,89hpes32h8g2" },
1467 { .compatible = "idt,89hpes48h12" },
1468 { .compatible = "idt,89hpes48h12g2" },
1469 { .compatible = "idt,89hpes48h12ag2" },
1470 { .compatible = "idt,89hpes16h16" },
1471 { .compatible = "idt,89hpes22h16" },
1472 { .compatible = "idt,89hpes22h16g2" },
1473 { .compatible = "idt,89hpes34h16" },
1474 { .compatible = "idt,89hpes34h16g2" },
1475 { .compatible = "idt,89hpes64h16" },
1476 { .compatible = "idt,89hpes64h16g2" },
1477 { .compatible = "idt,89hpes64h16ag2" },
1478
1479 { .compatible = "idt,89hpes12t3g2" },
1480 { .compatible = "idt,89hpes24t3g2" },
1481
1482 { .compatible = "idt,89hpes16t4" },
1483 { .compatible = "idt,89hpes4t4g2" },
1484 { .compatible = "idt,89hpes10t4g2" },
1485 { .compatible = "idt,89hpes16t4g2" },
1486 { .compatible = "idt,89hpes16t4ag2" },
1487 { .compatible = "idt,89hpes5t5" },
1488 { .compatible = "idt,89hpes6t5" },
1489 { .compatible = "idt,89hpes8t5" },
1490 { .compatible = "idt,89hpes8t5a" },
1491 { .compatible = "idt,89hpes24t6" },
1492 { .compatible = "idt,89hpes6t6g2" },
1493 { .compatible = "idt,89hpes24t6g2" },
1494 { .compatible = "idt,89hpes16t7" },
1495 { .compatible = "idt,89hpes32t8" },
1496 { .compatible = "idt,89hpes32t8g2" },
1497 { .compatible = "idt,89hpes48t12" },
1498 { .compatible = "idt,89hpes48t12g2" },
1499 { }
1500 };
1501 MODULE_DEVICE_TABLE(of, idt_of_match);
1502
1503 /*
1504 * idt_driver - IDT 89HPESx driver structure
1505 */
1506 static struct i2c_driver idt_driver = {
1507 .driver = {
1508 .name = IDT_NAME,
1509 .of_match_table = idt_of_match,
1510 },
1511 .probe = idt_probe,
1512 .remove = idt_remove,
1513 .id_table = idt_ids,
1514 };
1515 module_i2c_driver(idt_driver);
1516