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Searched refs:crtc_offset (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_cursor.c39 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
46 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
53 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor()
58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
68 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
72 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
99 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in radeon_show_cursor()
101 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
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H A Drs600.c123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip()
137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
160 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
333 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
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H A Drv515.c682 int index_reg = 0x6578 + crtc->crtc_offset; in atom_rv515_force_tv_scaler()
683 int data_reg = 0x657c + crtc->crtc_offset; in atom_rv515_force_tv_scaler()
685 WREG32(0x659C + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
686 WREG32(0x6594 + crtc->crtc_offset, 0x705); in atom_rv515_force_tv_scaler()
687 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); in atom_rv515_force_tv_scaler()
688 WREG32(0x65D8 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
689 WREG32(0x65B0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
690 WREG32(0x65C0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
691 WREG32(0x65D4 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
H A Drv770.c804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
815 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rv770_page_flip()
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
827 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
832 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
840 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
848 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
H A Datombios_encoders.c2020 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2023 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
2026 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2029 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
2032 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2035 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
H A Dr100.c174 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
181 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in r100_page_flip()
185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
H A Dr600.c346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
/linux/arch/loongarch/pci/
H A Dpci.c113 u32 i, val, count, crtc_offset, device; in loongson_gpu_fixup_dma_hang() local
129 crtc_offset = 0x10; in loongson_gpu_fixup_dma_hang()
133 crtc_offset = 0x400; in loongson_gpu_fixup_dma_hang()
140 for (i = 0; i < CRTC_NUM_MAX; i++, crtc_reg += crtc_offset) { in loongson_gpu_fixup_dma_hang()
/linux/drivers/video/fbdev/aty/
H A Dradeonfb.h191 u32 crtc_offset; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h466 uint32_t crtc_offset; member