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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
H A Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
H A Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
H A Dr9a09g057.dtsi8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
218 clocks = <&cpg CPG_MOD 0x5>;
219 power-domains = <&cpg>;
220 resets = <&cpg 0x36>;
226 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
233 power-domains = <&cpg>;
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
146 clocks = <&cpg CPG_MOD 402>;
148 resets = <&cpg 402>;
162 clocks = <&cpg CPG_MOD 912>;
164 resets = <&cpg 912>;
177 clocks = <&cpg CPG_MOD 911>;
179 resets = <&cpg 911>;
192 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
91 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
161 clocks = <&cpg CPG_MOD 402>;
163 resets = <&cpg 402>;
177 clocks = <&cpg CPG_MOD 912>;
179 resets = <&cpg 912>;
192 clocks = <&cpg CPG_MOD 911>;
194 resets = <&cpg 911>;
207 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
98 clocks = <&cpg CPG_MOD 402>;
100 resets = <&cpg 402>;
114 clocks = <&cpg CPG_MOD 912>;
116 resets = <&cpg 912>;
129 clocks = <&cpg CPG_MOD 911>;
131 resets = <&cpg 911>;
144 clocks = <&cpg CPG_MOD 910>;
146 resets = <&cpg 910>;
159 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
158 clocks = <&cpg CPG_MOD 402>;
160 resets = <&cpg 402>;
174 clocks = <&cpg CPG_MOD 912>;
176 resets = <&cpg 912>;
189 clocks = <&cpg CPG_MOD 911>;
191 resets = <&cpg 911>;
204 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
104 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
116 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
194 clocks = <&cpg CPG_MOD 402>;
196 resets = <&cpg 402>;
210 clocks = <&cpg CPG_MOD 912>;
212 resets = <&cpg 912>;
225 clocks = <&cpg CPG_MOD 911>;
227 resets = <&cpg 911>;
240 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
209 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
222 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
235 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
248 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
359 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a77960.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
323 clocks = <&cpg CPG_MOD 402>;
325 resets = <&cpg 402>;
339 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
44 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
54 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
64 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
133 clocks = <&cpg CPG_MOD 402>;
135 resets = <&cpg 402>;
149 clocks = <&cpg CPG_MOD 912>;
151 resets = <&cpg 912>;
164 clocks = <&cpg CPG_MOD 911>;
[all …]
H A Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
129 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
157 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
274 clocks = <&cpg CPG_MOD 402>;
276 resets = <&cpg 402>;
290 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a77961.dtsi8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
323 clocks = <&cpg CPG_MOD 402>;
325 resets = <&cpg 402>;
339 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a77970.dtsi9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
44 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
104 clocks = <&cpg CPG_MOD 402>;
106 resets = <&cpg 402>;
120 clocks = <&cpg CPG_MOD 912>;
122 resets = <&cpg 912>;
135 clocks = <&cpg CPG_MOD 911>;
137 resets = <&cpg 911>;
150 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a774e1.dtsi10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
136 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
194 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
233 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
338 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr9a07g043u.dtsi26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
66 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
67 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
68 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
74 resets = <&cpg R9A07G043_CRU_PRESETN>,
75 <&cpg R9A07G043_CRU_ARESETN>;
77 power-domains = <&cpg>;
101 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
102 <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
103 <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>;
[all …]
/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c59 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
137 table, &cpg->lock); in r8a7740_cpg_register_clock()
143 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
158 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7740_cpg_clocks_init()
160 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
167 spin_lock_init(&cpg->lock); in r8a7740_cpg_clocks_init()
169 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
170 cpg->data.clk_num = num_clks; in r8a7740_cpg_clocks_init()
183 clk = r8a7740_cpg_register_clock(np, cpg, base, name); in r8a7740_cpg_clocks_init()
188 cpg->data.clks[i] = clk; in r8a7740_cpg_clocks_init()
[all …]
H A Dclk-sh73a0.c72 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
155 table, &cpg->lock); in sh73a0_cpg_register_clock()
161 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
173 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
175 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
182 spin_lock_init(&cpg->lock); in sh73a0_cpg_clocks_init()
184 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
185 cpg->data.clk_num = num_clks; in sh73a0_cpg_clocks_init()
203 clk = sh73a0_cpg_register_clock(np, cpg, base, name); in sh73a0_cpg_clocks_init()
208 cpg->data.clks[i] = clk; in sh73a0_cpg_clocks_init()
[all …]
H A Dclk-r8a73a4.c58 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
181 table, &cpg->lock); in r8a73a4_cpg_register_clock()
187 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
199 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a73a4_cpg_clocks_init()
201 if (cpg == NULL || clks == NULL) { in r8a73a4_cpg_clocks_init()
208 spin_lock_init(&cpg->lock); in r8a73a4_cpg_clocks_init()
210 cpg->data.clks = clks; in r8a73a4_cpg_clocks_init()
211 cpg->data.clk_num = num_clks; in r8a73a4_cpg_clocks_init()
224 clk = r8a73a4_cpg_register_clock(np, cpg, base, name); in r8a73a4_cpg_clocks_init()
229 cpg->data.clks[i] = clk; in r8a73a4_cpg_clocks_init()
[all …]
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi37 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
125 clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
126 <&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
128 power-domains = <&cpg>;
129 resets = <&cpg R9A07G043_IAX45_RESETN>;
139 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
140 power-domains = <&cpg>;
141 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
/linux/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c38 struct device_node *cpg, *extal; in get_extal_freq() local
42 cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match); in get_extal_freq()
43 if (!cpg) in get_extal_freq()
47 idx = of_property_match_string(cpg, "clock-names", match->data); in get_extal_freq()
48 extal = of_parse_phandle(cpg, "clocks", idx); in get_extal_freq()
49 of_node_put(cpg); in get_extal_freq()

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