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Searched refs:con0 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-pll.c682 u32 con0, con1; in samsung_pll45xx_set_rate() local
692 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
695 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
697 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
698 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
699 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
705 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
708 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
731 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
819 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
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/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-common.h271 unsigned int con0; member
312 unsigned int con0; member
H A Dmt8365-afe-pcm.c257 .con0 = AFE_CM1_CON0,
264 .con0 = AFE_CM2_CON0,
492 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con0, mask, val); in mt8365_afe_configure_cm()
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c90 unsigned int con0; member
201 etdm_reg->con0 = ETDM_IN1_CON0; in get_etdm_reg()
209 etdm_reg->con0 = ETDM_IN2_CON0; in get_etdm_reg()
217 etdm_reg->con0 = ETDM_OUT1_CON0; in get_etdm_reg()
225 etdm_reg->con0 = ETDM_OUT2_CON0; in get_etdm_reg()
234 etdm_reg->con0 = ETDM_OUT3_CON0; in get_etdm_reg()
1333 regmap_update_bits(afe->regmap, etdm_reg.con0, in mt8195_afe_enable_etdm()
1359 regmap_update_bits(afe->regmap, etdm_reg.con0, in mt8195_afe_disable_etdm()
1839 /* con0 */ in mtk_dai_etdm_out_configure()
1842 regmap_update_bits(afe->regmap, etdm_reg.con0, mas in mtk_dai_etdm_out_configure()
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/linux/drivers/video/fbdev/
H A Dpxa168fb.h357 #define CFG_COS0(con0) (con0) argument
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h585 #define CFG_COS0(con0) (con0) argument