Lines Matching refs:con0

681 	u32 con0, con1;
691 	con0 = readl_relaxed(pll->con_reg);
694 	if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
696 		con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
697 		con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
698 		writel_relaxed(con0, pll->con_reg);
704 	con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
707 	con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
730 	writel_relaxed(con0, pll->con_reg);
818 	u32 con0, con1, lock;
828 	con0 = readl_relaxed(pll->con_reg);
831 	if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
833 		con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
834 		con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
835 		writel_relaxed(con0, pll->con_reg);
848 		con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
852 		con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
856 		con0 |=	rate->vsel << PLL46XX_VSEL_SHIFT;
859 	con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
874 	writel_relaxed(con0, pll->con_reg);
1151 	u32 con0, con1;
1161 	con0 = readl_relaxed(pll->con_reg);
1168 	con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1171 	con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1174 	con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1175 	writel_relaxed(con0, pll->con_reg);