xref: /linux/arch/mips/include/asm/ip32/mace.h (revision e5451c8f8330e03ad3cfa16048b4daf961af434f) 
1 /*
2  * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 2000 Harald Koerfgen
9  * Copyright (C) 2004 Ladislav Michl
10  */
11 
12 #ifndef __ASM_MACE_H__
13 #define __ASM_MACE_H__
14 
15 /*
16  * Address map
17  */
18 #define MACE_BASE	0x1f000000	/* physical */
19 
20 /*
21  * PCI interface
22  */
23 struct mace_pci {
24 	volatile unsigned int error_addr;
25 	volatile unsigned int error;
26 #define MACEPCI_ERROR_MASTER_ABORT		BIT(31)
27 #define MACEPCI_ERROR_TARGET_ABORT		BIT(30)
28 #define MACEPCI_ERROR_DATA_PARITY_ERR		BIT(29)
29 #define MACEPCI_ERROR_RETRY_ERR			BIT(28)
30 #define MACEPCI_ERROR_ILLEGAL_CMD		BIT(27)
31 #define MACEPCI_ERROR_SYSTEM_ERR		BIT(26)
32 #define MACEPCI_ERROR_INTERRUPT_TEST		BIT(25)
33 #define MACEPCI_ERROR_PARITY_ERR		BIT(24)
34 #define MACEPCI_ERROR_OVERRUN			BIT(23)
35 #define MACEPCI_ERROR_RSVD			BIT(22)
36 #define MACEPCI_ERROR_MEMORY_ADDR		BIT(21)
37 #define MACEPCI_ERROR_CONFIG_ADDR		BIT(20)
38 #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID	BIT(19)
39 #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID	BIT(18)
40 #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID	BIT(17)
41 #define MACEPCI_ERROR_RETRY_ADDR_VALID		BIT(16)
42 #define MACEPCI_ERROR_SIG_TABORT		BIT(4)
43 #define MACEPCI_ERROR_DEVSEL_MASK		0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST		0
45 #define MACEPCI_ERROR_DEVSEL_MED		0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW		0x80
47 #define MACEPCI_ERROR_FBB			BIT(1)
48 #define MACEPCI_ERROR_66MHZ			BIT(0)
49 	volatile unsigned int control;
50 #define MACEPCI_CONTROL_INT(x)			BIT(x)
51 #define MACEPCI_CONTROL_INT_MASK		0xff
52 #define MACEPCI_CONTROL_SERR_ENA		BIT(8)
53 #define MACEPCI_CONTROL_ARB_N6			BIT(9)
54 #define MACEPCI_CONTROL_PARITY_ERR		BIT(10)
55 #define MACEPCI_CONTROL_MRMRA_ENA		BIT(11)
56 #define MACEPCI_CONTROL_ARB_N3			BIT(12)
57 #define MACEPCI_CONTROL_ARB_N4			BIT(13)
58 #define MACEPCI_CONTROL_ARB_N5			BIT(14)
59 #define MACEPCI_CONTROL_PARK_LIU		BIT(15)
60 #define MACEPCI_CONTROL_INV_INT(x)		BIT(16+x)
61 #define MACEPCI_CONTROL_INV_INT_MASK		0x00ff0000
62 #define MACEPCI_CONTROL_OVERRUN_INT		BIT(24)
63 #define MACEPCI_CONTROL_PARITY_INT		BIT(25)
64 #define MACEPCI_CONTROL_SERR_INT		BIT(26)
65 #define MACEPCI_CONTROL_IT_INT			BIT(27)
66 #define MACEPCI_CONTROL_RE_INT			BIT(28)
67 #define MACEPCI_CONTROL_DPED_INT		BIT(29)
68 #define MACEPCI_CONTROL_TAR_INT			BIT(30)
69 #define MACEPCI_CONTROL_MAR_INT			BIT(31)
70 	volatile unsigned int rev;
71 	unsigned int _pad[0xcf8/4 - 4];
72 	volatile unsigned int config_addr;
73 	union {
74 		volatile unsigned char b[4];
75 		volatile unsigned short w[2];
76 		volatile unsigned int l;
77 	} config_data;
78 };
79 #define MACEPCI_LOW_MEMORY		0x1a000000
80 #define MACEPCI_LOW_IO			0x18000000
81 #define MACEPCI_SWAPPED_VIEW		0
82 #define MACEPCI_NATIVE_VIEW		0x40000000
83 #define MACEPCI_IO			0x80000000
84 #define MACEPCI_HI_MEMORY		0x280000000
85 #define MACEPCI_HI_IO			0x100000000
86 
87 /*
88  * Video interface
89  */
90 struct mace_video {
91 	unsigned long xxx;	/* later... */
92 };
93 
94 /*
95  * Ethernet interface
96  */
97 struct mace_ethernet {
98 	volatile u64 mac_ctrl;
99 	volatile unsigned long int_stat;
100 	volatile unsigned long dma_ctrl;
101 	volatile unsigned long timer;
102 	volatile unsigned long tx_int_al;
103 	volatile unsigned long rx_int_al;
104 	volatile unsigned long tx_info;
105 	volatile unsigned long tx_info_al;
106 	volatile unsigned long rx_buff;
107 	volatile unsigned long rx_buff_al1;
108 	volatile unsigned long rx_buff_al2;
109 	volatile unsigned long diag;
110 	volatile unsigned long phy_data;
111 	volatile unsigned long phy_regs;
112 	volatile unsigned long phy_trans_go;
113 	volatile unsigned long backoff_seed;
114 	/*===================================*/
115 	volatile unsigned long imq_reserved[4];
116 	volatile unsigned long mac_addr;
117 	volatile unsigned long mac_addr2;
118 	volatile unsigned long mcast_filter;
119 	volatile unsigned long tx_ring_base;
120 	/* Following are read-only registers for debugging */
121 	volatile unsigned long tx_pkt1_hdr;
122 	volatile unsigned long tx_pkt1_ptr[3];
123 	volatile unsigned long tx_pkt2_hdr;
124 	volatile unsigned long tx_pkt2_ptr[3];
125 	/*===================================*/
126 	volatile unsigned long rx_fifo;
127 };
128 
129 /*
130  * Peripherals
131  */
132 
133 /* Audio registers */
134 struct mace_audio {
135 	volatile unsigned long control;
136 	volatile unsigned long codec_control;		/* codec status control */
137 	volatile unsigned long codec_mask;		/* codec status input mask */
138 	volatile unsigned long codec_read;		/* codec status read data */
139 	struct {
140 		volatile unsigned long control;		/* channel control */
141 		volatile unsigned long read_ptr;	/* channel read pointer */
142 		volatile unsigned long write_ptr;	/* channel write pointer */
143 		volatile unsigned long depth;		/* channel depth */
144 	} chan[3];
145 };
146 
147 
148 /* register definitions for parallel port DMA */
149 struct mace_parport {
150 	/* 0 - do nothing,
151 	 * 1 - pulse terminal count to the device after buffer is drained */
152 #define MACEPAR_CONTEXT_LASTFLAG	BIT(63)
153 	/* Should not cross 4K page boundary */
154 #define MACEPAR_CONTEXT_DATA_BOUND	0x0000000000001000UL
155 #define MACEPAR_CONTEXT_DATALEN_MASK	0x00000fff00000000UL
156 #define MACEPAR_CONTEXT_DATALEN_SHIFT	32
157 	/* Can be arbitrarily aligned on any byte boundary on output,
158 	 * 64 byte aligned on input */
159 #define MACEPAR_CONTEXT_BASEADDR_MASK	0x00000000ffffffffUL
160 	volatile u64 context_a;
161 	volatile u64 context_b;
162 	/* 0 - mem->device, 1 - device->mem */
163 #define MACEPAR_CTLSTAT_DIRECTION	BIT(0)
164 	/* 0 - channel frozen, 1 - channel enabled */
165 #define MACEPAR_CTLSTAT_ENABLE		BIT(1)
166 	/* 0 - channel active, 1 - complete channel reset */
167 #define MACEPAR_CTLSTAT_RESET		BIT(2)
168 #define MACEPAR_CTLSTAT_CTXB_VALID	BIT(3)
169 #define MACEPAR_CTLSTAT_CTXA_VALID	BIT(4)
170 	volatile u64 cntlstat;		/* Control/Status register */
171 #define MACEPAR_DIAG_CTXINUSE		BIT(0)
172 	/* 1 - Dma engine is enabled and processing something */
173 #define MACEPAR_DIAG_DMACTIVE		BIT(1)
174 	/* Counter of bytes left */
175 #define MACEPAR_DIAG_CTRMASK		0x0000000000003ffcUL
176 #define MACEPAR_DIAG_CTRSHIFT		2
177 	volatile u64 diagnostic;	/* RO: diagnostic register */
178 };
179 
180 /* ISA Control and DMA registers */
181 struct mace_isactrl {
182 	volatile unsigned long ringbase;
183 #define MACEISA_RINGBUFFERS_SIZE	(8 * 4096)
184 
185 	volatile unsigned long misc;
186 #define MACEISA_FLASH_WE		BIT(0)	/* 1=> Enable FLASH writes */
187 #define MACEISA_PWD_CLEAR		BIT(1)	/* 1=> PWD CLEAR jumper detected */
188 #define MACEISA_NIC_DEASSERT		BIT(2)
189 #define MACEISA_NIC_DATA		BIT(3)
190 #define MACEISA_LED_RED			BIT(4)	/* 0=> Illuminate red LED */
191 #define MACEISA_LED_GREEN		BIT(5)	/* 0=> Illuminate green LED */
192 #define MACEISA_DP_RAM_ENABLE		BIT(6)
193 
194 	volatile unsigned long istat;
195 	volatile unsigned long imask;
196 #define MACEISA_AUDIO_SW_INT		BIT(0)
197 #define MACEISA_AUDIO_SC_INT		BIT(1)
198 #define MACEISA_AUDIO1_DMAT_INT		BIT(2)
199 #define MACEISA_AUDIO1_OF_INT		BIT(3)
200 #define MACEISA_AUDIO2_DMAT_INT		BIT(4)
201 #define MACEISA_AUDIO2_MERR_INT		BIT(5)
202 #define MACEISA_AUDIO3_DMAT_INT		BIT(6)
203 #define MACEISA_AUDIO3_MERR_INT		BIT(7)
204 #define MACEISA_RTC_INT			BIT(8)
205 #define MACEISA_KEYB_INT		BIT(9)
206 #define MACEISA_KEYB_POLL_INT		BIT(10)
207 #define MACEISA_MOUSE_INT		BIT(11)
208 #define MACEISA_MOUSE_POLL_INT		BIT(12)
209 #define MACEISA_TIMER0_INT		BIT(13)
210 #define MACEISA_TIMER1_INT		BIT(14)
211 #define MACEISA_TIMER2_INT		BIT(15)
212 #define MACEISA_PARALLEL_INT		BIT(16)
213 #define MACEISA_PAR_CTXA_INT		BIT(17)
214 #define MACEISA_PAR_CTXB_INT		BIT(18)
215 #define MACEISA_PAR_MERR_INT		BIT(19)
216 #define MACEISA_SERIAL1_INT		BIT(20)
217 #define MACEISA_SERIAL1_TDMAT_INT	BIT(21)
218 #define MACEISA_SERIAL1_TDMAPR_INT	BIT(22)
219 #define MACEISA_SERIAL1_TDMAME_INT	BIT(23)
220 #define MACEISA_SERIAL1_RDMAT_INT	BIT(24)
221 #define MACEISA_SERIAL1_RDMAOR_INT	BIT(25)
222 #define MACEISA_SERIAL2_INT		BIT(26)
223 #define MACEISA_SERIAL2_TDMAT_INT	BIT(27)
224 #define MACEISA_SERIAL2_TDMAPR_INT	BIT(28)
225 #define MACEISA_SERIAL2_TDMAME_INT	BIT(29)
226 #define MACEISA_SERIAL2_RDMAT_INT	BIT(30)
227 #define MACEISA_SERIAL2_RDMAOR_INT	BIT(31)
228 
229 	volatile unsigned long _pad[0x2000/8 - 4];
230 
231 	volatile unsigned long dp_ram[0x400];
232 	struct mace_parport parport;
233 };
234 
235 /* Keyboard & Mouse registers
236  * -> drivers/input/serio/maceps2.c */
237 struct mace_ps2port {
238 	volatile unsigned long tx;
239 	volatile unsigned long rx;
240 	volatile unsigned long control;
241 	volatile unsigned long status;
242 };
243 
244 struct mace_ps2 {
245 	struct mace_ps2port keyb;
246 	struct mace_ps2port mouse;
247 };
248 
249 /* I2C registers
250  * -> drivers/i2c/algos/i2c-algo-sgi.c */
251 struct mace_i2c {
252 	volatile unsigned long config;
253 #define MACEI2C_RESET		BIT(0)
254 #define MACEI2C_FAST		BIT(1)
255 #define MACEI2C_DATA_OVERRIDE	BIT(2)
256 #define MACEI2C_CLOCK_OVERRIDE	BIT(3)
257 #define MACEI2C_DATA_STATUS	BIT(4)
258 #define MACEI2C_CLOCK_STATUS	BIT(5)
259 	volatile unsigned long control;
260 	volatile unsigned long data;
261 };
262 
263 /* Timer registers */
264 typedef union {
265 	volatile unsigned long ust_msc;
266 	struct reg {
267 		volatile unsigned int ust;
268 		volatile unsigned int msc;
269 	} reg;
270 } timer_reg;
271 
272 struct mace_timers {
273 	volatile unsigned long ust;
274 #define MACE_UST_PERIOD_NS	960
275 
276 	volatile unsigned long compare1;
277 	volatile unsigned long compare2;
278 	volatile unsigned long compare3;
279 
280 	timer_reg audio_in;
281 	timer_reg audio_out1;
282 	timer_reg audio_out2;
283 	timer_reg video_in1;
284 	timer_reg video_in2;
285 	timer_reg video_out;
286 };
287 
288 struct mace_perif {
289 	struct mace_audio audio;
290 	char _pad0[0x10000 - sizeof(struct mace_audio)];
291 
292 	struct mace_isactrl ctrl;
293 	char _pad1[0x10000 - sizeof(struct mace_isactrl)];
294 
295 	struct mace_ps2 ps2;
296 	char _pad2[0x10000 - sizeof(struct mace_ps2)];
297 
298 	struct mace_i2c i2c;
299 	char _pad3[0x10000 - sizeof(struct mace_i2c)];
300 
301 	struct mace_timers timers;
302 	char _pad4[0x10000 - sizeof(struct mace_timers)];
303 };
304 
305 
306 /*
307  * ISA peripherals
308  */
309 
310 /* Parallel port */
311 struct mace_parallel {
312 };
313 
314 struct mace_ecp1284 {	/* later... */
315 };
316 
317 /* Serial port */
318 struct mace_serial {
319 	volatile unsigned long xxx;	/* later... */
320 };
321 
322 struct mace_isa {
323 	struct mace_parallel parallel;
324 	char _pad1[0x8000 - sizeof(struct mace_parallel)];
325 
326 	struct mace_ecp1284 ecp1284;
327 	char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
328 
329 	struct mace_serial serial1;
330 	char _pad3[0x8000 - sizeof(struct mace_serial)];
331 
332 	struct mace_serial serial2;
333 	char _pad4[0x8000 - sizeof(struct mace_serial)];
334 
335 	volatile unsigned char rtc[0x10000];
336 };
337 
338 struct sgi_mace {
339 	char _reserved[0x80000];
340 
341 	struct mace_pci pci;
342 	char _pad0[0x80000 - sizeof(struct mace_pci)];
343 
344 	struct mace_video video_in1;
345 	char _pad1[0x80000 - sizeof(struct mace_video)];
346 
347 	struct mace_video video_in2;
348 	char _pad2[0x80000 - sizeof(struct mace_video)];
349 
350 	struct mace_video video_out;
351 	char _pad3[0x80000 - sizeof(struct mace_video)];
352 
353 	struct mace_ethernet eth;
354 	char _pad4[0x80000 - sizeof(struct mace_ethernet)];
355 
356 	struct mace_perif perif;
357 	char _pad5[0x80000 - sizeof(struct mace_perif)];
358 
359 	struct mace_isa isa;
360 	char _pad6[0x80000 - sizeof(struct mace_isa)];
361 };
362 
363 extern struct sgi_mace __iomem *mace;
364 
365 #endif /* __ASM_MACE_H__ */
366