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Searched refs:cntl (Results 1 – 25 of 42) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c124 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
129 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
961 struct bp_transmitter_control cntl = { 0 }; in dce110_link_encoder_hw_init() local
964 cntl.action = TRANSMITTER_CONTROL_INIT; in dce110_link_encoder_hw_init()
965 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_hw_init()
966 cntl.transmitter = enc110->base.transmitter; in dce110_link_encoder_hw_init()
967 cntl.connector_obj_id = enc110->base.connector; in dce110_link_encoder_hw_init()
968 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_link_encoder_hw_init()
969 cntl.coherent = false; in dce110_link_encoder_hw_init()
970 cntl.hpd_sel = enc110->base.hpd_source; in dce110_link_encoder_hw_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c106 struct bp_encoder_control *cntl);
110 struct bp_encoder_control *cntl);
114 struct bp_encoder_control *cntl);
143 struct bp_encoder_control *cntl);
146 struct bp_encoder_control *cntl);
149 struct bp_encoder_control *cntl);
170 struct bp_encoder_control *cntl) in encoder_control_dig_v1() argument
175 if (cntl != NULL) in encoder_control_dig_v1()
176 switch (cntl->engine_id) { in encoder_control_dig_v1()
180 cmd_tbl->encoder_control_dig1(bp, cntl); in encoder_control_dig_v1()
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H A Dcommand_table2.c88 struct bp_encoder_control *cntl);
92 struct bp_encoder_control *cntl);
131 struct bp_encoder_control *cntl) in encoder_control_digx_v1_5() argument
136 params.digid = (uint8_t)(cntl->engine_id); in encoder_control_digx_v1_5()
137 params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action); in encoder_control_digx_v1_5()
139 params.pclk_10khz = cntl->pixel_clock / 10; in encoder_control_digx_v1_5()
142 cntl->signal, in encoder_control_digx_v1_5()
143 cntl->enable_dp_audio)); in encoder_control_digx_v1_5()
144 params.lanenum = (uint8_t)(cntl->lanes_number); in encoder_control_digx_v1_5()
146 switch (cntl->color_depth) { in encoder_control_digx_v1_5()
[all …]
H A Dcommand_table.h87 struct bp_external_encoder_control *cntl);
H A Dcommand_table2.h87 struct bp_external_encoder_control *cntl);
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_link_encoder.c95 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
832 struct bp_transmitter_control cntl = { 0 }; in dcn10_link_encoder_hw_init() local
835 cntl.action = TRANSMITTER_CONTROL_INIT; in dcn10_link_encoder_hw_init()
836 cntl.engine_id = ENGINE_ID_UNKNOWN; in dcn10_link_encoder_hw_init()
837 cntl.transmitter = enc10->base.transmitter; in dcn10_link_encoder_hw_init()
838 cntl.connector_obj_id = enc10->base.connector; in dcn10_link_encoder_hw_init()
839 cntl.lanes_number = LANE_COUNT_FOUR; in dcn10_link_encoder_hw_init()
840 cntl.coherent = false; in dcn10_link_encoder_hw_init()
841 cntl.hpd_sel = enc10->base.hpd_source; in dcn10_link_encoder_hw_init()
[all …]
/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c132 u32 cntl; in pl111_display_enable() local
243 cntl = CNTL_LCDEN | CNTL_LCDMONO8; in pl111_display_enable()
246 cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); in pl111_display_enable()
250 cntl |= CNTL_ST_CDWID_24; in pl111_display_enable()
262 cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR; in pl111_display_enable()
267 cntl |= CNTL_ST_LCDBPP24_PACKED; in pl111_display_enable()
272 cntl |= CNTL_LCDBPP24 | CNTL_BGR; in pl111_display_enable()
274 cntl |= CNTL_LCDBPP24; in pl111_display_enable()
279 cntl |= CNTL_LCDBPP24; in pl111_display_enable()
281 cntl |= CNTL_LCDBPP24 | CNTL_BGR; in pl111_display_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
H A Ddcn31_hpo_dp_link_encoder.c496 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
501 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
514 struct bp_transmitter_control cntl = { 0 }; in dcn31_hpo_dp_link_enc_enable_dp_output() local
524 cntl.action = TRANSMITTER_CONTROL_ENABLE; in dcn31_hpo_dp_link_enc_enable_dp_output()
525 cntl.engine_id = ENGINE_ID_UNKNOWN; in dcn31_hpo_dp_link_enc_enable_dp_output()
526 cntl.transmitter = enc3->base.transmitter; in dcn31_hpo_dp_link_enc_enable_dp_output()
528 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; in dcn31_hpo_dp_link_enc_enable_dp_output()
529 cntl.lanes_number = link_settings->lane_count; in dcn31_hpo_dp_link_enc_enable_dp_output()
530 cntl.hpd_sel = enc3->base.hpd_source; in dcn31_hpo_dp_link_enc_enable_dp_output()
531 cntl.pixel_clock = link_settings->link_rate * 1000; in dcn31_hpo_dp_link_enc_enable_dp_output()
[all …]
/linux/arch/arm/mach-omap1/
H A Dtime.c65 u32 cntl; /* CNTL_TIMER, R/W */ member
84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
107 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
H A Dmtd-xip.h21 u32 cntl; /* CNTL_TIMER, R/W */ member
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.c71 struct bp_encoder_control cntl = {0}; in enc32_stream_encoder_dvi_set_stream_attribute() local
73 cntl.action = ENCODER_CONTROL_SETUP; in enc32_stream_encoder_dvi_set_stream_attribute()
74 cntl.engine_id = enc1->base.id; in enc32_stream_encoder_dvi_set_stream_attribute()
75 cntl.signal = is_dual_link ? in enc32_stream_encoder_dvi_set_stream_attribute()
77 cntl.enable_dp_audio = false; in enc32_stream_encoder_dvi_set_stream_attribute()
78 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; in enc32_stream_encoder_dvi_set_stream_attribute()
79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc32_stream_encoder_dvi_set_stream_attribute()
82 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc32_stream_encoder_dvi_set_stream_attribute()
112 struct bp_encoder_control cntl = {0}; in enc32_stream_encoder_hdmi_set_stream_attribute() local
114 cntl.action = ENCODER_CONTROL_SETUP; in enc32_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.c59 struct bp_encoder_control cntl = {0}; in enc35_stream_encoder_dvi_set_stream_attribute() local
61 cntl.action = ENCODER_CONTROL_SETUP; in enc35_stream_encoder_dvi_set_stream_attribute()
62 cntl.engine_id = enc1->base.id; in enc35_stream_encoder_dvi_set_stream_attribute()
63 cntl.signal = is_dual_link ? in enc35_stream_encoder_dvi_set_stream_attribute()
65 cntl.enable_dp_audio = false; in enc35_stream_encoder_dvi_set_stream_attribute()
66 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; in enc35_stream_encoder_dvi_set_stream_attribute()
67 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc35_stream_encoder_dvi_set_stream_attribute()
70 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc35_stream_encoder_dvi_set_stream_attribute()
99 struct bp_encoder_control cntl = {0}; in enc35_stream_encoder_hdmi_set_stream_attribute() local
101 cntl.action = ENCODER_CONTROL_SETUP; in enc35_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.c113 struct bp_encoder_control cntl = {0}; in enc314_stream_encoder_dvi_set_stream_attribute() local
115 cntl.action = ENCODER_CONTROL_SETUP; in enc314_stream_encoder_dvi_set_stream_attribute()
116 cntl.engine_id = enc1->base.id; in enc314_stream_encoder_dvi_set_stream_attribute()
117 cntl.signal = is_dual_link ? in enc314_stream_encoder_dvi_set_stream_attribute()
119 cntl.enable_dp_audio = false; in enc314_stream_encoder_dvi_set_stream_attribute()
120 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; in enc314_stream_encoder_dvi_set_stream_attribute()
121 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc314_stream_encoder_dvi_set_stream_attribute()
124 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc314_stream_encoder_dvi_set_stream_attribute()
154 struct bp_encoder_control cntl = {0}; in enc314_stream_encoder_hdmi_set_stream_attribute() local
156 cntl.action = ENCODER_CONTROL_SETUP; in enc314_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cursor.c206 u32 cntl = 0; in i845_cursor_ctl_crtc() local
209 cntl |= CURSOR_PIPE_GAMMA_ENABLE; in i845_cursor_ctl_crtc()
211 return cntl; in i845_cursor_ctl_crtc()
284 u32 cntl = 0, base = 0, pos = 0, size = 0; in i845_cursor_update_arm() local
290 cntl = plane_state->ctl | in i845_cursor_update_arm()
304 plane->cursor.cntl != cntl) { in i845_cursor_update_arm()
309 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); in i845_cursor_update_arm()
313 plane->cursor.cntl = cntl; in i845_cursor_update_arm()
382 u32 cntl = 0; in i9xx_cursor_ctl_crtc() local
385 return cntl; in i9xx_cursor_ctl_crtc()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce100/
H A Ddce100_hwseq.c79 enum bp_pipe_control_action cntl; in dce100_enable_display_power_gating() local
83 cntl = ASIC_PIPE_INIT; in dce100_enable_display_power_gating()
85 cntl = ASIC_PIPE_ENABLE; in dce100_enable_display_power_gating()
87 cntl = ASIC_PIPE_DISABLE; in dce100_enable_display_power_gating()
92 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c120 enum bp_pipe_control_action cntl; in dce112_enable_display_power_gating() local
124 cntl = ASIC_PIPE_INIT; in dce112_enable_display_power_gating()
126 cntl = ASIC_PIPE_ENABLE; in dce112_enable_display_power_gating()
128 cntl = ASIC_PIPE_DISABLE; in dce112_enable_display_power_gating()
133 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_stream_encoder.c536 struct bp_encoder_control cntl = {0}; in enc3_stream_encoder_dvi_set_stream_attribute() local
538 cntl.action = ENCODER_CONTROL_SETUP; in enc3_stream_encoder_dvi_set_stream_attribute()
539 cntl.engine_id = enc1->base.id; in enc3_stream_encoder_dvi_set_stream_attribute()
540 cntl.signal = is_dual_link ? in enc3_stream_encoder_dvi_set_stream_attribute()
542 cntl.enable_dp_audio = false; in enc3_stream_encoder_dvi_set_stream_attribute()
543 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; in enc3_stream_encoder_dvi_set_stream_attribute()
544 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc3_stream_encoder_dvi_set_stream_attribute()
547 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc3_stream_encoder_dvi_set_stream_attribute()
583 struct bp_encoder_control cntl = {0}; in enc3_stream_encoder_hdmi_set_stream_attribute() local
585 cntl.action = ENCODER_CONTROL_SETUP; in enc3_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce120/
H A Ddce120_hwseq.c159 enum bp_pipe_control_action cntl; in dce120_enable_display_power_gating()
163 cntl = ASIC_PIPE_INIT; in dce120_enable_display_power_gating()
165 cntl = ASIC_PIPE_ENABLE; in dce120_enable_display_power_gating()
167 cntl = ASIC_PIPE_DISABLE; in dce120_enable_display_power_gating()
172 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating()
/linux/drivers/iio/accel/
H A Dkionix-kx022a.c466 ret = regmap_set_bits(data->regmap, data->chip_info->cntl, in __kx022a_turn_on_off()
469 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl, in __kx022a_turn_on_off()
571 ret = regmap_update_bits(data->regmap, data->chip_info->cntl, in kx022a_write_raw()
651 ret = regmap_read(data->regmap, data->chip_info->cntl, &regval); in kx022a_read_raw()
895 return regmap_set_bits(data->regmap, data->chip_info->cntl, in kx022a_set_drdy_irq()
898 return regmap_clear_bits(data->regmap, data->chip_info->cntl, in kx022a_set_drdy_irq()
1166 .cntl = KX022A_REG_CNTL,
1194 .cntl = KX132_REG_CNTL,
1223 .cntl = KX132_REG_CNTL,
1259 .cntl = KX022A_REG_CNTL,
[all …]
/linux/arch/arm/mach-footbridge/
H A Ddc21285.c182 unsigned int cntl; in dc21285_serr_irq() local
188 cntl = *CSR_SA110_CNTL & 0xffffdf07; in dc21285_serr_irq()
189 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; in dc21285_serr_irq()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c212 enum bp_pipe_control_action cntl; in dce110_enable_display_power_gating() local
217 cntl = ASIC_PIPE_INIT; in dce110_enable_display_power_gating()
219 cntl = ASIC_PIPE_ENABLE; in dce110_enable_display_power_gating()
221 cntl = ASIC_PIPE_DISABLE; in dce110_enable_display_power_gating()
229 dcb, controller_id + 1, cntl); in dce110_enable_display_power_gating()
694 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
698 result = bios->funcs->transmitter_control(bios, cntl); in link_transmitter_control()
785 struct bp_transmitter_control cntl = { 0 }; in dce110_edp_power_control() local
862 cntl.action = power_up ? in dce110_edp_power_control()
865 cntl.transmitter = link->link_enc->transmitter; in dce110_edp_power_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_bios_types.h96 struct bp_encoder_control *cntl);
99 struct bp_transmitter_control *cntl);
/linux/arch/powerpc/platforms/cell/spufs/
H A Dcontext.c126 if (ctx->cntl) in spu_unmap_mappings()
127 unmap_mapping_range(ctx->cntl, 0, SPUFS_CNTL_MAP_SIZE, 1); in spu_unmap_mappings()
/linux/drivers/net/wireless/ath/ath6kl/
H A Dcommon.h65 u8 cntl; member
/linux/drivers/i2c/busses/
H A Di2c-ibm_iic.h27 u8 cntl; member

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