| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.c | 154 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
159 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
1060 struct bp_transmitter_control cntl = { 0 }; in dce110_link_encoder_hw_init() local
1063 cntl.action = TRANSMITTER_CONTROL_INIT; in dce110_link_encoder_hw_init()
1064 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_hw_init()
1065 cntl.transmitter = enc110->base.transmitter; in dce110_link_encoder_hw_init()
1066 cntl.connector_obj_id = enc110->base.connector; in dce110_link_encoder_hw_init()
1067 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_link_encoder_hw_init()
1068 cntl.coherent = false; in dce110_link_encoder_hw_init()
1069 cntl.hpd_sel = enc110->base.hpd_source; in dce110_link_encoder_hw_init()
[all …]
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| /linux/arch/arm/mach-omap1/ |
| H A D | time.c | 65 u32 cntl; /* CNTL_TIMER, R/W */ member
84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
107 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
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| H A D | mtd-xip.h | 21 u32 cntl; /* CNTL_TIMER, R/W */ member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/ |
| H A D | dce112_hwseq.c | 120 enum bp_pipe_control_action cntl; in dce112_enable_display_power_gating() local
124 cntl = ASIC_PIPE_INIT; in dce112_enable_display_power_gating()
126 cntl = ASIC_PIPE_ENABLE; in dce112_enable_display_power_gating()
128 cntl = ASIC_PIPE_DISABLE; in dce112_enable_display_power_gating()
133 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-ibm_iic.c | 90 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), in dump_iic_regs()
163 out_8(&iic->cntl, 0); in iic_dev_init()
383 out_8(&iic->cntl, CNTL_HMT); in iic_abort_xfer()
463 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT; in iic_xfer_bytes() local
465 cntl |= CNTL_RW; in iic_xfer_bytes()
470 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT); in iic_xfer_bytes()
472 if (!(cntl & CNTL_RW)) in iic_xfer_bytes()
484 out_8(&iic->cntl, cmd); in iic_xfer_bytes()
503 if (cntl & CNTL_RW) in iic_xfer_bytes()
520 out_8(&iic->cntl, CNTL_AMD); in iic_address()
[all …]
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| H A D | i2c-ibm_iic.h | 27 u8 cntl; member
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_bios_types.h | 99 struct bp_encoder_control *cntl);
102 struct bp_external_encoder_control *cntl);
109 struct bp_transmitter_control *cntl);
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| /linux/drivers/iio/accel/ |
| H A D | kionix-kx022a.c | 476 ret = regmap_set_bits(data->regmap, data->chip_info->cntl, in __kx022a_turn_on_off()
479 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl, in __kx022a_turn_on_off()
565 ret = regmap_update_bits(data->regmap, data->chip_info->cntl, in __kx022a_write_raw()
663 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val); in kx022a_read_raw()
907 return regmap_set_bits(data->regmap, data->chip_info->cntl, in kx022a_set_drdy_irq()
910 return regmap_clear_bits(data->regmap, data->chip_info->cntl, in kx022a_set_drdy_irq()
1178 .cntl = KX022A_REG_CNTL,
1206 .cntl = KX132_REG_CNTL,
1235 .cntl = KX132_REG_CNTL,
1271 .cntl = KX022A_REG_CNTL,
[all …]
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| /linux/arch/arm/mach-footbridge/ |
| H A D | dc21285.c | 182 unsigned int cntl; in dc21285_serr_irq() local
188 cntl = *CSR_SA110_CNTL & 0xffffdf07; in dc21285_serr_irq()
189 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; in dc21285_serr_irq()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 216 enum bp_pipe_control_action cntl; in dce110_enable_display_power_gating() local
221 cntl = ASIC_PIPE_INIT; in dce110_enable_display_power_gating()
223 cntl = ASIC_PIPE_ENABLE; in dce110_enable_display_power_gating()
225 cntl = ASIC_PIPE_DISABLE; in dce110_enable_display_power_gating()
233 dcb, controller_id + 1, cntl); in dce110_enable_display_power_gating()
757 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
761 result = bios->funcs->transmitter_control(bios, cntl); in link_transmitter_control()
829 struct bp_transmitter_control cntl = { 0 }; in dce110_edp_power_control() local
907 cntl.action = power_up ? in dce110_edp_power_control()
910 cntl.transmitter = link->link_enc->transmitter; in dce110_edp_power_control()
[all …]
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| /linux/arch/powerpc/platforms/cell/spufs/ |
| H A D | context.c | 126 if (ctx->cntl) in spu_unmap_mappings()
127 unmap_mapping_range(ctx->cntl, 0, SPUFS_CNTL_MAP_SIZE, 1); in spu_unmap_mappings()
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| H A D | spufs.h | 73 struct address_space *cntl; /* 'control' area mappings. */ member
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| H A D | file.c | 430 ctx->cntl = inode->i_mapping; in spufs_cntl_open()
446 ctx->cntl = NULL; in spufs_cntl_release()
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| /linux/drivers/net/wireless/ath/ath6kl/ |
| H A D | common.h | 65 u8 cntl; member
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| /linux/drivers/gpu/drm/amd/display/dc/bios/ |
| H A D | command_table2.h | 87 struct bp_external_encoder_control *cntl);
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| H A D | command_table.h | 93 struct bp_external_encoder_control *cntl);
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| H A D | bios_parser.c | 733 struct bp_transmitter_control *cntl) in bios_parser_transmitter_control() argument
740 return bp->cmd_tbl.transmitter_control(bp, cntl); in bios_parser_transmitter_control()
757 struct bp_encoder_control *cntl) in bios_parser_encoder_control() argument
761 if (cntl->engine_id == ENGINE_ID_DACA) { in bios_parser_encoder_control()
766 bp, cntl->action, in bios_parser_encoder_control()
767 cntl->pixel_clock, ATOM_DAC1_PS2); in bios_parser_encoder_control()
768 } else if (cntl->engine_id == ENGINE_ID_DACB) { in bios_parser_encoder_control()
773 bp, cntl->action, in bios_parser_encoder_control()
774 cntl->pixel_clock, ATOM_DAC1_PS2); in bios_parser_encoder_control()
780 return bp->cmd_tbl.dig_encoder_control(bp, cntl); in bios_parser_encoder_control()
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| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx_gpu.h | 112 uint32_t cntl; member
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| H A D | a8xx_gpu.c | 239 u32 cntl, final_cfg; in a8xx_set_cp_protect() local
242 cntl = A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN | in a8xx_set_cp_protect()
251 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); in a8xx_set_cp_protect()
252 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); in a8xx_set_cp_protect()
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| H A D | a5xx_preempt.c | 285 ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE; in preempt_init_ring()
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| /linux/drivers/scsi/ |
| H A D | advansys.c | 249 uchar cntl; member
293 uchar cntl; member
345 uchar cntl; member
591 ushort cntl; member
1735 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ member
2574 q->cntl, (ulong)le32_to_cpu(q->data_addr)); in asc_prt_adv_scsi_req_q()
2878 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); in asc_prt_asc_board_eeprom()
6138 scsiq->cntl = 0; in AdvISR()
6639 scsiq->cntl = (uchar)_val; in _AscCopyLramScsiDoneQ()
6802 if ((scsiq->cntl & QC_SG_HEAD) != 0) { in AscIsrQDone()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | kv_dpm.h | 59 u32 cntl; member
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_dpm.h | 85 u32 cntl; member
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| H A D | kv_dpm.c | 393 WREG32_SMC(local_cac_reg->cntl, data);
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_types.h | 1590 u32 base, cntl, size; member
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