| /linux/arch/arm/mach-omap1/ |
| H A D | time.c | 65 u32 cntl; /* CNTL_TIMER, R/W */ member
84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
107 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
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| H A D | mtd-xip.h | 21 u32 cntl; /* CNTL_TIMER, R/W */ member
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cursor.c | 200 u32 cntl = 0; in i845_cursor_ctl_crtc() local
203 cntl |= CURSOR_PIPE_GAMMA_ENABLE; in i845_cursor_ctl_crtc()
205 return cntl; in i845_cursor_ctl_crtc()
280 u32 cntl = 0, base = 0, pos = 0, size = 0; in i845_cursor_update_arm() local
286 cntl = plane_state->ctl | in i845_cursor_update_arm()
300 plane->cursor.cntl != cntl) { in i845_cursor_update_arm()
305 intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); in i845_cursor_update_arm()
309 plane->cursor.cntl = cntl; in i845_cursor_update_arm()
383 u32 cntl = 0; in i9xx_cursor_ctl_crtc() local
386 return cntl; in i9xx_cursor_ctl_crtc()
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| H A D | intel_display_types.h | 1607 u32 base, cntl, size; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/ |
| H A D | dce112_hwseq.c | 120 enum bp_pipe_control_action cntl; in dce112_enable_display_power_gating() local
124 cntl = ASIC_PIPE_INIT; in dce112_enable_display_power_gating()
126 cntl = ASIC_PIPE_ENABLE; in dce112_enable_display_power_gating()
128 cntl = ASIC_PIPE_DISABLE; in dce112_enable_display_power_gating()
133 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.c | 554 struct bp_encoder_control cntl = {0}; in dce110_stream_encoder_hdmi_set_stream_attribute() local
556 cntl.action = ENCODER_CONTROL_SETUP; in dce110_stream_encoder_hdmi_set_stream_attribute()
557 cntl.engine_id = enc110->base.id; in dce110_stream_encoder_hdmi_set_stream_attribute()
558 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; in dce110_stream_encoder_hdmi_set_stream_attribute()
559 cntl.enable_dp_audio = enable_audio; in dce110_stream_encoder_hdmi_set_stream_attribute()
560 cntl.pixel_clock = actual_pix_clk_khz; in dce110_stream_encoder_hdmi_set_stream_attribute()
561 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_hdmi_set_stream_attribute()
562 cntl.color_depth = crtc_timing->display_color_depth; in dce110_stream_encoder_hdmi_set_stream_attribute()
565 enc110->base.bp, &cntl) != BP_RESULT_OK) in dce110_stream_encoder_hdmi_set_stream_attribute()
670 struct bp_encoder_control cntl = {0}; in dce110_stream_encoder_dvi_set_stream_attribute() local
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-ibm_iic.c | 90 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), in dump_iic_regs()
163 out_8(&iic->cntl, 0); in iic_dev_init()
383 out_8(&iic->cntl, CNTL_HMT); in iic_abort_xfer()
463 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT; in iic_xfer_bytes() local
465 cntl |= CNTL_RW; in iic_xfer_bytes()
470 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT); in iic_xfer_bytes()
472 if (!(cntl & CNTL_RW)) in iic_xfer_bytes()
484 out_8(&iic->cntl, cmd); in iic_xfer_bytes()
503 if (cntl & CNTL_RW) in iic_xfer_bytes()
520 out_8(&iic->cntl, CNTL_AMD); in iic_address()
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| H A D | i2c-ibm_iic.h | 27 u8 cntl; member
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| /linux/arch/arm/mach-footbridge/ |
| H A D | dc21285.c | 182 unsigned int cntl; in dc21285_serr_irq() local
188 cntl = *CSR_SA110_CNTL & 0xffffdf07; in dc21285_serr_irq()
189 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; in dc21285_serr_irq()
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| /linux/arch/powerpc/platforms/cell/spufs/ |
| H A D | context.c | 126 if (ctx->cntl) in spu_unmap_mappings()
127 unmap_mapping_range(ctx->cntl, 0, SPUFS_CNTL_MAP_SIZE, 1); in spu_unmap_mappings()
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| H A D | spufs.h | 73 struct address_space *cntl; /* 'control' area mappings. */ member
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| H A D | file.c | 432 ctx->cntl = inode->i_mapping; in spufs_cntl_open()
448 ctx->cntl = NULL; in spufs_cntl_release()
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| /linux/drivers/net/wireless/ath/ath6kl/ |
| H A D | common.h | 65 u8 cntl; member
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| H A D | wmi.c | 197 llc_hdr->cntl = 0x03; in ath6kl_wmi_dix_2_dot3()
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| /linux/drivers/gpu/drm/amd/display/dc/bios/ |
| H A D | command_table2.h | 87 struct bp_external_encoder_control *cntl);
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| H A D | command_table.h | 93 struct bp_external_encoder_control *cntl);
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| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx_gpu.h | 112 uint32_t cntl; member
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| H A D | a8xx_gpu.c | 239 u32 cntl, final_cfg; in a8xx_set_cp_protect() local
242 cntl = A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN | in a8xx_set_cp_protect()
251 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); in a8xx_set_cp_protect()
252 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); in a8xx_set_cp_protect()
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| H A D | a5xx_preempt.c | 285 ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE; in preempt_init_ring()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | kv_dpm.h | 59 u32 cntl; member
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_dpm.h | 85 u32 cntl; member
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 1568 u32 f32_cntl, freeze, cntl, stat1_reg; in sdma_v5_0_stop_queue() local
1607 cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_stop_queue()
1608 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); in sdma_v5_0_stop_queue()
1609 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); in sdma_v5_0_stop_queue()
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| H A D | sdma_v5_2.c | 1479 u32 f32_cntl, freeze, cntl, stat1_reg; in sdma_v5_2_stop_queue() local
1519 cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_stop_queue()
1520 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); in sdma_v5_2_stop_queue()
1521 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); in sdma_v5_2_stop_queue()
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