1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2024 Marvell.
5 *
6 */
7
8 #include "otx2_common.h"
9 #include "otx2_reg.h"
10 #include "otx2_struct.h"
11 #include "cn10k.h"
12
13 /* CN20K mbox AF => PFx irq handler */
cn20k_pfaf_mbox_intr_handler(int irq,void * pf_irq)14 irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq)
15 {
16 struct otx2_nic *pf = pf_irq;
17 struct mbox *mw = &pf->mbox;
18 struct otx2_mbox_dev *mdev;
19 struct otx2_mbox *mbox;
20 struct mbox_hdr *hdr;
21 u64 pf_trig_val;
22
23 pf_trig_val = otx2_read64(pf, RVU_PF_INT) & 0x3ULL;
24
25 /* Clear the IRQ */
26 otx2_write64(pf, RVU_PF_INT, pf_trig_val);
27
28 if (pf_trig_val & BIT_ULL(0)) {
29 mbox = &mw->mbox_up;
30 mdev = &mbox->dev[0];
31 otx2_sync_mbox_bbuf(mbox, 0);
32
33 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
34 if (hdr->num_msgs)
35 queue_work(pf->mbox_wq, &mw->mbox_up_wrk);
36
37 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF",
38 BIT_ULL(0));
39 }
40
41 if (pf_trig_val & BIT_ULL(1)) {
42 mbox = &mw->mbox;
43 mdev = &mbox->dev[0];
44 otx2_sync_mbox_bbuf(mbox, 0);
45
46 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
47 if (hdr->num_msgs)
48 queue_work(pf->mbox_wq, &mw->mbox_wrk);
49 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF",
50 BIT_ULL(1));
51 }
52
53 return IRQ_HANDLED;
54 }
55
cn20k_vfaf_mbox_intr_handler(int irq,void * vf_irq)56 irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq)
57 {
58 struct otx2_nic *vf = vf_irq;
59 struct otx2_mbox_dev *mdev;
60 struct otx2_mbox *mbox;
61 struct mbox_hdr *hdr;
62 u64 vf_trig_val;
63
64 vf_trig_val = otx2_read64(vf, RVU_VF_INT) & 0x3ULL;
65 /* Clear the IRQ */
66 otx2_write64(vf, RVU_VF_INT, vf_trig_val);
67
68 /* Read latest mbox data */
69 smp_rmb();
70
71 if (vf_trig_val & BIT_ULL(1)) {
72 /* Check for PF => VF response messages */
73 mbox = &vf->mbox.mbox;
74 mdev = &mbox->dev[0];
75 otx2_sync_mbox_bbuf(mbox, 0);
76
77 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
78 if (hdr->num_msgs)
79 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
80
81 trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF0 to VF",
82 BIT_ULL(1));
83 }
84
85 if (vf_trig_val & BIT_ULL(0)) {
86 /* Check for PF => VF notification messages */
87 mbox = &vf->mbox.mbox_up;
88 mdev = &mbox->dev[0];
89 otx2_sync_mbox_bbuf(mbox, 0);
90
91 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
92 if (hdr->num_msgs)
93 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
94
95 trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF0 to VF",
96 BIT_ULL(0));
97 }
98
99 return IRQ_HANDLED;
100 }
101
cn20k_enable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)102 void cn20k_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
103 {
104 /* Clear PF <=> VF mailbox IRQ */
105 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull);
106 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull);
107 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull);
108 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull);
109
110 /* Enable PF <=> VF mailbox IRQ */
111 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(0), INTR_MASK(numvfs));
112 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(0), INTR_MASK(numvfs));
113 if (numvfs > 64) {
114 numvfs -= 64;
115 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(1),
116 INTR_MASK(numvfs));
117 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(1),
118 INTR_MASK(numvfs));
119 }
120 }
121
cn20k_disable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)122 void cn20k_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
123 {
124 int vector, intr_vec, vec = 0;
125
126 /* Disable PF <=> VF mailbox IRQ */
127 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(0), ~0ull);
128 otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(1), ~0ull);
129 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(0), ~0ull);
130 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(1), ~0ull);
131
132 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull);
133 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull);
134
135 if (numvfs > 64) {
136 otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull);
137 otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull);
138 }
139
140 for (intr_vec = RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=
141 RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) {
142 vector = pci_irq_vector(pf->pdev, intr_vec);
143 free_irq(vector, pf->hw.pfvf_irq_devid[vec]);
144 }
145 }
146
cn20k_pfvf_mbox_intr_handler(int irq,void * pf_irq)147 irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq)
148 {
149 struct pf_irq_data *irq_data = pf_irq;
150 struct otx2_nic *pf = irq_data->pf;
151 struct mbox *mbox;
152 u64 intr;
153
154 /* Sync with mbox memory region */
155 rmb();
156
157 /* Clear interrupts */
158 intr = otx2_read64(pf, irq_data->intr_status);
159 otx2_write64(pf, irq_data->intr_status, intr);
160 mbox = pf->mbox_pfvf;
161
162 if (intr)
163 trace_otx2_msg_interrupt(pf->pdev, "VF(s) to PF", intr);
164
165 irq_data->pf_queue_work_hdlr(mbox, pf->mbox_pfvf_wq, irq_data->start,
166 irq_data->mdevs, intr);
167
168 return IRQ_HANDLED;
169 }
170
cn20k_register_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)171 int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
172 {
173 struct otx2_hw *hw = &pf->hw;
174 struct pf_irq_data *irq_data;
175 int intr_vec, ret, vec = 0;
176 char *irq_name;
177
178 /* irq data for 4 PF intr vectors */
179 irq_data = devm_kcalloc(pf->dev, 4,
180 sizeof(struct pf_irq_data), GFP_KERNEL);
181 if (!irq_data)
182 return -ENOMEM;
183
184 for (intr_vec = RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=
185 RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) {
186 switch (intr_vec) {
187 case RVU_MBOX_PF_INT_VEC_VFPF_MBOX0:
188 irq_data[vec].intr_status =
189 RVU_MBOX_PF_VFPF_INTX(0);
190 irq_data[vec].start = 0;
191 irq_data[vec].mdevs = 64;
192 break;
193 case RVU_MBOX_PF_INT_VEC_VFPF_MBOX1:
194 irq_data[vec].intr_status =
195 RVU_MBOX_PF_VFPF_INTX(1);
196 irq_data[vec].start = 64;
197 irq_data[vec].mdevs = 96;
198 break;
199 case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0:
200 irq_data[vec].intr_status =
201 RVU_MBOX_PF_VFPF1_INTX(0);
202 irq_data[vec].start = 0;
203 irq_data[vec].mdevs = 64;
204 break;
205 case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1:
206 irq_data[vec].intr_status =
207 RVU_MBOX_PF_VFPF1_INTX(1);
208 irq_data[vec].start = 64;
209 irq_data[vec].mdevs = 96;
210 break;
211 }
212 irq_data[vec].pf_queue_work_hdlr = otx2_queue_vf_work;
213 irq_data[vec].vec_num = intr_vec;
214 irq_data[vec].pf = pf;
215
216 /* Register mailbox interrupt handler */
217 irq_name = &hw->irq_name[intr_vec * NAME_SIZE];
218 if (pf->pcifunc)
219 snprintf(irq_name, NAME_SIZE,
220 "RVUPF%d_VF%d Mbox%d", rvu_get_pf(pf->pdev,
221 pf->pcifunc), vec / 2, vec % 2);
222 else
223 snprintf(irq_name, NAME_SIZE, "RVUPF_VF%d Mbox%d",
224 vec / 2, vec % 2);
225
226 hw->pfvf_irq_devid[vec] = &irq_data[vec];
227 ret = request_irq(pci_irq_vector(pf->pdev, intr_vec),
228 pf->hw_ops->pfvf_mbox_intr_handler, 0,
229 irq_name,
230 &irq_data[vec]);
231 if (ret) {
232 dev_err(pf->dev,
233 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
234 return ret;
235 }
236 }
237
238 cn20k_enable_pfvf_mbox_intr(pf, numvfs);
239
240 return 0;
241 }
242
243 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */
244
cn20k_aura_bpid_idx(struct otx2_nic * pfvf,int aura_id)245 static u8 cn20k_aura_bpid_idx(struct otx2_nic *pfvf, int aura_id)
246 {
247 #ifdef CONFIG_DCB
248 return pfvf->queue_to_pfc_map[aura_id];
249 #else
250 return 0;
251 #endif
252 }
253
cn20k_tc_get_entry_index(struct otx2_flow_config * flow_cfg,struct otx2_tc_flow * node)254 static int cn20k_tc_get_entry_index(struct otx2_flow_config *flow_cfg,
255 struct otx2_tc_flow *node)
256 {
257 struct otx2_tc_flow *tmp;
258 int index = 0;
259
260 list_for_each_entry(tmp, &flow_cfg->flow_list_tc, list) {
261 if (tmp == node)
262 return index;
263
264 index++;
265 }
266
267 return -1;
268 }
269
cn20k_tc_free_mcam_entry(struct otx2_nic * nic,u16 entry)270 int cn20k_tc_free_mcam_entry(struct otx2_nic *nic, u16 entry)
271 {
272 struct npc_mcam_free_entry_req *req;
273 int err;
274
275 mutex_lock(&nic->mbox.lock);
276 req = otx2_mbox_alloc_msg_npc_mcam_free_entry(&nic->mbox);
277 if (!req) {
278 mutex_unlock(&nic->mbox.lock);
279 return -ENOMEM;
280 }
281
282 req->entry = entry;
283 /* Send message to AF to free MCAM entries */
284 err = otx2_sync_mbox_msg(&nic->mbox);
285 if (err) {
286 mutex_unlock(&nic->mbox.lock);
287 return err;
288 }
289
290 mutex_unlock(&nic->mbox.lock);
291
292 return 0;
293 }
294
cn20k_tc_check_entry_shiftable(struct otx2_nic * nic,struct otx2_flow_config * flow_cfg,struct otx2_tc_flow * node,int index,bool error)295 static bool cn20k_tc_check_entry_shiftable(struct otx2_nic *nic,
296 struct otx2_flow_config *flow_cfg,
297 struct otx2_tc_flow *node, int index,
298 bool error)
299 {
300 struct otx2_tc_flow *first, *tmp, *n;
301 u32 prio = 0;
302 int i = 0;
303 u8 type;
304
305 first = list_first_entry(&flow_cfg->flow_list_tc, struct otx2_tc_flow,
306 list);
307 type = first->kw_type;
308
309 /* Check all the nodes from start to given index (including index) has
310 * same type i.e, either X2 or X4
311 */
312 list_for_each_entry_safe(tmp, n, &flow_cfg->flow_list_tc, list) {
313 if (i > index)
314 break;
315
316 if (type != tmp->kw_type) {
317 /* List has both X2 and X4 entries so entries cannot be
318 * shifted to save MCAM space.
319 */
320 if (error)
321 dev_err(nic->dev, "Rule %d cannot be shifted to %d\n",
322 tmp->prio, prio);
323 return false;
324 }
325
326 type = tmp->kw_type;
327 prio = tmp->prio;
328 i++;
329 }
330
331 return true;
332 }
333
cn20k_tc_update_mcam_table_del_req(struct otx2_nic * nic,struct otx2_flow_config * flow_cfg,struct otx2_tc_flow * node)334 void cn20k_tc_update_mcam_table_del_req(struct otx2_nic *nic,
335 struct otx2_flow_config *flow_cfg,
336 struct otx2_tc_flow *node)
337 {
338 struct otx2_tc_flow *first, *tmp, *n;
339 int i = 0, index;
340 u16 cntr_val = 0;
341 u16 entry;
342
343 index = cn20k_tc_get_entry_index(flow_cfg, node);
344 if (index < 0) {
345 netdev_dbg(nic->netdev, "Could not find node\n");
346 return;
347 }
348
349 first = list_first_entry(&flow_cfg->flow_list_tc, struct otx2_tc_flow,
350 list);
351 entry = first->entry;
352
353 /* If entries cannot be shifted then delete given entry
354 * and free it to AF too.
355 */
356 if (!cn20k_tc_check_entry_shiftable(nic, flow_cfg, node,
357 index, false)) {
358 list_del(&node->list);
359 entry = node->entry;
360 goto free_mcam_entry;
361 }
362
363 /* Find and delete the entry from the list and re-install
364 * all the entries from beginning to the index of the
365 * deleted entry to higher mcam indexes.
366 */
367 list_for_each_entry_safe(tmp, n, &flow_cfg->flow_list_tc, list) {
368 if (node == tmp) {
369 list_del(&tmp->list);
370 break;
371 }
372
373 otx2_del_mcam_flow_entry(nic, tmp->entry, &cntr_val);
374 tmp->entry = (list_next_entry(tmp, list))->entry;
375 tmp->req.entry = tmp->entry;
376 tmp->req.cntr_val = cntr_val;
377 }
378
379 list_for_each_entry_safe(tmp, n, &flow_cfg->flow_list_tc, list) {
380 if (i == index)
381 break;
382
383 otx2_add_mcam_flow_entry(nic, &tmp->req);
384 i++;
385 }
386
387 free_mcam_entry:
388 if (cn20k_tc_free_mcam_entry(nic, entry))
389 netdev_err(nic->netdev, "Freeing entry %d to AF failed\n",
390 entry);
391 }
392
cn20k_tc_update_mcam_table_add_req(struct otx2_nic * nic,struct otx2_flow_config * flow_cfg,struct otx2_tc_flow * node)393 int cn20k_tc_update_mcam_table_add_req(struct otx2_nic *nic,
394 struct otx2_flow_config *flow_cfg,
395 struct otx2_tc_flow *node)
396 {
397 struct otx2_tc_flow *tmp;
398 u16 cntr_val = 0;
399 int list_idx, i;
400 int entry, prev;
401
402 /* Find the index of the entry(list_idx) whose priority
403 * is greater than the new entry and re-install all
404 * the entries from beginning to list_idx to higher
405 * mcam indexes.
406 */
407 list_idx = otx2_tc_add_to_flow_list(flow_cfg, node);
408 entry = node->entry;
409 if (!cn20k_tc_check_entry_shiftable(nic, flow_cfg, node,
410 list_idx, true))
411 /* Due to mix of X2 and X4, entries cannot be shifted.
412 * In this case free the entry allocated for this rule.
413 */
414 return -EINVAL;
415
416 for (i = 0; i < list_idx; i++) {
417 tmp = otx2_tc_get_entry_by_index(flow_cfg, i);
418 if (!tmp)
419 return -ENOMEM;
420
421 otx2_del_mcam_flow_entry(nic, tmp->entry, &cntr_val);
422 prev = tmp->entry;
423 tmp->entry = entry;
424 tmp->req.entry = tmp->entry;
425 tmp->req.cntr_val = cntr_val;
426 otx2_add_mcam_flow_entry(nic, &tmp->req);
427 entry = prev;
428 }
429
430 return entry;
431 }
432
433 #define MAX_TC_HW_PRIORITY 125
434 #define MAX_TC_VF_PRIORITY 126
435 #define MAX_TC_PF_PRIORITY 127
436
__cn20k_tc_alloc_entry(struct otx2_nic * nic,struct npc_install_flow_req * flow_req,u16 * entry,u8 * type,u32 tc_priority,bool hw_priority)437 static int __cn20k_tc_alloc_entry(struct otx2_nic *nic,
438 struct npc_install_flow_req *flow_req,
439 u16 *entry, u8 *type,
440 u32 tc_priority, bool hw_priority)
441 {
442 struct otx2_flow_config *flow_cfg = nic->flow_cfg;
443 struct npc_install_flow_req *req;
444 struct npc_install_flow_rsp *rsp;
445 struct otx2_tc_flow *tmp;
446 int ret = 0;
447
448 req = otx2_mbox_alloc_msg_npc_install_flow(&nic->mbox);
449 if (!req)
450 return -ENOMEM;
451
452 memcpy(&flow_req->hdr, &req->hdr, sizeof(struct mbox_msghdr));
453 memcpy(req, flow_req, sizeof(struct npc_install_flow_req));
454 req->alloc_entry = 1;
455
456 /* Allocate very least priority for first rule */
457 if (hw_priority || list_empty(&flow_cfg->flow_list_tc)) {
458 req->ref_prio = NPC_MCAM_LEAST_PRIO;
459 } else {
460 req->ref_prio = NPC_MCAM_HIGHER_PRIO;
461 tmp = list_first_entry(&flow_cfg->flow_list_tc,
462 struct otx2_tc_flow, list);
463 req->ref_entry = tmp->entry;
464 }
465
466 ret = otx2_sync_mbox_msg(&nic->mbox);
467 if (ret)
468 return ret;
469
470 rsp = (struct npc_install_flow_rsp *)otx2_mbox_get_rsp(&nic->mbox.mbox,
471 0, &req->hdr);
472 if (IS_ERR(rsp))
473 return -EFAULT;
474
475 if (entry)
476 *entry = rsp->entry;
477 if (type)
478 *type = rsp->kw_type;
479
480 return ret;
481 }
482
cn20k_tc_alloc_entry(struct otx2_nic * nic,struct flow_cls_offload * tc_flow_cmd,struct otx2_tc_flow * new_node,struct npc_install_flow_req * flow_req)483 int cn20k_tc_alloc_entry(struct otx2_nic *nic,
484 struct flow_cls_offload *tc_flow_cmd,
485 struct otx2_tc_flow *new_node,
486 struct npc_install_flow_req *flow_req)
487 {
488 bool hw_priority = false;
489 u16 entry_from_af;
490 u8 entry_type;
491 int ret;
492
493 if (is_otx2_vf(nic->pcifunc))
494 flow_req->hw_prio = MAX_TC_VF_PRIORITY;
495 else
496 flow_req->hw_prio = MAX_TC_PF_PRIORITY;
497
498 if (new_node->prio <= MAX_TC_HW_PRIORITY) {
499 flow_req->hw_prio = new_node->prio;
500 hw_priority = true;
501 }
502
503 mutex_lock(&nic->mbox.lock);
504
505 ret = __cn20k_tc_alloc_entry(nic, flow_req, &entry_from_af, &entry_type,
506 new_node->prio, hw_priority);
507 if (ret) {
508 mutex_unlock(&nic->mbox.lock);
509 return ret;
510 }
511
512 new_node->kw_type = entry_type;
513 new_node->entry = entry_from_af;
514
515 mutex_unlock(&nic->mbox.lock);
516
517 return 0;
518 }
519
cn20k_aura_aq_init(struct otx2_nic * pfvf,int aura_id,int pool_id,int numptrs)520 static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
521 int pool_id, int numptrs)
522 {
523 struct npa_cn20k_aq_enq_req *aq;
524 struct otx2_pool *pool;
525 u8 bpid_idx;
526 int err;
527
528 pool = &pfvf->qset.pool[pool_id];
529
530 /* Allocate memory for HW to update Aura count.
531 * Alloc one cache line, so that it fits all FC_STYPE modes.
532 */
533 if (!pool->fc_addr) {
534 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
535 if (err)
536 return err;
537 }
538
539 /* Initialize this aura's context via AF */
540 aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
541 if (!aq) {
542 /* Shared mbox memory buffer is full, flush it and retry */
543 err = otx2_sync_mbox_msg(&pfvf->mbox);
544 if (err)
545 return err;
546 aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
547 if (!aq)
548 return -ENOMEM;
549 }
550
551 aq->aura_id = aura_id;
552
553 /* Will be filled by AF with correct pool context address */
554 aq->aura.pool_addr = pool_id;
555 aq->aura.pool_caching = 1;
556 aq->aura.shift = ilog2(numptrs) - 8;
557 aq->aura.count = numptrs;
558 aq->aura.limit = numptrs;
559 aq->aura.avg_level = 255;
560 aq->aura.ena = 1;
561 aq->aura.fc_ena = 1;
562 aq->aura.fc_addr = pool->fc_addr->iova;
563 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
564
565 /* Enable backpressure for RQ aura */
566 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
567 aq->aura.bp_ena = 0;
568 /* If NIX1 LF is attached then specify NIX1_RX.
569 *
570 * Below NPA_AURA_S[BP_ENA] is set according to the
571 * NPA_BPINTF_E enumeration given as:
572 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
573 * NIX0_RX is 0x0 + 0*0x1 = 0
574 * NIX1_RX is 0x0 + 1*0x1 = 1
575 * But in HRM it is given that
576 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
577 * NIX-RX based on [BP] level. One bit per NIX-RX; index
578 * enumerated by NPA_BPINTF_E."
579 */
580 if (pfvf->nix_blkaddr == BLKADDR_NIX1)
581 aq->aura.bp_ena = 1;
582
583 bpid_idx = cn20k_aura_bpid_idx(pfvf, aura_id);
584 aq->aura.bpid = pfvf->bpid[bpid_idx];
585
586 /* Set backpressure level for RQ's Aura */
587 aq->aura.bp = RQ_BP_LVL_AURA;
588 }
589
590 /* Fill AQ info */
591 aq->ctype = NPA_AQ_CTYPE_AURA;
592 aq->op = NPA_AQ_INSTOP_INIT;
593
594 return 0;
595 }
596
cn20k_pool_aq_init(struct otx2_nic * pfvf,u16 pool_id,int stack_pages,int numptrs,int buf_size,int type)597 static int cn20k_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id,
598 int stack_pages, int numptrs, int buf_size,
599 int type)
600 {
601 struct page_pool_params pp_params = { 0 };
602 struct npa_cn20k_aq_enq_req *aq;
603 struct otx2_pool *pool;
604 int err, sz;
605
606 pool = &pfvf->qset.pool[pool_id];
607 /* Alloc memory for stack which is used to store buffer pointers */
608 err = qmem_alloc(pfvf->dev, &pool->stack,
609 stack_pages, pfvf->hw.stack_pg_bytes);
610 if (err)
611 return err;
612
613 pool->rbsize = buf_size;
614
615 /* Initialize this pool's context via AF */
616 aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
617 if (!aq) {
618 /* Shared mbox memory buffer is full, flush it and retry */
619 err = otx2_sync_mbox_msg(&pfvf->mbox);
620 if (err) {
621 qmem_free(pfvf->dev, pool->stack);
622 pool->stack = NULL;
623 return err;
624 }
625 aq = otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox);
626 if (!aq) {
627 qmem_free(pfvf->dev, pool->stack);
628 pool->stack = NULL;
629 return -ENOMEM;
630 }
631 }
632
633 aq->aura_id = pool_id;
634 aq->pool.stack_base = pool->stack->iova;
635 aq->pool.stack_caching = 1;
636 aq->pool.ena = 1;
637 aq->pool.buf_size = buf_size / 128;
638 aq->pool.stack_max_pages = stack_pages;
639 aq->pool.shift = ilog2(numptrs) - 8;
640 aq->pool.ptr_start = 0;
641 aq->pool.ptr_end = ~0ULL;
642
643 /* Fill AQ info */
644 aq->ctype = NPA_AQ_CTYPE_POOL;
645 aq->op = NPA_AQ_INSTOP_INIT;
646
647 if (type != AURA_NIX_RQ) {
648 pool->page_pool = NULL;
649 return 0;
650 }
651
652 sz = ALIGN(ALIGN(SKB_DATA_ALIGN(buf_size), OTX2_ALIGN), PAGE_SIZE);
653 pp_params.order = get_order(sz);
654 pp_params.flags = PP_FLAG_DMA_MAP;
655 pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs);
656 pp_params.nid = NUMA_NO_NODE;
657 pp_params.dev = pfvf->dev;
658 pp_params.dma_dir = DMA_FROM_DEVICE;
659 pool->page_pool = page_pool_create(&pp_params);
660 if (IS_ERR(pool->page_pool)) {
661 netdev_err(pfvf->netdev, "Creation of page pool failed\n");
662 return PTR_ERR(pool->page_pool);
663 }
664
665 return 0;
666 }
667
cn20k_sq_aq_init(void * dev,u16 qidx,u8 chan_offset,u16 sqb_aura)668 static int cn20k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura)
669 {
670 struct nix_cn20k_aq_enq_req *aq;
671 struct otx2_nic *pfvf = dev;
672
673 /* Get memory to put this msg */
674 aq = otx2_mbox_alloc_msg_nix_cn20k_aq_enq(&pfvf->mbox);
675 if (!aq)
676 return -ENOMEM;
677
678 aq->sq.cq = pfvf->hw.rx_queues + qidx;
679 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
680 aq->sq.cq_ena = 1;
681 aq->sq.ena = 1;
682 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
683 aq->sq.smq_rr_weight = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
684 aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset;
685 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
686 aq->sq.sqb_aura = sqb_aura;
687 aq->sq.sq_int_ena = NIX_SQINT_BITS;
688 aq->sq.qint_idx = 0;
689 /* Due pipelining impact minimum 2000 unused SQ CQE's
690 * need to maintain to avoid CQ overflow.
691 */
692 aq->sq.cq_limit = (SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt);
693
694 /* Fill AQ info */
695 aq->qidx = qidx;
696 aq->ctype = NIX_AQ_CTYPE_SQ;
697 aq->op = NIX_AQ_INSTOP_INIT;
698
699 return otx2_sync_mbox_msg(&pfvf->mbox);
700 }
701
702 static struct dev_hw_ops cn20k_hw_ops = {
703 .pfaf_mbox_intr_handler = cn20k_pfaf_mbox_intr_handler,
704 .vfaf_mbox_intr_handler = cn20k_vfaf_mbox_intr_handler,
705 .pfvf_mbox_intr_handler = cn20k_pfvf_mbox_intr_handler,
706 .sq_aq_init = cn20k_sq_aq_init,
707 .sqe_flush = cn10k_sqe_flush,
708 .aura_freeptr = cn10k_aura_freeptr,
709 .refill_pool_ptrs = cn10k_refill_pool_ptrs,
710 .aura_aq_init = cn20k_aura_aq_init,
711 .pool_aq_init = cn20k_pool_aq_init,
712 };
713
cn20k_init(struct otx2_nic * pfvf)714 void cn20k_init(struct otx2_nic *pfvf)
715 {
716 pfvf->hw_ops = &cn20k_hw_ops;
717 }
718 EXPORT_SYMBOL(cn20k_init);
719