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Searched refs:cmr (Results 1 – 5 of 5) sorted by relevance

/linux/mm/
H A Dcma_debug.c49 struct cma_memrange *cmr; in cma_maxchunk_get() local
57 cmr = &cma->ranges[r]; in cma_maxchunk_get()
58 bitmap_maxno = cma_bitmap_maxno(cma, cmr); in cma_maxchunk_get()
59 for_each_clear_bitrange(start, end, cmr->bitmap, bitmap_maxno) in cma_maxchunk_get()
166 struct cma_memrange *cmr; in cma_debugfs_add_one() local
180 cmr = &cma->ranges[r]; in cma_debugfs_add_one()
184 &cmr->base_pfn, &cma_debugfs_fops); in cma_debugfs_add_one()
185 cmr->dfs_bitmap.array = (u32 *)cmr->bitmap; in cma_debugfs_add_one()
186 cmr->dfs_bitmap.n_elements = in cma_debugfs_add_one()
187 DIV_ROUND_UP(cma_bitmap_maxno(cma, cmr), in cma_debugfs_add_one()
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H A Dcma.h78 struct cma_memrange *cmr) in cma_bitmap_maxno() argument
80 return cmr->count >> cma->order_per_bit; in cma_bitmap_maxno()
/linux/drivers/counter/
H A Dmicrochip-tcb-capture.c93 u32 bmr, cmr; in mchp_tc_count_function_write() local
96 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); in mchp_tc_count_function_write()
99 cmr &= ~ATMEL_TC_WAVE; in mchp_tc_count_function_write()
107 cmr |= ATMEL_TC_TIMER_CLOCK2; in mchp_tc_count_function_write()
109 cmr |= ATMEL_TC_TIMER_CLOCK1; in mchp_tc_count_function_write()
111 cmr |= ATMEL_TC_CMR_MASK; in mchp_tc_count_function_write()
112 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0); in mchp_tc_count_function_write()
125 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0; in mchp_tc_count_function_write()
133 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr); in mchp_tc_count_function_write()
141 ATMEL_TC_REG(priv->channel[1], CMR), cmr); in mchp_tc_count_function_write()
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H A D104-quad-8.c62 u8 cmr[QUAD8_NUM_COUNTERS]; member
326 switch (u8_get_bits(priv->cmr[id], QUADRATURE_MODE)) { in quad8_function_get()
402 ret = quad8_control_register_update(priv->map, priv->cmr, id, mode_cfg, QUADRATURE_MODE); in quad8_function_write()
714 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_mode_read()
761 ret = quad8_control_register_update(priv->map, priv->cmr, count->id, count_mode, in quad8_count_mode_write()
854 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_read()
882 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_write()
1264 priv->cmr[channel] = SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) | in quad8_init_counter()
1266 ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->cmr[channel]); in quad8_init_counter()
/linux/drivers/clocksource/
H A Dtimer-atmel-tcb.c44 u32 cmr; member
78 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_suspend()
94 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_resume()