1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/errno.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/random.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/eq.h>
42 #include <linux/debugfs.h>
43
44 #include "mlx5_core.h"
45 #include "lib/eq.h"
46 #include "lib/tout.h"
47 #define CREATE_TRACE_POINTS
48 #include "diag/cmd_tracepoint.h"
49
50 struct mlx5_ifc_mbox_out_bits {
51 u8 status[0x8];
52 u8 reserved_at_8[0x18];
53
54 u8 syndrome[0x20];
55
56 u8 reserved_at_40[0x40];
57 };
58
59 struct mlx5_ifc_mbox_in_bits {
60 u8 opcode[0x10];
61 u8 uid[0x10];
62
63 u8 reserved_at_20[0x10];
64 u8 op_mod[0x10];
65
66 u8 reserved_at_40[0x40];
67 };
68
69 enum {
70 CMD_IF_REV = 5,
71 };
72
73 enum {
74 CMD_MODE_POLLING,
75 CMD_MODE_EVENTS
76 };
77
78 enum {
79 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
80 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
81 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
82 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
83 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
84 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
85 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
86 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
87 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
88 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
89 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
90 };
91
in_to_opcode(void * in)92 static u16 in_to_opcode(void *in)
93 {
94 return MLX5_GET(mbox_in, in, opcode);
95 }
96
97 /* Returns true for opcodes that might be triggered very frequently and throttle
98 * the command interface. Limit their command slots usage.
99 */
mlx5_cmd_is_throttle_opcode(u16 op)100 static bool mlx5_cmd_is_throttle_opcode(u16 op)
101 {
102 switch (op) {
103 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
104 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
105 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
106 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
107 case MLX5_CMD_OP_SYNC_CRYPTO:
108 return true;
109 }
110 return false;
111 }
112
113 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)114 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
115 struct mlx5_cmd_msg *out, void *uout, int uout_size,
116 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
117 {
118 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
119 struct mlx5_cmd_work_ent *ent;
120
121 ent = kzalloc(sizeof(*ent), alloc_flags);
122 if (!ent)
123 return ERR_PTR(-ENOMEM);
124
125 ent->idx = -EINVAL;
126 ent->in = in;
127 ent->out = out;
128 ent->uout = uout;
129 ent->uout_size = uout_size;
130 ent->callback = cbk;
131 ent->context = context;
132 ent->cmd = cmd;
133 ent->page_queue = page_queue;
134 ent->op = in_to_opcode(in->first.data);
135 refcount_set(&ent->refcnt, 1);
136
137 return ent;
138 }
139
cmd_free_ent(struct mlx5_cmd_work_ent * ent)140 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
141 {
142 kfree(ent);
143 }
144
alloc_token(struct mlx5_cmd * cmd)145 static u8 alloc_token(struct mlx5_cmd *cmd)
146 {
147 u8 token;
148
149 spin_lock(&cmd->token_lock);
150 cmd->token++;
151 if (cmd->token == 0)
152 cmd->token++;
153 token = cmd->token;
154 spin_unlock(&cmd->token_lock);
155
156 return token;
157 }
158
cmd_alloc_index(struct mlx5_cmd * cmd,struct mlx5_cmd_work_ent * ent)159 static int cmd_alloc_index(struct mlx5_cmd *cmd, struct mlx5_cmd_work_ent *ent)
160 {
161 unsigned long flags;
162 int ret;
163
164 spin_lock_irqsave(&cmd->alloc_lock, flags);
165 ret = find_first_bit(&cmd->vars.bitmask, cmd->vars.max_reg_cmds);
166 if (ret < cmd->vars.max_reg_cmds) {
167 clear_bit(ret, &cmd->vars.bitmask);
168 ent->idx = ret;
169 cmd->ent_arr[ent->idx] = ent;
170 }
171 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
172
173 return ret < cmd->vars.max_reg_cmds ? ret : -ENOMEM;
174 }
175
cmd_free_index(struct mlx5_cmd * cmd,int idx)176 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
177 {
178 lockdep_assert_held(&cmd->alloc_lock);
179 set_bit(idx, &cmd->vars.bitmask);
180 }
181
cmd_ent_get(struct mlx5_cmd_work_ent * ent)182 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
183 {
184 refcount_inc(&ent->refcnt);
185 }
186
cmd_ent_put(struct mlx5_cmd_work_ent * ent)187 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
188 {
189 struct mlx5_cmd *cmd = ent->cmd;
190 unsigned long flags;
191
192 spin_lock_irqsave(&cmd->alloc_lock, flags);
193 if (!refcount_dec_and_test(&ent->refcnt))
194 goto out;
195
196 if (ent->idx >= 0) {
197 cmd_free_index(cmd, ent->idx);
198 up(ent->page_queue ? &cmd->vars.pages_sem : &cmd->vars.sem);
199 }
200
201 cmd_free_ent(ent);
202 out:
203 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
204 }
205
get_inst(struct mlx5_cmd * cmd,int idx)206 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
207 {
208 return cmd->cmd_buf + (idx << cmd->vars.log_stride);
209 }
210
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)211 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
212 {
213 int size = msg->len;
214 int blen = size - min_t(int, sizeof(msg->first.data), size);
215
216 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
217 }
218
xor8_buf(void * buf,size_t offset,int len)219 static u8 xor8_buf(void *buf, size_t offset, int len)
220 {
221 u8 *ptr = buf;
222 u8 sum = 0;
223 int i;
224 int end = len + offset;
225
226 for (i = offset; i < end; i++)
227 sum ^= ptr[i];
228
229 return sum;
230 }
231
verify_block_sig(struct mlx5_cmd_prot_block * block)232 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
233 {
234 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
235 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
236
237 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
238 return -EHWPOISON;
239
240 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
241 return -EHWPOISON;
242
243 return 0;
244 }
245
calc_block_sig(struct mlx5_cmd_prot_block * block)246 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
247 {
248 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
249 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
250
251 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
252 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
253 }
254
calc_chain_sig(struct mlx5_cmd_msg * msg)255 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
256 {
257 struct mlx5_cmd_mailbox *next = msg->next;
258 int n = mlx5_calc_cmd_blocks(msg);
259 int i = 0;
260
261 for (i = 0; i < n && next; i++) {
262 calc_block_sig(next->buf);
263 next = next->next;
264 }
265 }
266
set_signature(struct mlx5_cmd_work_ent * ent,int csum)267 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
268 {
269 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
270 if (csum) {
271 calc_chain_sig(ent->in);
272 calc_chain_sig(ent->out);
273 }
274 }
275
poll_timeout(struct mlx5_cmd_work_ent * ent)276 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
277 {
278 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, cmd);
279 u64 cmd_to_ms = mlx5_tout_ms(dev, CMD);
280 unsigned long poll_end;
281 u8 own;
282
283 poll_end = jiffies + msecs_to_jiffies(cmd_to_ms + 1000);
284
285 do {
286 own = READ_ONCE(ent->lay->status_own);
287 if (!(own & CMD_OWNER_HW)) {
288 ent->ret = 0;
289 return;
290 }
291 cond_resched();
292 } while (time_before(jiffies, poll_end));
293
294 ent->ret = -ETIMEDOUT;
295 }
296
verify_signature(struct mlx5_cmd_work_ent * ent)297 static int verify_signature(struct mlx5_cmd_work_ent *ent)
298 {
299 struct mlx5_cmd_mailbox *next = ent->out->next;
300 int n = mlx5_calc_cmd_blocks(ent->out);
301 int err;
302 u8 sig;
303 int i = 0;
304
305 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
306 if (sig != 0xff)
307 return -EHWPOISON;
308
309 for (i = 0; i < n && next; i++) {
310 err = verify_block_sig(next->buf);
311 if (err)
312 return -EHWPOISON;
313
314 next = next->next;
315 }
316
317 return 0;
318 }
319
dump_buf(void * buf,int size,int data_only,int offset,int idx)320 static void dump_buf(void *buf, int size, int data_only, int offset, int idx)
321 {
322 __be32 *p = buf;
323 int i;
324
325 for (i = 0; i < size; i += 16) {
326 pr_debug("cmd[%d]: %03x: %08x %08x %08x %08x\n", idx, offset,
327 be32_to_cpu(p[0]), be32_to_cpu(p[1]),
328 be32_to_cpu(p[2]), be32_to_cpu(p[3]));
329 p += 4;
330 offset += 16;
331 }
332 if (!data_only)
333 pr_debug("\n");
334 }
335
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)336 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
337 u32 *synd, u8 *status)
338 {
339 *synd = 0;
340 *status = 0;
341
342 switch (op) {
343 case MLX5_CMD_OP_TEARDOWN_HCA:
344 case MLX5_CMD_OP_DISABLE_HCA:
345 case MLX5_CMD_OP_MANAGE_PAGES:
346 case MLX5_CMD_OP_DESTROY_MKEY:
347 case MLX5_CMD_OP_DESTROY_EQ:
348 case MLX5_CMD_OP_DESTROY_CQ:
349 case MLX5_CMD_OP_DESTROY_QP:
350 case MLX5_CMD_OP_DESTROY_PSV:
351 case MLX5_CMD_OP_DESTROY_SRQ:
352 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
353 case MLX5_CMD_OP_DESTROY_XRQ:
354 case MLX5_CMD_OP_DESTROY_DCT:
355 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
356 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
357 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
358 case MLX5_CMD_OP_DEALLOC_PD:
359 case MLX5_CMD_OP_DEALLOC_UAR:
360 case MLX5_CMD_OP_DETACH_FROM_MCG:
361 case MLX5_CMD_OP_DEALLOC_XRCD:
362 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
363 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
364 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
365 case MLX5_CMD_OP_DESTROY_LAG:
366 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
367 case MLX5_CMD_OP_DESTROY_TIR:
368 case MLX5_CMD_OP_DESTROY_SQ:
369 case MLX5_CMD_OP_DESTROY_RQ:
370 case MLX5_CMD_OP_DESTROY_RMP:
371 case MLX5_CMD_OP_DESTROY_TIS:
372 case MLX5_CMD_OP_DESTROY_RQT:
373 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
374 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
375 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
376 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
377 case MLX5_CMD_OP_2ERR_QP:
378 case MLX5_CMD_OP_2RST_QP:
379 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
380 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
381 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
382 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
383 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
384 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
385 case MLX5_CMD_OP_FPGA_DESTROY_QP:
386 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
387 case MLX5_CMD_OP_DEALLOC_MEMIC:
388 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
389 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
390 case MLX5_CMD_OP_DEALLOC_SF:
391 case MLX5_CMD_OP_DESTROY_UCTX:
392 case MLX5_CMD_OP_DESTROY_UMEM:
393 case MLX5_CMD_OP_MODIFY_RQT:
394 return MLX5_CMD_STAT_OK;
395
396 case MLX5_CMD_OP_QUERY_HCA_CAP:
397 case MLX5_CMD_OP_QUERY_ADAPTER:
398 case MLX5_CMD_OP_INIT_HCA:
399 case MLX5_CMD_OP_ENABLE_HCA:
400 case MLX5_CMD_OP_QUERY_PAGES:
401 case MLX5_CMD_OP_SET_HCA_CAP:
402 case MLX5_CMD_OP_QUERY_ISSI:
403 case MLX5_CMD_OP_SET_ISSI:
404 case MLX5_CMD_OP_CREATE_MKEY:
405 case MLX5_CMD_OP_QUERY_MKEY:
406 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
407 case MLX5_CMD_OP_CREATE_EQ:
408 case MLX5_CMD_OP_QUERY_EQ:
409 case MLX5_CMD_OP_GEN_EQE:
410 case MLX5_CMD_OP_CREATE_CQ:
411 case MLX5_CMD_OP_QUERY_CQ:
412 case MLX5_CMD_OP_MODIFY_CQ:
413 case MLX5_CMD_OP_CREATE_QP:
414 case MLX5_CMD_OP_RST2INIT_QP:
415 case MLX5_CMD_OP_INIT2RTR_QP:
416 case MLX5_CMD_OP_RTR2RTS_QP:
417 case MLX5_CMD_OP_RTS2RTS_QP:
418 case MLX5_CMD_OP_SQERR2RTS_QP:
419 case MLX5_CMD_OP_QUERY_QP:
420 case MLX5_CMD_OP_SQD_RTS_QP:
421 case MLX5_CMD_OP_INIT2INIT_QP:
422 case MLX5_CMD_OP_CREATE_PSV:
423 case MLX5_CMD_OP_CREATE_SRQ:
424 case MLX5_CMD_OP_QUERY_SRQ:
425 case MLX5_CMD_OP_ARM_RQ:
426 case MLX5_CMD_OP_CREATE_XRC_SRQ:
427 case MLX5_CMD_OP_QUERY_XRC_SRQ:
428 case MLX5_CMD_OP_ARM_XRC_SRQ:
429 case MLX5_CMD_OP_CREATE_XRQ:
430 case MLX5_CMD_OP_QUERY_XRQ:
431 case MLX5_CMD_OP_ARM_XRQ:
432 case MLX5_CMD_OP_CREATE_DCT:
433 case MLX5_CMD_OP_DRAIN_DCT:
434 case MLX5_CMD_OP_QUERY_DCT:
435 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
436 case MLX5_CMD_OP_QUERY_VPORT_STATE:
437 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
438 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
439 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
440 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
441 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
442 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
443 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
444 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
445 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
446 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
447 case MLX5_CMD_OP_QUERY_VNIC_ENV:
448 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
449 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
450 case MLX5_CMD_OP_QUERY_Q_COUNTER:
451 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
452 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
453 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
454 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
455 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
456 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
457 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
458 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
459 case MLX5_CMD_OP_ALLOC_PD:
460 case MLX5_CMD_OP_ALLOC_UAR:
461 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
462 case MLX5_CMD_OP_ACCESS_REG:
463 case MLX5_CMD_OP_ATTACH_TO_MCG:
464 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
465 case MLX5_CMD_OP_MAD_IFC:
466 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
467 case MLX5_CMD_OP_SET_MAD_DEMUX:
468 case MLX5_CMD_OP_NOP:
469 case MLX5_CMD_OP_ALLOC_XRCD:
470 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
471 case MLX5_CMD_OP_QUERY_CONG_STATUS:
472 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
473 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
474 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
475 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
476 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
477 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
478 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
479 case MLX5_CMD_OP_CREATE_LAG:
480 case MLX5_CMD_OP_MODIFY_LAG:
481 case MLX5_CMD_OP_QUERY_LAG:
482 case MLX5_CMD_OP_CREATE_VPORT_LAG:
483 case MLX5_CMD_OP_CREATE_TIR:
484 case MLX5_CMD_OP_MODIFY_TIR:
485 case MLX5_CMD_OP_QUERY_TIR:
486 case MLX5_CMD_OP_CREATE_SQ:
487 case MLX5_CMD_OP_MODIFY_SQ:
488 case MLX5_CMD_OP_QUERY_SQ:
489 case MLX5_CMD_OP_CREATE_RQ:
490 case MLX5_CMD_OP_MODIFY_RQ:
491 case MLX5_CMD_OP_QUERY_RQ:
492 case MLX5_CMD_OP_CREATE_RMP:
493 case MLX5_CMD_OP_MODIFY_RMP:
494 case MLX5_CMD_OP_QUERY_RMP:
495 case MLX5_CMD_OP_CREATE_TIS:
496 case MLX5_CMD_OP_MODIFY_TIS:
497 case MLX5_CMD_OP_QUERY_TIS:
498 case MLX5_CMD_OP_CREATE_RQT:
499 case MLX5_CMD_OP_QUERY_RQT:
500
501 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
502 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
503 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
504 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
505 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
506 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
507 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
508 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
509 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
510 case MLX5_CMD_OP_FPGA_CREATE_QP:
511 case MLX5_CMD_OP_FPGA_MODIFY_QP:
512 case MLX5_CMD_OP_FPGA_QUERY_QP:
513 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
514 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
515 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
516 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
517 case MLX5_CMD_OP_CREATE_UCTX:
518 case MLX5_CMD_OP_CREATE_UMEM:
519 case MLX5_CMD_OP_ALLOC_MEMIC:
520 case MLX5_CMD_OP_MODIFY_XRQ:
521 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
522 case MLX5_CMD_OP_QUERY_VHCA_STATE:
523 case MLX5_CMD_OP_MODIFY_VHCA_STATE:
524 case MLX5_CMD_OP_ALLOC_SF:
525 case MLX5_CMD_OP_SUSPEND_VHCA:
526 case MLX5_CMD_OP_RESUME_VHCA:
527 case MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE:
528 case MLX5_CMD_OP_SAVE_VHCA_STATE:
529 case MLX5_CMD_OP_LOAD_VHCA_STATE:
530 case MLX5_CMD_OP_SYNC_CRYPTO:
531 case MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS:
532 *status = MLX5_DRIVER_STATUS_ABORTED;
533 *synd = MLX5_DRIVER_SYND;
534 return -ENOLINK;
535 default:
536 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
537 return -EINVAL;
538 }
539 }
540
mlx5_command_str(int command)541 const char *mlx5_command_str(int command)
542 {
543 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
544
545 switch (command) {
546 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
547 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
548 MLX5_COMMAND_STR_CASE(INIT_HCA);
549 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
550 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
551 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
552 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
553 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
554 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
555 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
556 MLX5_COMMAND_STR_CASE(SET_ISSI);
557 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
558 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
559 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
560 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
561 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
562 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
563 MLX5_COMMAND_STR_CASE(CREATE_EQ);
564 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
565 MLX5_COMMAND_STR_CASE(QUERY_EQ);
566 MLX5_COMMAND_STR_CASE(GEN_EQE);
567 MLX5_COMMAND_STR_CASE(CREATE_CQ);
568 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
569 MLX5_COMMAND_STR_CASE(QUERY_CQ);
570 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
571 MLX5_COMMAND_STR_CASE(CREATE_QP);
572 MLX5_COMMAND_STR_CASE(DESTROY_QP);
573 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
574 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
575 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
576 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
577 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
578 MLX5_COMMAND_STR_CASE(2ERR_QP);
579 MLX5_COMMAND_STR_CASE(2RST_QP);
580 MLX5_COMMAND_STR_CASE(QUERY_QP);
581 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
582 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
583 MLX5_COMMAND_STR_CASE(CREATE_PSV);
584 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
585 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
586 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
587 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
588 MLX5_COMMAND_STR_CASE(ARM_RQ);
589 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
590 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
591 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
592 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
593 MLX5_COMMAND_STR_CASE(CREATE_DCT);
594 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
595 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
596 MLX5_COMMAND_STR_CASE(QUERY_DCT);
597 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
598 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
599 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
600 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
601 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
602 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
603 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
604 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
605 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
606 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
607 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
608 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
609 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
610 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
611 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
612 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
613 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
614 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
615 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
616 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
617 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
618 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
619 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
620 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
621 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
622 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
623 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
624 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
625 MLX5_COMMAND_STR_CASE(ALLOC_PD);
626 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
627 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
628 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
629 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
630 MLX5_COMMAND_STR_CASE(ACCESS_REG);
631 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
632 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
633 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
634 MLX5_COMMAND_STR_CASE(MAD_IFC);
635 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
636 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
637 MLX5_COMMAND_STR_CASE(NOP);
638 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
639 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
640 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
641 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
642 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
643 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
644 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
645 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
646 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
647 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
648 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
649 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
650 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
651 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
652 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
653 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
654 MLX5_COMMAND_STR_CASE(CREATE_LAG);
655 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
656 MLX5_COMMAND_STR_CASE(QUERY_LAG);
657 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
658 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
659 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
660 MLX5_COMMAND_STR_CASE(CREATE_TIR);
661 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
662 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
663 MLX5_COMMAND_STR_CASE(QUERY_TIR);
664 MLX5_COMMAND_STR_CASE(CREATE_SQ);
665 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
666 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
667 MLX5_COMMAND_STR_CASE(QUERY_SQ);
668 MLX5_COMMAND_STR_CASE(CREATE_RQ);
669 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
670 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
671 MLX5_COMMAND_STR_CASE(QUERY_RQ);
672 MLX5_COMMAND_STR_CASE(CREATE_RMP);
673 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
674 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
675 MLX5_COMMAND_STR_CASE(QUERY_RMP);
676 MLX5_COMMAND_STR_CASE(CREATE_TIS);
677 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
678 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
679 MLX5_COMMAND_STR_CASE(QUERY_TIS);
680 MLX5_COMMAND_STR_CASE(CREATE_RQT);
681 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
682 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
683 MLX5_COMMAND_STR_CASE(QUERY_RQT);
684 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
685 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
686 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
687 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
688 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
689 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
690 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
691 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
692 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
693 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
694 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
695 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
696 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
697 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
698 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
699 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
700 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
701 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
702 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
703 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
704 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
705 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
706 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
707 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
708 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
709 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
710 MLX5_COMMAND_STR_CASE(ARM_XRQ);
711 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
712 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
713 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
714 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
715 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
716 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
717 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
718 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
719 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
720 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
721 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
722 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
723 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
724 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
725 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE);
726 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE);
727 MLX5_COMMAND_STR_CASE(ALLOC_SF);
728 MLX5_COMMAND_STR_CASE(DEALLOC_SF);
729 MLX5_COMMAND_STR_CASE(SUSPEND_VHCA);
730 MLX5_COMMAND_STR_CASE(RESUME_VHCA);
731 MLX5_COMMAND_STR_CASE(QUERY_VHCA_MIGRATION_STATE);
732 MLX5_COMMAND_STR_CASE(SAVE_VHCA_STATE);
733 MLX5_COMMAND_STR_CASE(LOAD_VHCA_STATE);
734 MLX5_COMMAND_STR_CASE(SYNC_CRYPTO);
735 MLX5_COMMAND_STR_CASE(ALLOW_OTHER_VHCA_ACCESS);
736 default: return "unknown command opcode";
737 }
738 }
739
cmd_status_str(u8 status)740 static const char *cmd_status_str(u8 status)
741 {
742 switch (status) {
743 case MLX5_CMD_STAT_OK:
744 return "OK";
745 case MLX5_CMD_STAT_INT_ERR:
746 return "internal error";
747 case MLX5_CMD_STAT_BAD_OP_ERR:
748 return "bad operation";
749 case MLX5_CMD_STAT_BAD_PARAM_ERR:
750 return "bad parameter";
751 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
752 return "bad system state";
753 case MLX5_CMD_STAT_BAD_RES_ERR:
754 return "bad resource";
755 case MLX5_CMD_STAT_RES_BUSY:
756 return "resource busy";
757 case MLX5_CMD_STAT_NOT_READY:
758 return "FW not ready";
759 case MLX5_CMD_STAT_LIM_ERR:
760 return "limits exceeded";
761 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
762 return "bad resource state";
763 case MLX5_CMD_STAT_IX_ERR:
764 return "bad index";
765 case MLX5_CMD_STAT_NO_RES_ERR:
766 return "no resources";
767 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
768 return "bad input length";
769 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
770 return "bad output length";
771 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
772 return "bad QP state";
773 case MLX5_CMD_STAT_BAD_PKT_ERR:
774 return "bad packet (discarded)";
775 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
776 return "bad size too many outstanding CQEs";
777 default:
778 return "unknown status";
779 }
780 }
781
cmd_status_to_err(u8 status)782 static int cmd_status_to_err(u8 status)
783 {
784 switch (status) {
785 case MLX5_CMD_STAT_OK: return 0;
786 case MLX5_CMD_STAT_INT_ERR: return -EIO;
787 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
788 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
789 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
790 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
791 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
792 case MLX5_CMD_STAT_NOT_READY: return -EAGAIN;
793 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
794 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
795 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
796 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
797 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
798 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
799 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
800 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
801 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
802 default: return -EIO;
803 }
804 }
805
mlx5_cmd_out_err(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)806 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
807 {
808 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
809 u8 status = MLX5_GET(mbox_out, out, status);
810
811 mlx5_core_err_rl(dev,
812 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x), err(%d)\n",
813 mlx5_command_str(opcode), opcode, op_mod,
814 cmd_status_str(status), status, syndrome, cmd_status_to_err(status));
815 }
816 EXPORT_SYMBOL(mlx5_cmd_out_err);
817
cmd_status_print(struct mlx5_core_dev * dev,void * in,void * out)818 static void cmd_status_print(struct mlx5_core_dev *dev, void *in, void *out)
819 {
820 u16 opcode, op_mod;
821 u8 status;
822 u16 uid;
823
824 opcode = in_to_opcode(in);
825 op_mod = MLX5_GET(mbox_in, in, op_mod);
826 uid = MLX5_GET(mbox_in, in, uid);
827 status = MLX5_GET(mbox_out, out, status);
828
829 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY &&
830 opcode != MLX5_CMD_OP_CREATE_UCTX && status != MLX5_CMD_STAT_NOT_READY)
831 mlx5_cmd_out_err(dev, opcode, op_mod, out);
832 }
833
mlx5_cmd_check(struct mlx5_core_dev * dev,int err,void * in,void * out)834 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out)
835 {
836 /* aborted due to PCI error or via reset flow mlx5_cmd_trigger_completions() */
837 if (err == -ENXIO) {
838 u16 opcode = in_to_opcode(in);
839 u32 syndrome;
840 u8 status;
841
842 /* PCI Error, emulate command return status, for smooth reset */
843 err = mlx5_internal_err_ret_value(dev, opcode, &syndrome, &status);
844 MLX5_SET(mbox_out, out, status, status);
845 MLX5_SET(mbox_out, out, syndrome, syndrome);
846 if (!err)
847 return 0;
848 }
849
850 /* driver or FW delivery error */
851 if (err != -EREMOTEIO && err)
852 return err;
853
854 /* check outbox status */
855 err = cmd_status_to_err(MLX5_GET(mbox_out, out, status));
856 if (err)
857 cmd_status_print(dev, in, out);
858
859 return err;
860 }
861 EXPORT_SYMBOL(mlx5_cmd_check);
862
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)863 static void dump_command(struct mlx5_core_dev *dev,
864 struct mlx5_cmd_work_ent *ent, int input)
865 {
866 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
867 struct mlx5_cmd_mailbox *next = msg->next;
868 int n = mlx5_calc_cmd_blocks(msg);
869 u16 op = ent->op;
870 int data_only;
871 u32 offset = 0;
872 int dump_len;
873 int i;
874
875 mlx5_core_dbg(dev, "cmd[%d]: start dump\n", ent->idx);
876 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
877
878 if (data_only)
879 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
880 "cmd[%d]: dump command data %s(0x%x) %s\n",
881 ent->idx, mlx5_command_str(op), op,
882 input ? "INPUT" : "OUTPUT");
883 else
884 mlx5_core_dbg(dev, "cmd[%d]: dump command %s(0x%x) %s\n",
885 ent->idx, mlx5_command_str(op), op,
886 input ? "INPUT" : "OUTPUT");
887
888 if (data_only) {
889 if (input) {
890 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset, ent->idx);
891 offset += sizeof(ent->lay->in);
892 } else {
893 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset, ent->idx);
894 offset += sizeof(ent->lay->out);
895 }
896 } else {
897 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset, ent->idx);
898 offset += sizeof(*ent->lay);
899 }
900
901 for (i = 0; i < n && next; i++) {
902 if (data_only) {
903 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
904 dump_buf(next->buf, dump_len, 1, offset, ent->idx);
905 offset += MLX5_CMD_DATA_BLOCK_SIZE;
906 } else {
907 mlx5_core_dbg(dev, "cmd[%d]: command block:\n", ent->idx);
908 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset,
909 ent->idx);
910 offset += sizeof(struct mlx5_cmd_prot_block);
911 }
912 next = next->next;
913 }
914
915 if (data_only)
916 pr_debug("\n");
917
918 mlx5_core_dbg(dev, "cmd[%d]: end dump\n", ent->idx);
919 }
920
921 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
922
cb_timeout_handler(struct work_struct * work)923 static void cb_timeout_handler(struct work_struct *work)
924 {
925 struct delayed_work *dwork = container_of(work, struct delayed_work,
926 work);
927 struct mlx5_cmd_work_ent *ent = container_of(dwork,
928 struct mlx5_cmd_work_ent,
929 cb_timeout_work);
930 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
931 cmd);
932
933 mlx5_cmd_eq_recover(dev);
934
935 /* Maybe got handled by eq recover ? */
936 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
937 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
938 mlx5_command_str(ent->op), ent->op);
939 goto out; /* phew, already handled */
940 }
941
942 ent->ret = -ETIMEDOUT;
943 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
944 ent->idx, mlx5_command_str(ent->op), ent->op);
945 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
946
947 out:
948 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
949 }
950
951 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
952 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
953 struct mlx5_cmd_msg *msg);
954
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)955 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
956 {
957 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
958 return true;
959
960 return cmd->allowed_opcode == opcode;
961 }
962
mlx5_cmd_is_down(struct mlx5_core_dev * dev)963 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
964 {
965 return pci_channel_offline(dev->pdev) ||
966 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
967 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
968 }
969
cmd_work_handler(struct work_struct * work)970 static void cmd_work_handler(struct work_struct *work)
971 {
972 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
973 struct mlx5_cmd *cmd = ent->cmd;
974 bool poll_cmd = ent->polling;
975 struct mlx5_cmd_layout *lay;
976 struct mlx5_core_dev *dev;
977 unsigned long timeout;
978 unsigned long flags;
979 int alloc_ret;
980 int cmd_mode;
981
982 complete(&ent->handling);
983
984 dev = container_of(cmd, struct mlx5_core_dev, cmd);
985 timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
986
987 if (!ent->page_queue) {
988 if (down_timeout(&cmd->vars.sem, timeout)) {
989 mlx5_core_warn(dev, "%s(0x%x) timed out while waiting for a slot.\n",
990 mlx5_command_str(ent->op), ent->op);
991 if (ent->callback) {
992 ent->callback(-EBUSY, ent->context);
993 mlx5_free_cmd_msg(dev, ent->out);
994 free_msg(dev, ent->in);
995 cmd_ent_put(ent);
996 } else {
997 ent->ret = -EBUSY;
998 complete(&ent->done);
999 }
1000 complete(&ent->slotted);
1001 return;
1002 }
1003 alloc_ret = cmd_alloc_index(cmd, ent);
1004 if (alloc_ret < 0) {
1005 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
1006 if (ent->callback) {
1007 ent->callback(-EAGAIN, ent->context);
1008 mlx5_free_cmd_msg(dev, ent->out);
1009 free_msg(dev, ent->in);
1010 cmd_ent_put(ent);
1011 } else {
1012 ent->ret = -EAGAIN;
1013 complete(&ent->done);
1014 }
1015 up(&cmd->vars.sem);
1016 complete(&ent->slotted);
1017 return;
1018 }
1019 } else {
1020 down(&cmd->vars.pages_sem);
1021 ent->idx = cmd->vars.max_reg_cmds;
1022 spin_lock_irqsave(&cmd->alloc_lock, flags);
1023 clear_bit(ent->idx, &cmd->vars.bitmask);
1024 cmd->ent_arr[ent->idx] = ent;
1025 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
1026 }
1027
1028 complete(&ent->slotted);
1029
1030 lay = get_inst(cmd, ent->idx);
1031 ent->lay = lay;
1032 memset(lay, 0, sizeof(*lay));
1033 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
1034 if (ent->in->next)
1035 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
1036 lay->inlen = cpu_to_be32(ent->in->len);
1037 if (ent->out->next)
1038 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
1039 lay->outlen = cpu_to_be32(ent->out->len);
1040 lay->type = MLX5_PCI_CMD_XPORT;
1041 lay->token = ent->token;
1042 lay->status_own = CMD_OWNER_HW;
1043 set_signature(ent, !cmd->checksum_disabled);
1044 dump_command(dev, ent, 1);
1045 ent->ts1 = ktime_get_ns();
1046 cmd_mode = cmd->mode;
1047
1048 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, timeout))
1049 cmd_ent_get(ent);
1050 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
1051
1052 cmd_ent_get(ent); /* for the _real_ FW event on completion */
1053 /* Skip sending command to fw if internal error */
1054 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
1055 ent->ret = -ENXIO;
1056 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1057 return;
1058 }
1059
1060 /* ring doorbell after the descriptor is valid */
1061 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
1062 wmb();
1063 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
1064 /* if not in polling don't use ent after this point */
1065 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
1066 poll_timeout(ent);
1067 /* make sure we read the descriptor after ownership is SW */
1068 rmb();
1069 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
1070 }
1071 }
1072
deliv_status_to_err(u8 status)1073 static int deliv_status_to_err(u8 status)
1074 {
1075 switch (status) {
1076 case MLX5_CMD_DELIVERY_STAT_OK:
1077 case MLX5_DRIVER_STATUS_ABORTED:
1078 return 0;
1079 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1080 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1081 return -EBADR;
1082 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1083 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1084 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1085 return -EFAULT; /* Bad address */
1086 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1087 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1088 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1089 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1090 return -ENOMSG;
1091 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1092 return -EIO;
1093 default:
1094 return -EINVAL;
1095 }
1096 }
1097
deliv_status_to_str(u8 status)1098 static const char *deliv_status_to_str(u8 status)
1099 {
1100 switch (status) {
1101 case MLX5_CMD_DELIVERY_STAT_OK:
1102 return "no errors";
1103 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1104 return "signature error";
1105 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1106 return "token error";
1107 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1108 return "bad block number";
1109 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1110 return "output pointer not aligned to block size";
1111 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1112 return "input pointer not aligned to block size";
1113 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1114 return "firmware internal error";
1115 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1116 return "command input length error";
1117 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1118 return "command output length error";
1119 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1120 return "reserved fields not cleared";
1121 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1122 return "bad command descriptor type";
1123 default:
1124 return "unknown status code";
1125 }
1126 }
1127
1128 enum {
1129 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1130 };
1131
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1132 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1133 struct mlx5_cmd_work_ent *ent)
1134 {
1135 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1136
1137 mlx5_cmd_eq_recover(dev);
1138
1139 /* Re-wait on the ent->done after executing the recovery flow. If the
1140 * recovery flow (or any other recovery flow running simultaneously)
1141 * has recovered an EQE, it should cause the entry to be completed by
1142 * the command interface.
1143 */
1144 if (wait_for_completion_timeout(&ent->done, timeout)) {
1145 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1146 mlx5_command_str(ent->op), ent->op);
1147 return;
1148 }
1149
1150 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1151 mlx5_command_str(ent->op), ent->op);
1152
1153 ent->ret = -ETIMEDOUT;
1154 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1155 }
1156
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1157 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1158 {
1159 unsigned long timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
1160 struct mlx5_cmd *cmd = &dev->cmd;
1161 int err;
1162
1163 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1164 cancel_work_sync(&ent->work)) {
1165 ent->ret = -ECANCELED;
1166 goto out_err;
1167 }
1168
1169 wait_for_completion(&ent->slotted);
1170
1171 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1172 wait_for_completion(&ent->done);
1173 else if (!wait_for_completion_timeout(&ent->done, timeout))
1174 wait_func_handle_exec_timeout(dev, ent);
1175
1176 out_err:
1177 err = ent->ret;
1178
1179 if (err == -ETIMEDOUT) {
1180 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1181 mlx5_command_str(ent->op), ent->op);
1182 } else if (err == -ECANCELED) {
1183 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1184 mlx5_command_str(ent->op), ent->op);
1185 } else if (err == -EBUSY) {
1186 mlx5_core_warn(dev, "%s(0x%x) timeout while waiting for command semaphore.\n",
1187 mlx5_command_str(ent->op), ent->op);
1188 }
1189 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1190 err, deliv_status_to_str(ent->status), ent->status);
1191
1192 return err;
1193 }
1194
1195 /* Notes:
1196 * 1. Callback functions may not sleep
1197 * 2. page queue commands do not support asynchrous completion
1198 *
1199 * return value in case (!callback):
1200 * ret < 0 : Command execution couldn't be submitted by driver
1201 * ret > 0 : Command execution couldn't be performed by firmware
1202 * ret == 0: Command was executed by FW, Caller must check FW outbox status.
1203 *
1204 * return value in case (callback):
1205 * ret < 0 : Command execution couldn't be submitted by driver
1206 * ret == 0: Command will be submitted to FW for execution
1207 * and the callback will be called for further status updates
1208 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 token,bool force_polling)1209 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1210 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1211 mlx5_cmd_cbk_t callback,
1212 void *context, int page_queue,
1213 u8 token, bool force_polling)
1214 {
1215 struct mlx5_cmd *cmd = &dev->cmd;
1216 struct mlx5_cmd_work_ent *ent;
1217 struct mlx5_cmd_stats *stats;
1218 u8 status = 0;
1219 int err = 0;
1220 s64 ds;
1221
1222 if (callback && page_queue)
1223 return -EINVAL;
1224
1225 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1226 callback, context, page_queue);
1227 if (IS_ERR(ent))
1228 return PTR_ERR(ent);
1229
1230 /* put for this ent is when consumed, depending on the use case
1231 * 1) (!callback) blocking flow: by caller after wait_func completes
1232 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1233 */
1234
1235 ent->token = token;
1236 ent->polling = force_polling;
1237
1238 init_completion(&ent->handling);
1239 init_completion(&ent->slotted);
1240 if (!callback)
1241 init_completion(&ent->done);
1242
1243 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1244 INIT_WORK(&ent->work, cmd_work_handler);
1245 if (page_queue) {
1246 cmd_work_handler(&ent->work);
1247 } else if (!queue_work(cmd->wq, &ent->work)) {
1248 mlx5_core_warn(dev, "failed to queue work\n");
1249 err = -EALREADY;
1250 goto out_free;
1251 }
1252
1253 if (callback)
1254 return 0; /* mlx5_cmd_comp_handler() will put(ent) */
1255
1256 err = wait_func(dev, ent);
1257 if (err == -ETIMEDOUT || err == -ECANCELED || err == -EBUSY)
1258 goto out_free;
1259
1260 ds = ent->ts2 - ent->ts1;
1261 stats = xa_load(&cmd->stats, ent->op);
1262 if (stats) {
1263 spin_lock_irq(&stats->lock);
1264 stats->sum += ds;
1265 ++stats->n;
1266 spin_unlock_irq(&stats->lock);
1267 }
1268 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1269 "fw exec time for %s is %lld nsec\n",
1270 mlx5_command_str(ent->op), ds);
1271
1272 out_free:
1273 status = ent->status;
1274 cmd_ent_put(ent);
1275 return err ? : status;
1276 }
1277
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1278 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1279 size_t count, loff_t *pos)
1280 {
1281 struct mlx5_core_dev *dev = filp->private_data;
1282 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1283 char lbuf[3];
1284 int err;
1285
1286 if (!dbg->in_msg || !dbg->out_msg)
1287 return -ENOMEM;
1288
1289 if (count < sizeof(lbuf) - 1)
1290 return -EINVAL;
1291
1292 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1293 return -EFAULT;
1294
1295 lbuf[sizeof(lbuf) - 1] = 0;
1296
1297 if (strcmp(lbuf, "go"))
1298 return -EINVAL;
1299
1300 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1301
1302 return err ? err : count;
1303 }
1304
1305 static const struct file_operations fops = {
1306 .owner = THIS_MODULE,
1307 .open = simple_open,
1308 .write = dbg_write,
1309 };
1310
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1311 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1312 u8 token)
1313 {
1314 struct mlx5_cmd_prot_block *block;
1315 struct mlx5_cmd_mailbox *next;
1316 int copy;
1317
1318 if (!to || !from)
1319 return -ENOMEM;
1320
1321 copy = min_t(int, size, sizeof(to->first.data));
1322 memcpy(to->first.data, from, copy);
1323 size -= copy;
1324 from += copy;
1325
1326 next = to->next;
1327 while (size) {
1328 if (!next) {
1329 /* this is a BUG */
1330 return -ENOMEM;
1331 }
1332
1333 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1334 block = next->buf;
1335 memcpy(block->data, from, copy);
1336 from += copy;
1337 size -= copy;
1338 block->token = token;
1339 next = next->next;
1340 }
1341
1342 return 0;
1343 }
1344
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1345 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1346 {
1347 struct mlx5_cmd_prot_block *block;
1348 struct mlx5_cmd_mailbox *next;
1349 int copy;
1350
1351 if (!to || !from)
1352 return -ENOMEM;
1353
1354 copy = min_t(int, size, sizeof(from->first.data));
1355 memcpy(to, from->first.data, copy);
1356 size -= copy;
1357 to += copy;
1358
1359 next = from->next;
1360 while (size) {
1361 if (!next) {
1362 /* this is a BUG */
1363 return -ENOMEM;
1364 }
1365
1366 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1367 block = next->buf;
1368
1369 memcpy(to, block->data, copy);
1370 to += copy;
1371 size -= copy;
1372 next = next->next;
1373 }
1374
1375 return 0;
1376 }
1377
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1378 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1379 gfp_t flags)
1380 {
1381 struct mlx5_cmd_mailbox *mailbox;
1382
1383 mailbox = kmalloc(sizeof(*mailbox), flags);
1384 if (!mailbox)
1385 return ERR_PTR(-ENOMEM);
1386
1387 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1388 &mailbox->dma);
1389 if (!mailbox->buf) {
1390 mlx5_core_dbg(dev, "failed allocation\n");
1391 kfree(mailbox);
1392 return ERR_PTR(-ENOMEM);
1393 }
1394 mailbox->next = NULL;
1395
1396 return mailbox;
1397 }
1398
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1399 static void free_cmd_box(struct mlx5_core_dev *dev,
1400 struct mlx5_cmd_mailbox *mailbox)
1401 {
1402 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1403 kfree(mailbox);
1404 }
1405
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1406 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1407 gfp_t flags, int size,
1408 u8 token)
1409 {
1410 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1411 struct mlx5_cmd_prot_block *block;
1412 struct mlx5_cmd_msg *msg;
1413 int err;
1414 int n;
1415 int i;
1416
1417 msg = kzalloc(sizeof(*msg), flags);
1418 if (!msg)
1419 return ERR_PTR(-ENOMEM);
1420
1421 msg->len = size;
1422 n = mlx5_calc_cmd_blocks(msg);
1423
1424 for (i = 0; i < n; i++) {
1425 tmp = alloc_cmd_box(dev, flags);
1426 if (IS_ERR(tmp)) {
1427 mlx5_core_warn(dev, "failed allocating block\n");
1428 err = PTR_ERR(tmp);
1429 goto err_alloc;
1430 }
1431
1432 block = tmp->buf;
1433 tmp->next = head;
1434 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1435 block->block_num = cpu_to_be32(n - i - 1);
1436 block->token = token;
1437 head = tmp;
1438 }
1439 msg->next = head;
1440 return msg;
1441
1442 err_alloc:
1443 while (head) {
1444 tmp = head->next;
1445 free_cmd_box(dev, head);
1446 head = tmp;
1447 }
1448 kfree(msg);
1449
1450 return ERR_PTR(err);
1451 }
1452
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1453 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1454 struct mlx5_cmd_msg *msg)
1455 {
1456 struct mlx5_cmd_mailbox *head = msg->next;
1457 struct mlx5_cmd_mailbox *next;
1458
1459 while (head) {
1460 next = head->next;
1461 free_cmd_box(dev, head);
1462 head = next;
1463 }
1464 kfree(msg);
1465 }
1466
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1467 static ssize_t data_write(struct file *filp, const char __user *buf,
1468 size_t count, loff_t *pos)
1469 {
1470 struct mlx5_core_dev *dev = filp->private_data;
1471 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1472 void *ptr;
1473
1474 if (*pos != 0)
1475 return -EINVAL;
1476
1477 kfree(dbg->in_msg);
1478 dbg->in_msg = NULL;
1479 dbg->inlen = 0;
1480 ptr = memdup_user(buf, count);
1481 if (IS_ERR(ptr))
1482 return PTR_ERR(ptr);
1483 dbg->in_msg = ptr;
1484 dbg->inlen = count;
1485
1486 *pos = count;
1487
1488 return count;
1489 }
1490
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1491 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1492 loff_t *pos)
1493 {
1494 struct mlx5_core_dev *dev = filp->private_data;
1495 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1496
1497 if (!dbg->out_msg)
1498 return -ENOMEM;
1499
1500 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1501 dbg->outlen);
1502 }
1503
1504 static const struct file_operations dfops = {
1505 .owner = THIS_MODULE,
1506 .open = simple_open,
1507 .write = data_write,
1508 .read = data_read,
1509 };
1510
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1511 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1512 loff_t *pos)
1513 {
1514 struct mlx5_core_dev *dev = filp->private_data;
1515 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1516 char outlen[8];
1517 int err;
1518
1519 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1520 if (err < 0)
1521 return err;
1522
1523 return simple_read_from_buffer(buf, count, pos, outlen, err);
1524 }
1525
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1526 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1527 size_t count, loff_t *pos)
1528 {
1529 struct mlx5_core_dev *dev = filp->private_data;
1530 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1531 char outlen_str[8] = {0};
1532 int outlen;
1533 void *ptr;
1534 int err;
1535
1536 if (*pos != 0 || count > 6)
1537 return -EINVAL;
1538
1539 kfree(dbg->out_msg);
1540 dbg->out_msg = NULL;
1541 dbg->outlen = 0;
1542
1543 if (copy_from_user(outlen_str, buf, count))
1544 return -EFAULT;
1545
1546 err = sscanf(outlen_str, "%d", &outlen);
1547 if (err != 1)
1548 return -EINVAL;
1549
1550 ptr = kzalloc(outlen, GFP_KERNEL);
1551 if (!ptr)
1552 return -ENOMEM;
1553
1554 dbg->out_msg = ptr;
1555 dbg->outlen = outlen;
1556
1557 *pos = count;
1558
1559 return count;
1560 }
1561
1562 static const struct file_operations olfops = {
1563 .owner = THIS_MODULE,
1564 .open = simple_open,
1565 .write = outlen_write,
1566 .read = outlen_read,
1567 };
1568
set_wqname(struct mlx5_core_dev * dev)1569 static void set_wqname(struct mlx5_core_dev *dev)
1570 {
1571 struct mlx5_cmd *cmd = &dev->cmd;
1572
1573 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1574 dev_name(dev->device));
1575 }
1576
clean_debug_files(struct mlx5_core_dev * dev)1577 static void clean_debug_files(struct mlx5_core_dev *dev)
1578 {
1579 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1580
1581 if (!mlx5_debugfs_root)
1582 return;
1583
1584 debugfs_remove_recursive(dbg->dbg_root);
1585 }
1586
create_debugfs_files(struct mlx5_core_dev * dev)1587 static void create_debugfs_files(struct mlx5_core_dev *dev)
1588 {
1589 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1590
1591 dbg->dbg_root = debugfs_create_dir("cmd", mlx5_debugfs_get_dev_root(dev));
1592
1593 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1594 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1595 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1596 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1597 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1598 }
1599
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1600 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1601 {
1602 struct mlx5_cmd *cmd = &dev->cmd;
1603 int i;
1604
1605 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1606 down(&cmd->vars.sem);
1607 down(&cmd->vars.pages_sem);
1608
1609 cmd->allowed_opcode = opcode;
1610
1611 up(&cmd->vars.pages_sem);
1612 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1613 up(&cmd->vars.sem);
1614 }
1615
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1616 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1617 {
1618 struct mlx5_cmd *cmd = &dev->cmd;
1619 int i;
1620
1621 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1622 down(&cmd->vars.sem);
1623 down(&cmd->vars.pages_sem);
1624
1625 cmd->mode = mode;
1626
1627 up(&cmd->vars.pages_sem);
1628 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1629 up(&cmd->vars.sem);
1630 }
1631
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1632 static int cmd_comp_notifier(struct notifier_block *nb,
1633 unsigned long type, void *data)
1634 {
1635 struct mlx5_core_dev *dev;
1636 struct mlx5_cmd *cmd;
1637 struct mlx5_eqe *eqe;
1638
1639 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1640 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1641 eqe = data;
1642
1643 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1644 return NOTIFY_DONE;
1645
1646 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1647
1648 return NOTIFY_OK;
1649 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1650 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1651 {
1652 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1653 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1654 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1655 }
1656
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1657 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1658 {
1659 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1660 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1661 }
1662
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1663 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1664 {
1665 unsigned long flags;
1666
1667 if (msg->parent) {
1668 spin_lock_irqsave(&msg->parent->lock, flags);
1669 list_add_tail(&msg->list, &msg->parent->head);
1670 spin_unlock_irqrestore(&msg->parent->lock, flags);
1671 } else {
1672 mlx5_free_cmd_msg(dev, msg);
1673 }
1674 }
1675
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1676 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1677 {
1678 struct mlx5_cmd *cmd = &dev->cmd;
1679 struct mlx5_cmd_work_ent *ent;
1680 mlx5_cmd_cbk_t callback;
1681 void *context;
1682 int err;
1683 int i;
1684 s64 ds;
1685 struct mlx5_cmd_stats *stats;
1686 unsigned long flags;
1687 unsigned long vector;
1688
1689 /* there can be at most 32 command queues */
1690 vector = vec & 0xffffffff;
1691 for (i = 0; i < (1 << cmd->vars.log_sz); i++) {
1692 if (test_bit(i, &vector)) {
1693 ent = cmd->ent_arr[i];
1694
1695 /* if we already completed the command, ignore it */
1696 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1697 &ent->state)) {
1698 /* only real completion can free the cmd slot */
1699 if (!forced) {
1700 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1701 ent->idx);
1702 cmd_ent_put(ent);
1703 }
1704 continue;
1705 }
1706
1707 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1708 cmd_ent_put(ent); /* timeout work was canceled */
1709
1710 if (!forced || /* Real FW completion */
1711 mlx5_cmd_is_down(dev) || /* No real FW completion is expected */
1712 !opcode_allowed(cmd, ent->op))
1713 cmd_ent_put(ent);
1714
1715 ent->ts2 = ktime_get_ns();
1716 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1717 dump_command(dev, ent, 0);
1718
1719 if (vec & MLX5_TRIGGERED_CMD_COMP)
1720 ent->ret = -ENXIO;
1721
1722 if (!ent->ret) { /* Command completed by FW */
1723 if (!cmd->checksum_disabled)
1724 ent->ret = verify_signature(ent);
1725
1726 ent->status = ent->lay->status_own >> 1;
1727
1728 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1729 ent->ret, deliv_status_to_str(ent->status), ent->status);
1730 }
1731
1732 if (ent->callback) {
1733 ds = ent->ts2 - ent->ts1;
1734 stats = xa_load(&cmd->stats, ent->op);
1735 if (stats) {
1736 spin_lock_irqsave(&stats->lock, flags);
1737 stats->sum += ds;
1738 ++stats->n;
1739 spin_unlock_irqrestore(&stats->lock, flags);
1740 }
1741
1742 callback = ent->callback;
1743 context = ent->context;
1744 err = ent->ret ? : ent->status;
1745 if (err > 0) /* Failed in FW, command didn't execute */
1746 err = deliv_status_to_err(err);
1747
1748 if (!err)
1749 err = mlx5_copy_from_msg(ent->uout,
1750 ent->out,
1751 ent->uout_size);
1752
1753 mlx5_free_cmd_msg(dev, ent->out);
1754 free_msg(dev, ent->in);
1755
1756 /* final consumer is done, release ent */
1757 cmd_ent_put(ent);
1758 callback(err, context);
1759 } else {
1760 /* release wait_func() so mlx5_cmd_invoke()
1761 * can make the final ent_put()
1762 */
1763 complete(&ent->done);
1764 }
1765 }
1766 }
1767 }
1768
1769 #define MLX5_MAX_MANAGE_PAGES_CMD_ENT 1
1770 #define MLX5_CMD_MASK ((1UL << (cmd->vars.max_reg_cmds + \
1771 MLX5_MAX_MANAGE_PAGES_CMD_ENT)) - 1)
1772
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1773 static void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1774 {
1775 struct mlx5_cmd *cmd = &dev->cmd;
1776 unsigned long bitmask;
1777 unsigned long flags;
1778 u64 vector;
1779 int i;
1780
1781 /* wait for pending handlers to complete */
1782 mlx5_eq_synchronize_cmd_irq(dev);
1783 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1784 vector = ~dev->cmd.vars.bitmask & MLX5_CMD_MASK;
1785 if (!vector)
1786 goto no_trig;
1787
1788 bitmask = vector;
1789 /* we must increment the allocated entries refcount before triggering the completions
1790 * to guarantee pending commands will not get freed in the meanwhile.
1791 * For that reason, it also has to be done inside the alloc_lock.
1792 */
1793 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1794 cmd_ent_get(cmd->ent_arr[i]);
1795 vector |= MLX5_TRIGGERED_CMD_COMP;
1796 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1797
1798 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1799 mlx5_cmd_comp_handler(dev, vector, true);
1800 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1801 cmd_ent_put(cmd->ent_arr[i]);
1802 return;
1803
1804 no_trig:
1805 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1806 }
1807
mlx5_cmd_flush(struct mlx5_core_dev * dev)1808 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1809 {
1810 struct mlx5_cmd *cmd = &dev->cmd;
1811 int i;
1812
1813 for (i = 0; i < cmd->vars.max_reg_cmds; i++) {
1814 while (down_trylock(&cmd->vars.sem)) {
1815 mlx5_cmd_trigger_completions(dev);
1816 cond_resched();
1817 }
1818 }
1819
1820 while (down_trylock(&cmd->vars.pages_sem)) {
1821 mlx5_cmd_trigger_completions(dev);
1822 cond_resched();
1823 }
1824
1825 /* Unlock cmdif */
1826 up(&cmd->vars.pages_sem);
1827 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1828 up(&cmd->vars.sem);
1829 }
1830
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1831 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1832 gfp_t gfp)
1833 {
1834 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1835 struct cmd_msg_cache *ch = NULL;
1836 struct mlx5_cmd *cmd = &dev->cmd;
1837 int i;
1838
1839 if (in_size <= 16)
1840 goto cache_miss;
1841
1842 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
1843 ch = &cmd->cache[i];
1844 if (in_size > ch->max_inbox_size)
1845 continue;
1846 spin_lock_irq(&ch->lock);
1847 if (list_empty(&ch->head)) {
1848 spin_unlock_irq(&ch->lock);
1849 continue;
1850 }
1851 msg = list_entry(ch->head.next, typeof(*msg), list);
1852 /* For cached lists, we must explicitly state what is
1853 * the real size
1854 */
1855 msg->len = in_size;
1856 list_del(&msg->list);
1857 spin_unlock_irq(&ch->lock);
1858 break;
1859 }
1860
1861 if (!IS_ERR(msg))
1862 return msg;
1863
1864 cache_miss:
1865 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1866 return msg;
1867 }
1868
is_manage_pages(void * in)1869 static int is_manage_pages(void *in)
1870 {
1871 return in_to_opcode(in) == MLX5_CMD_OP_MANAGE_PAGES;
1872 }
1873
1874 /* Notes:
1875 * 1. Callback functions may not sleep
1876 * 2. Page queue commands do not support asynchrous completion
1877 */
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1878 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1879 int out_size, mlx5_cmd_cbk_t callback, void *context,
1880 bool force_polling)
1881 {
1882 struct mlx5_cmd_msg *inb, *outb;
1883 u16 opcode = in_to_opcode(in);
1884 bool throttle_op;
1885 int pages_queue;
1886 gfp_t gfp;
1887 u8 token;
1888 int err;
1889
1890 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode))
1891 return -ENXIO;
1892
1893 throttle_op = mlx5_cmd_is_throttle_opcode(opcode);
1894 if (throttle_op) {
1895 if (callback) {
1896 if (down_trylock(&dev->cmd.vars.throttle_sem))
1897 return -EBUSY;
1898 } else {
1899 down(&dev->cmd.vars.throttle_sem);
1900 }
1901 }
1902
1903 pages_queue = is_manage_pages(in);
1904 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1905
1906 inb = alloc_msg(dev, in_size, gfp);
1907 if (IS_ERR(inb)) {
1908 err = PTR_ERR(inb);
1909 goto out_up;
1910 }
1911
1912 token = alloc_token(&dev->cmd);
1913
1914 err = mlx5_copy_to_msg(inb, in, in_size, token);
1915 if (err) {
1916 mlx5_core_warn(dev, "err %d\n", err);
1917 goto out_in;
1918 }
1919
1920 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1921 if (IS_ERR(outb)) {
1922 err = PTR_ERR(outb);
1923 goto out_in;
1924 }
1925
1926 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1927 pages_queue, token, force_polling);
1928 if (callback)
1929 return err;
1930
1931 if (err > 0) /* Failed in FW, command didn't execute */
1932 err = deliv_status_to_err(err);
1933
1934 if (err)
1935 goto out_out;
1936
1937 /* command completed by FW */
1938 err = mlx5_copy_from_msg(out, outb, out_size);
1939 out_out:
1940 mlx5_free_cmd_msg(dev, outb);
1941 out_in:
1942 free_msg(dev, inb);
1943 out_up:
1944 if (throttle_op)
1945 up(&dev->cmd.vars.throttle_sem);
1946 return err;
1947 }
1948
mlx5_cmd_err_trace(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)1949 static void mlx5_cmd_err_trace(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
1950 {
1951 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1952 u8 status = MLX5_GET(mbox_out, out, status);
1953
1954 trace_mlx5_cmd(mlx5_command_str(opcode), opcode, op_mod,
1955 cmd_status_str(status), status, syndrome,
1956 cmd_status_to_err(status));
1957 }
1958
cmd_status_log(struct mlx5_core_dev * dev,u16 opcode,u8 status,u32 syndrome,int err)1959 static void cmd_status_log(struct mlx5_core_dev *dev, u16 opcode, u8 status,
1960 u32 syndrome, int err)
1961 {
1962 const char *namep = mlx5_command_str(opcode);
1963 struct mlx5_cmd_stats *stats;
1964 unsigned long flags;
1965
1966 if (!err || !(strcmp(namep, "unknown command opcode")))
1967 return;
1968
1969 stats = xa_load(&dev->cmd.stats, opcode);
1970 if (!stats)
1971 return;
1972 spin_lock_irqsave(&stats->lock, flags);
1973 stats->failed++;
1974 if (err < 0)
1975 stats->last_failed_errno = -err;
1976 if (err == -EREMOTEIO) {
1977 stats->failed_mbox_status++;
1978 stats->last_failed_mbox_status = status;
1979 stats->last_failed_syndrome = syndrome;
1980 }
1981 spin_unlock_irqrestore(&stats->lock, flags);
1982 }
1983
1984 /* preserve -EREMOTEIO for outbox.status != OK, otherwise return err as is */
cmd_status_err(struct mlx5_core_dev * dev,int err,u16 opcode,u16 op_mod,void * out)1985 static int cmd_status_err(struct mlx5_core_dev *dev, int err, u16 opcode, u16 op_mod, void *out)
1986 {
1987 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1988 u8 status = MLX5_GET(mbox_out, out, status);
1989
1990 if (err == -EREMOTEIO) /* -EREMOTEIO is preserved */
1991 err = -EIO;
1992
1993 if (!err && status != MLX5_CMD_STAT_OK) {
1994 err = -EREMOTEIO;
1995 mlx5_cmd_err_trace(dev, opcode, op_mod, out);
1996 }
1997
1998 cmd_status_log(dev, opcode, status, syndrome, err);
1999 return err;
2000 }
2001
2002 /**
2003 * mlx5_cmd_do - Executes a fw command, wait for completion.
2004 * Unlike mlx5_cmd_exec, this function will not translate or intercept
2005 * outbox.status and will return -EREMOTEIO when
2006 * outbox.status != MLX5_CMD_STAT_OK
2007 *
2008 * @dev: mlx5 core device
2009 * @in: inbox mlx5_ifc command buffer
2010 * @in_size: inbox buffer size
2011 * @out: outbox mlx5_ifc buffer
2012 * @out_size: outbox size
2013 *
2014 * @return:
2015 * -EREMOTEIO : Command executed by FW, outbox.status != MLX5_CMD_STAT_OK.
2016 * Caller must check FW outbox status.
2017 * 0 : Command execution successful, outbox.status == MLX5_CMD_STAT_OK.
2018 * < 0 : Command execution couldn't be performed by firmware or driver
2019 */
mlx5_cmd_do(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2020 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size)
2021 {
2022 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
2023 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2024 u16 opcode = in_to_opcode(in);
2025
2026 return cmd_status_err(dev, err, opcode, op_mod, out);
2027 }
2028 EXPORT_SYMBOL(mlx5_cmd_do);
2029
2030 /**
2031 * mlx5_cmd_exec - Executes a fw command, wait for completion
2032 *
2033 * @dev: mlx5 core device
2034 * @in: inbox mlx5_ifc command buffer
2035 * @in_size: inbox buffer size
2036 * @out: outbox mlx5_ifc buffer
2037 * @out_size: outbox size
2038 *
2039 * @return: 0 if no error, FW command execution was successful
2040 * and outbox status is ok.
2041 */
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2042 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
2043 int out_size)
2044 {
2045 int err = mlx5_cmd_do(dev, in, in_size, out, out_size);
2046
2047 return mlx5_cmd_check(dev, err, in, out);
2048 }
2049 EXPORT_SYMBOL(mlx5_cmd_exec);
2050
2051 /**
2052 * mlx5_cmd_exec_polling - Executes a fw command, poll for completion
2053 * Needed for driver force teardown, when command completion EQ
2054 * will not be available to complete the command
2055 *
2056 * @dev: mlx5 core device
2057 * @in: inbox mlx5_ifc command buffer
2058 * @in_size: inbox buffer size
2059 * @out: outbox mlx5_ifc buffer
2060 * @out_size: outbox size
2061 *
2062 * @return: 0 if no error, FW command execution was successful
2063 * and outbox status is ok.
2064 */
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2065 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
2066 void *out, int out_size)
2067 {
2068 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
2069 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2070 u16 opcode = in_to_opcode(in);
2071
2072 err = cmd_status_err(dev, err, opcode, op_mod, out);
2073 return mlx5_cmd_check(dev, err, in, out);
2074 }
2075 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
2076
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)2077 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
2078 struct mlx5_async_ctx *ctx)
2079 {
2080 ctx->dev = dev;
2081 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
2082 atomic_set(&ctx->num_inflight, 1);
2083 init_completion(&ctx->inflight_done);
2084 }
2085 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
2086
2087 /**
2088 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
2089 * @ctx: The ctx to clean
2090 *
2091 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
2092 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
2093 * the call mlx5_cleanup_async_ctx().
2094 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)2095 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
2096 {
2097 if (!atomic_dec_and_test(&ctx->num_inflight))
2098 wait_for_completion(&ctx->inflight_done);
2099 }
2100 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
2101
mlx5_cmd_exec_cb_handler(int status,void * _work)2102 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
2103 {
2104 struct mlx5_async_work *work = _work;
2105 struct mlx5_async_ctx *ctx;
2106 struct mlx5_core_dev *dev;
2107 u16 opcode;
2108
2109 ctx = work->ctx;
2110 dev = ctx->dev;
2111 opcode = work->opcode;
2112 status = cmd_status_err(dev, status, work->opcode, work->op_mod, work->out);
2113 work->user_callback(status, work);
2114 /* Can't access "work" from this point on. It could have been freed in
2115 * the callback.
2116 */
2117 if (mlx5_cmd_is_throttle_opcode(opcode))
2118 up(&dev->cmd.vars.throttle_sem);
2119 if (atomic_dec_and_test(&ctx->num_inflight))
2120 complete(&ctx->inflight_done);
2121 }
2122
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)2123 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
2124 void *out, int out_size, mlx5_async_cbk_t callback,
2125 struct mlx5_async_work *work)
2126 {
2127 int ret;
2128
2129 work->ctx = ctx;
2130 work->user_callback = callback;
2131 work->opcode = in_to_opcode(in);
2132 work->op_mod = MLX5_GET(mbox_in, in, op_mod);
2133 work->out = out;
2134 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
2135 return -EIO;
2136 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
2137 mlx5_cmd_exec_cb_handler, work, false);
2138 if (ret && atomic_dec_and_test(&ctx->num_inflight))
2139 complete(&ctx->inflight_done);
2140
2141 return ret;
2142 }
2143 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
2144
mlx5_cmd_allow_other_vhca_access(struct mlx5_core_dev * dev,struct mlx5_cmd_allow_other_vhca_access_attr * attr)2145 int mlx5_cmd_allow_other_vhca_access(struct mlx5_core_dev *dev,
2146 struct mlx5_cmd_allow_other_vhca_access_attr *attr)
2147 {
2148 u32 out[MLX5_ST_SZ_DW(allow_other_vhca_access_out)] = {};
2149 u32 in[MLX5_ST_SZ_DW(allow_other_vhca_access_in)] = {};
2150 void *key;
2151
2152 MLX5_SET(allow_other_vhca_access_in,
2153 in, opcode, MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS);
2154 MLX5_SET(allow_other_vhca_access_in,
2155 in, object_type_to_be_accessed, attr->obj_type);
2156 MLX5_SET(allow_other_vhca_access_in,
2157 in, object_id_to_be_accessed, attr->obj_id);
2158
2159 key = MLX5_ADDR_OF(allow_other_vhca_access_in, in, access_key);
2160 memcpy(key, attr->access_key, sizeof(attr->access_key));
2161
2162 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
2163 }
2164
mlx5_cmd_alias_obj_create(struct mlx5_core_dev * dev,struct mlx5_cmd_alias_obj_create_attr * alias_attr,u32 * obj_id)2165 int mlx5_cmd_alias_obj_create(struct mlx5_core_dev *dev,
2166 struct mlx5_cmd_alias_obj_create_attr *alias_attr,
2167 u32 *obj_id)
2168 {
2169 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {};
2170 u32 in[MLX5_ST_SZ_DW(create_alias_obj_in)] = {};
2171 void *param;
2172 void *attr;
2173 void *key;
2174 int ret;
2175
2176 attr = MLX5_ADDR_OF(create_alias_obj_in, in, hdr);
2177 MLX5_SET(general_obj_in_cmd_hdr,
2178 attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2179 MLX5_SET(general_obj_in_cmd_hdr,
2180 attr, obj_type, alias_attr->obj_type);
2181 param = MLX5_ADDR_OF(general_obj_in_cmd_hdr, in, op_param);
2182 MLX5_SET(general_obj_create_param, param, alias_object, 1);
2183
2184 attr = MLX5_ADDR_OF(create_alias_obj_in, in, alias_ctx);
2185 MLX5_SET(alias_context, attr, vhca_id_to_be_accessed, alias_attr->vhca_id);
2186 MLX5_SET(alias_context, attr, object_id_to_be_accessed, alias_attr->obj_id);
2187
2188 key = MLX5_ADDR_OF(alias_context, attr, access_key);
2189 memcpy(key, alias_attr->access_key, sizeof(alias_attr->access_key));
2190
2191 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
2192 if (ret)
2193 return ret;
2194
2195 *obj_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2196
2197 return 0;
2198 }
2199
mlx5_cmd_alias_obj_destroy(struct mlx5_core_dev * dev,u32 obj_id,u16 obj_type)2200 int mlx5_cmd_alias_obj_destroy(struct mlx5_core_dev *dev, u32 obj_id,
2201 u16 obj_type)
2202 {
2203 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {};
2204 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {};
2205
2206 MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
2207 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type, obj_type);
2208 MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, obj_id);
2209
2210 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
2211 }
2212
destroy_msg_cache(struct mlx5_core_dev * dev)2213 static void destroy_msg_cache(struct mlx5_core_dev *dev)
2214 {
2215 struct cmd_msg_cache *ch;
2216 struct mlx5_cmd_msg *msg;
2217 struct mlx5_cmd_msg *n;
2218 int i;
2219
2220 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
2221 ch = &dev->cmd.cache[i];
2222 list_for_each_entry_safe(msg, n, &ch->head, list) {
2223 list_del(&msg->list);
2224 mlx5_free_cmd_msg(dev, msg);
2225 }
2226 }
2227 }
2228
2229 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
2230 512, 32, 16, 8, 2
2231 };
2232
2233 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
2234 16 + MLX5_CMD_DATA_BLOCK_SIZE,
2235 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
2236 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
2237 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
2238 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
2239 };
2240
create_msg_cache(struct mlx5_core_dev * dev)2241 static void create_msg_cache(struct mlx5_core_dev *dev)
2242 {
2243 struct mlx5_cmd *cmd = &dev->cmd;
2244 struct cmd_msg_cache *ch;
2245 struct mlx5_cmd_msg *msg;
2246 int i;
2247 int k;
2248
2249 /* Initialize and fill the caches with initial entries */
2250 for (k = 0; k < dev->profile.num_cmd_caches; k++) {
2251 ch = &cmd->cache[k];
2252 spin_lock_init(&ch->lock);
2253 INIT_LIST_HEAD(&ch->head);
2254 ch->num_ent = cmd_cache_num_ent[k];
2255 ch->max_inbox_size = cmd_cache_ent_size[k];
2256 for (i = 0; i < ch->num_ent; i++) {
2257 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
2258 ch->max_inbox_size, 0);
2259 if (IS_ERR(msg))
2260 break;
2261 msg->parent = ch;
2262 list_add_tail(&msg->list, &ch->head);
2263 }
2264 }
2265 }
2266
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2267 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2268 {
2269 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
2270 &cmd->alloc_dma, GFP_KERNEL);
2271 if (!cmd->cmd_alloc_buf)
2272 return -ENOMEM;
2273
2274 /* make sure it is aligned to 4K */
2275 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
2276 cmd->cmd_buf = cmd->cmd_alloc_buf;
2277 cmd->dma = cmd->alloc_dma;
2278 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
2279 return 0;
2280 }
2281
2282 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
2283 cmd->alloc_dma);
2284 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
2285 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
2286 &cmd->alloc_dma, GFP_KERNEL);
2287 if (!cmd->cmd_alloc_buf)
2288 return -ENOMEM;
2289
2290 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
2291 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
2292 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2293 return 0;
2294 }
2295
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2296 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2297 {
2298 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2299 cmd->alloc_dma);
2300 }
2301
cmdif_rev(struct mlx5_core_dev * dev)2302 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2303 {
2304 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2305 }
2306
mlx5_cmd_init(struct mlx5_core_dev * dev)2307 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2308 {
2309 struct mlx5_cmd *cmd = &dev->cmd;
2310
2311 cmd->checksum_disabled = 1;
2312
2313 spin_lock_init(&cmd->alloc_lock);
2314 spin_lock_init(&cmd->token_lock);
2315
2316 set_wqname(dev);
2317 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2318 if (!cmd->wq) {
2319 mlx5_core_err(dev, "failed to create command workqueue\n");
2320 return -ENOMEM;
2321 }
2322
2323 mlx5_cmdif_debugfs_init(dev);
2324
2325 return 0;
2326 }
2327
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2328 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2329 {
2330 struct mlx5_cmd *cmd = &dev->cmd;
2331
2332 mlx5_cmdif_debugfs_cleanup(dev);
2333 destroy_workqueue(cmd->wq);
2334 }
2335
mlx5_cmd_enable(struct mlx5_core_dev * dev)2336 int mlx5_cmd_enable(struct mlx5_core_dev *dev)
2337 {
2338 int size = sizeof(struct mlx5_cmd_prot_block);
2339 int align = roundup_pow_of_two(size);
2340 struct mlx5_cmd *cmd = &dev->cmd;
2341 u32 cmd_h, cmd_l;
2342 int err;
2343
2344 memset(&cmd->vars, 0, sizeof(cmd->vars));
2345 cmd->vars.cmdif_rev = cmdif_rev(dev);
2346 if (cmd->vars.cmdif_rev != CMD_IF_REV) {
2347 mlx5_core_err(dev,
2348 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2349 CMD_IF_REV, cmd->vars.cmdif_rev);
2350 return -EINVAL;
2351 }
2352
2353 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2354 cmd->vars.log_sz = cmd_l >> 4 & 0xf;
2355 cmd->vars.log_stride = cmd_l & 0xf;
2356 if (1 << cmd->vars.log_sz > MLX5_MAX_COMMANDS) {
2357 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2358 1 << cmd->vars.log_sz);
2359 return -EINVAL;
2360 }
2361
2362 if (cmd->vars.log_sz + cmd->vars.log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2363 mlx5_core_err(dev, "command queue size overflow\n");
2364 return -EINVAL;
2365 }
2366
2367 cmd->state = MLX5_CMDIF_STATE_DOWN;
2368 cmd->vars.max_reg_cmds = (1 << cmd->vars.log_sz) - 1;
2369 cmd->vars.bitmask = MLX5_CMD_MASK;
2370
2371 sema_init(&cmd->vars.sem, cmd->vars.max_reg_cmds);
2372 sema_init(&cmd->vars.pages_sem, 1);
2373 sema_init(&cmd->vars.throttle_sem, DIV_ROUND_UP(cmd->vars.max_reg_cmds, 2));
2374
2375 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2376 if (!cmd->pool)
2377 return -ENOMEM;
2378
2379 err = alloc_cmd_page(dev, cmd);
2380 if (err)
2381 goto err_free_pool;
2382
2383 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2384 cmd_l = (u32)(cmd->dma);
2385 if (cmd_l & 0xfff) {
2386 mlx5_core_err(dev, "invalid command queue address\n");
2387 err = -ENOMEM;
2388 goto err_cmd_page;
2389 }
2390
2391 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2392 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2393
2394 /* Make sure firmware sees the complete address before we proceed */
2395 wmb();
2396
2397 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2398
2399 cmd->mode = CMD_MODE_POLLING;
2400 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2401
2402 create_msg_cache(dev);
2403 create_debugfs_files(dev);
2404
2405 return 0;
2406
2407 err_cmd_page:
2408 free_cmd_page(dev, cmd);
2409 err_free_pool:
2410 dma_pool_destroy(cmd->pool);
2411 return err;
2412 }
2413
mlx5_cmd_disable(struct mlx5_core_dev * dev)2414 void mlx5_cmd_disable(struct mlx5_core_dev *dev)
2415 {
2416 struct mlx5_cmd *cmd = &dev->cmd;
2417
2418 flush_workqueue(cmd->wq);
2419 clean_debug_files(dev);
2420 destroy_msg_cache(dev);
2421 free_cmd_page(dev, cmd);
2422 dma_pool_destroy(cmd->pool);
2423 }
2424
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2425 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2426 enum mlx5_cmdif_state cmdif_state)
2427 {
2428 dev->cmd.state = cmdif_state;
2429 }
2430