1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 4 Copyright Echo Digital Audio Corporation (c) 1998 - 2004 5 All rights reserved 6 www.echoaudio.com 7 8 This file is part of Echo Digital Audio's generic driver library. 9 ************************************************************************* 10 11 Translation from C++ and adaptation for use in ALSA-Driver 12 were made by Giuliano Pochini <pochini@shiny.it> 13 14 ****************************************************************************/ 15 16 #ifndef _ECHO_DSP_ 17 #define _ECHO_DSP_ 18 19 20 /**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/ 21 #if defined(ECHOGALS_FAMILY) 22 23 #define NUM_ASIC_TESTS 5 24 #define READ_DSP_TIMEOUT 1000000L /* one second */ 25 26 /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/ 27 #elif defined(ECHO24_FAMILY) 28 29 #define DSP_56361 /* Some Echo24 cards use the 56361 DSP */ 30 #define READ_DSP_TIMEOUT 100000L /* .1 second */ 31 32 /**** 3G: Gina3G, Layla3G ****/ 33 #elif defined(ECHO3G_FAMILY) 34 35 #define DSP_56361 36 #define READ_DSP_TIMEOUT 100000L /* .1 second */ 37 #define MIN_MTC_1X_RATE 32000 38 39 /**** Indigo: Indigo, Indigo IO, Indigo DJ ****/ 40 #elif defined(INDIGO_FAMILY) 41 42 #define DSP_56361 43 #define READ_DSP_TIMEOUT 100000L /* .1 second */ 44 45 #else 46 47 #error No family is defined 48 49 #endif 50 51 52 53 /* 54 * 55 * Max inputs and outputs 56 * 57 */ 58 59 #define DSP_MAXAUDIOINPUTS 16 /* Max audio input channels */ 60 #define DSP_MAXAUDIOOUTPUTS 16 /* Max audio output channels */ 61 #define DSP_MAXPIPES 32 /* Max total pipes (input + output) */ 62 63 64 /* 65 * 66 * These are the offsets for the memory-mapped DSP registers; the DSP base 67 * address is treated as the start of a u32 array. 68 */ 69 70 #define CHI32_CONTROL_REG 4 71 #define CHI32_STATUS_REG 5 72 #define CHI32_VECTOR_REG 6 73 #define CHI32_DATA_REG 7 74 75 76 /* 77 * 78 * Interesting bits within the DSP registers 79 * 80 */ 81 82 #define CHI32_VECTOR_BUSY 0x00000001 83 #define CHI32_STATUS_REG_HF3 0x00000008 84 #define CHI32_STATUS_REG_HF4 0x00000010 85 #define CHI32_STATUS_REG_HF5 0x00000020 86 #define CHI32_STATUS_HOST_READ_FULL 0x00000004 87 #define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002 88 #define CHI32_STATUS_IRQ 0x00000040 89 90 91 /* 92 * 93 * DSP commands sent via slave mode; these are sent to the DSP by write_dsp() 94 * 95 */ 96 97 #define DSP_FNC_SET_COMMPAGE_ADDR 0x02 98 #define DSP_FNC_LOAD_LAYLA_ASIC 0xa0 99 #define DSP_FNC_LOAD_GINA24_ASIC 0xa0 100 #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0 101 #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0 102 #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1 103 #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1 104 #define DSP_FNC_LOAD_3G_ASIC 0xa0 105 106 107 /* 108 * 109 * Defines to handle the MIDI input state engine; these are used to properly 110 * extract MIDI time code bytes and their timestamps from the MIDI input stream. 111 * 112 */ 113 114 #define MIDI_IN_STATE_NORMAL 0 115 #define MIDI_IN_STATE_TS_HIGH 1 116 #define MIDI_IN_STATE_TS_LOW 2 117 #define MIDI_IN_STATE_F1_DATA 3 118 #define MIDI_IN_SKIP_DATA (-1) 119 120 121 /*---------------------------------------------------------------------------- 122 123 Setting the sample rates on Layla24 is somewhat schizophrenic. 124 125 For standard rates, it works exactly like Mona and Gina24. That is, for 126 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the 127 appropriate bits in the control register and write the control register. 128 129 In order to support MIDI time code sync (and possibly SMPTE LTC sync in 130 the future), Layla24 also has "continuous sample rate mode". In this mode, 131 Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or 132 50 to 100 kHz inclusive for double speed mode. 133 134 To use continuous mode: 135 136 -Set the clock select bits in the control register to 0xe (see the #define 137 below) 138 139 -Set double-speed mode if you want to use sample rates above 50 kHz 140 141 -Write the control register as you would normally 142 143 -Now, you need to set the frequency register. First, you need to determine the 144 value for the frequency register. This is given by the following formula: 145 146 frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2 147 148 Note the #define below for the magic number 149 150 -Wait for the DSP handshake 151 -Write the frequency_reg value to the .SampleRate field of the comm page 152 -Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h) 153 154 Once you have set the control register up for continuous mode, you can just 155 write the frequency register to change the sample rate. This could be 156 used for MIDI time code sync. For MTC sync, the control register is set for 157 continuous mode. The driver then just keeps writing the 158 SET_LAYLA24_FREQUENCY_REG command. 159 160 -----------------------------------------------------------------------------*/ 161 162 #define LAYLA24_MAGIC_NUMBER 677376000 163 #define LAYLA24_CONTINUOUS_CLOCK 0x000e 164 165 166 /* 167 * 168 * DSP vector commands 169 * 170 */ 171 172 #define DSP_VC_RESET 0x80ff 173 174 #ifndef DSP_56361 175 176 #define DSP_VC_ACK_INT 0x8073 177 #define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */ 178 #define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */ 179 #define DSP_VC_METERS_ON 0x0079 180 #define DSP_VC_METERS_OFF 0x007b 181 #define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */ 182 #define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */ 183 #define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */ 184 #define DSP_VC_TEST_ASIC 0x00eb 185 #define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */ 186 #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */ 187 #define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */ 188 #define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */ 189 #define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */ 190 #define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */ 191 #define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */ 192 #define DSP_VC_GO_COMATOSE 0x00f9 193 194 #else /* !DSP_56361 */ 195 196 /* Vector commands for families that use either the 56301 or 56361 */ 197 #define DSP_VC_ACK_INT 0x80F5 198 #define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */ 199 #define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */ 200 #define DSP_VC_METERS_ON 0x00EF 201 #define DSP_VC_METERS_OFF 0x00F1 202 #define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */ 203 #define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */ 204 #define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */ 205 #define DSP_VC_TEST_ASIC 0x00ED 206 #define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */ 207 #define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */ 208 #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */ 209 #define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */ 210 #define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */ 211 #define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */ 212 #define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */ 213 #define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */ 214 #define DSP_VC_GO_COMATOSE 0x00d9 215 216 #endif /* !DSP_56361 */ 217 218 219 /* 220 * 221 * Timeouts 222 * 223 */ 224 225 #define HANDSHAKE_TIMEOUT 20000 /* send_vector command timeout (20ms) */ 226 #define VECTOR_BUSY_TIMEOUT 100000 /* 100ms */ 227 #define MIDI_OUT_DELAY_USEC 2000 /* How long to wait after MIDI fills up */ 228 229 230 /* 231 * 232 * Flags for .Flags field in the comm page 233 * 234 */ 235 236 #define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */ 237 #define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit 238 * in the S/PDIF out status 239 * bits. Clear this flag for 240 * audio data; 241 * set it for AC3 or WMA or 242 * some such */ 243 #define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */ 244 245 246 /* 247 * 248 * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia 249 * 250 */ 251 252 #define GLDM_CLOCK_DETECT_BIT_WORD 0x0002 253 #define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004 254 #define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008 255 #define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010 256 257 258 /* 259 * 260 * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24 261 * 262 */ 263 264 #define GML_CLOCK_DETECT_BIT_WORD96 0x0002 265 #define GML_CLOCK_DETECT_BIT_WORD48 0x0004 266 #define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008 267 #define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010 268 #define GML_CLOCK_DETECT_BIT_WORD (GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48) 269 #define GML_CLOCK_DETECT_BIT_SPDIF (GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96) 270 #define GML_CLOCK_DETECT_BIT_ESYNC 0x0020 271 #define GML_CLOCK_DETECT_BIT_ADAT 0x0040 272 273 274 /* 275 * 276 * Layla clock numbers to send to DSP 277 * 278 */ 279 280 #define LAYLA20_CLOCK_INTERNAL 0 281 #define LAYLA20_CLOCK_SPDIF 1 282 #define LAYLA20_CLOCK_WORD 2 283 #define LAYLA20_CLOCK_SUPER 3 284 285 286 /* 287 * 288 * Gina/Darla clock states 289 * 290 */ 291 292 #define GD_CLOCK_NOCHANGE 0 293 #define GD_CLOCK_44 1 294 #define GD_CLOCK_48 2 295 #define GD_CLOCK_SPDIFIN 3 296 #define GD_CLOCK_UNDEF 0xff 297 298 299 /* 300 * 301 * Gina/Darla S/PDIF status bits 302 * 303 */ 304 305 #define GD_SPDIF_STATUS_NOCHANGE 0 306 #define GD_SPDIF_STATUS_44 1 307 #define GD_SPDIF_STATUS_48 2 308 #define GD_SPDIF_STATUS_UNDEF 0xff 309 310 311 /* 312 * 313 * Layla20 output clocks 314 * 315 */ 316 317 #define LAYLA20_OUTPUT_CLOCK_SUPER 0 318 #define LAYLA20_OUTPUT_CLOCK_WORD 1 319 320 321 /**************************************************************************** 322 323 Magic constants for the Darla24 hardware 324 325 ****************************************************************************/ 326 327 #define GD24_96000 0x0 328 #define GD24_48000 0x1 329 #define GD24_44100 0x2 330 #define GD24_32000 0x3 331 #define GD24_22050 0x4 332 #define GD24_16000 0x5 333 #define GD24_11025 0x6 334 #define GD24_8000 0x7 335 #define GD24_88200 0x8 336 #define GD24_EXT_SYNC 0x9 337 338 339 /* 340 * 341 * Return values from the DSP when ASIC is loaded 342 * 343 */ 344 345 #define ASIC_ALREADY_LOADED 0x1 346 #define ASIC_NOT_LOADED 0x0 347 348 349 /* 350 * 351 * DSP Audio formats 352 * 353 * These are the audio formats that the DSP can transfer 354 * via input and output pipes. LE means little-endian, 355 * BE means big-endian. 356 * 357 * DSP_AUDIOFORM_MS_8 358 * 359 * 8-bit mono unsigned samples. For playback, 360 * mono data is duplicated out the left and right channels 361 * of the output bus. The "MS" part of the name 362 * means mono->stereo. 363 * 364 * DSP_AUDIOFORM_MS_16LE 365 * 366 * 16-bit signed little-endian mono samples. Playback works 367 * like the previous code. 368 * 369 * DSP_AUDIOFORM_MS_24LE 370 * 371 * 24-bit signed little-endian mono samples. Data is packed 372 * three bytes per sample; if you had two samples 0x112233 and 0x445566 373 * they would be stored in memory like this: 33 22 11 66 55 44. 374 * 375 * DSP_AUDIOFORM_MS_32LE 376 * 377 * 24-bit signed little-endian mono samples in a 32-bit 378 * container. In other words, each sample is a 32-bit signed 379 * integer, where the actual audio data is left-justified 380 * in the 32 bits and only the 24 most significant bits are valid. 381 * 382 * DSP_AUDIOFORM_SS_8 383 * DSP_AUDIOFORM_SS_16LE 384 * DSP_AUDIOFORM_SS_24LE 385 * DSP_AUDIOFORM_SS_32LE 386 * 387 * Like the previous ones, except now with stereo interleaved 388 * data. "SS" means stereo->stereo. 389 * 390 * DSP_AUDIOFORM_MM_32LE 391 * 392 * Similar to DSP_AUDIOFORM_MS_32LE, except that the mono 393 * data is not duplicated out both the left and right outputs. 394 * This mode is used by the ASIO driver. Here, "MM" means 395 * mono->mono. 396 * 397 * DSP_AUDIOFORM_MM_32BE 398 * 399 * Just like DSP_AUDIOFORM_MM_32LE, but now the data is 400 * in big-endian format. 401 * 402 */ 403 404 #define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */ 405 #define DSP_AUDIOFORM_MS_16LE 1 /* 16 bit mono */ 406 #define DSP_AUDIOFORM_MS_24LE 2 /* 24 bit mono */ 407 #define DSP_AUDIOFORM_MS_32LE 3 /* 32 bit mono */ 408 #define DSP_AUDIOFORM_SS_8 4 /* 8 bit stereo */ 409 #define DSP_AUDIOFORM_SS_16LE 5 /* 16 bit stereo */ 410 #define DSP_AUDIOFORM_SS_24LE 6 /* 24 bit stereo */ 411 #define DSP_AUDIOFORM_SS_32LE 7 /* 32 bit stereo */ 412 #define DSP_AUDIOFORM_MM_32LE 8 /* 32 bit mono->mono little-endian */ 413 #define DSP_AUDIOFORM_MM_32BE 9 /* 32 bit mono->mono big-endian */ 414 #define DSP_AUDIOFORM_SS_32BE 10 /* 32 bit stereo big endian */ 415 #define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */ 416 417 418 /* 419 * 420 * Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20 421 * do not support super interleave. 422 * 423 * 16 bit, 24 bit, and 32 bit little endian samples are supported for super 424 * interleave. The interleave factor must be even. 16 - way interleave is the 425 * current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16. 426 * 427 * The actual format code is derived by taking the define below and or-ing with 428 * the interleave factor. So, 32 bit interleave by 6 is 0x86 and 429 * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50. 430 * 431 */ 432 433 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40 434 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0 435 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80 436 437 438 /* 439 * 440 * Gina24, Mona, and Layla24 control register defines 441 * 442 */ 443 444 #define GML_CONVERTER_ENABLE 0x0010 445 #define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, 446 consumer == 0 */ 447 #define GML_SPDIF_SAMPLE_RATE0 0x0040 448 #define GML_SPDIF_SAMPLE_RATE1 0x0080 449 #define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, 450 0 == one channel */ 451 #define GML_SPDIF_NOT_AUDIO 0x0200 452 #define GML_SPDIF_COPY_PERMIT 0x0400 453 #define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ 454 #define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */ 455 #define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */ 456 #define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode, 457 * 0 == RCA or optical mode */ 458 #define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, 459 0 == single speed */ 460 461 #define GML_DIGITAL_IN_AUTO_MUTE 0x800000 462 463 #define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE) 464 #define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE) 465 #define GML_48KHZ 0x2 466 #define GML_44KHZ 0x3 467 #define GML_32KHZ 0x4 468 #define GML_22KHZ 0x5 469 #define GML_16KHZ 0x6 470 #define GML_11KHZ 0x7 471 #define GML_8KHZ 0x8 472 #define GML_SPDIF_CLOCK 0x9 473 #define GML_ADAT_CLOCK 0xA 474 #define GML_WORD_CLOCK 0xB 475 #define GML_ESYNC_CLOCK 0xC 476 #define GML_ESYNCx2_CLOCK 0xD 477 478 #define GML_CLOCK_CLEAR_MASK 0xffffbff0 479 #define GML_SPDIF_RATE_CLEAR_MASK (~(GML_SPDIF_SAMPLE_RATE0|GML_SPDIF_SAMPLE_RATE1)) 480 #define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff 481 #define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f 482 483 484 /* 485 * 486 * Mia sample rate and clock setting constants 487 * 488 */ 489 490 #define MIA_32000 0x0040 491 #define MIA_44100 0x0042 492 #define MIA_48000 0x0041 493 #define MIA_88200 0x0142 494 #define MIA_96000 0x0141 495 496 #define MIA_SPDIF 0x00000044 497 #define MIA_SPDIF96 0x00000144 498 499 #define MIA_MIDI_REV 1 /* Must be Mia rev 1 for MIDI support */ 500 501 502 /* 503 * 504 * 3G register bits 505 * 506 */ 507 508 #define E3G_CONVERTER_ENABLE 0x0010 509 #define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, 510 consumer == 0 */ 511 #define E3G_SPDIF_SAMPLE_RATE0 0x0040 512 #define E3G_SPDIF_SAMPLE_RATE1 0x0080 513 #define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, 514 0 == one channel */ 515 #define E3G_SPDIF_NOT_AUDIO 0x0200 516 #define E3G_SPDIF_COPY_PERMIT 0x0400 517 #define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ 518 #define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, 519 0 == single speed */ 520 #define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on, 521 0 == phantom power off */ 522 523 #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE) 524 #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE) 525 #define E3G_48KHZ 0x2 526 #define E3G_44KHZ 0x3 527 #define E3G_32KHZ 0x4 528 #define E3G_22KHZ 0x5 529 #define E3G_16KHZ 0x6 530 #define E3G_11KHZ 0x7 531 #define E3G_8KHZ 0x8 532 #define E3G_SPDIF_CLOCK 0x9 533 #define E3G_ADAT_CLOCK 0xA 534 #define E3G_WORD_CLOCK 0xB 535 #define E3G_CONTINUOUS_CLOCK 0xE 536 537 #define E3G_ADAT_MODE 0x1000 538 #define E3G_SPDIF_OPTICAL_MODE 0x2000 539 540 #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0 541 #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff 542 #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f 543 544 /* Clock detect bits reported by the DSP */ 545 #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001 546 #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002 547 #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004 548 #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004 549 #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008 550 #define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48) 551 #define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96) 552 553 /* Frequency control register */ 554 #define E3G_MAGIC_NUMBER 677376000 555 #define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2) 556 #define E3G_FREQ_REG_MAX 0xffff 557 558 /* 3G external box types */ 559 #define E3G_GINA3G_BOX_TYPE 0x00 560 #define E3G_LAYLA3G_BOX_TYPE 0x10 561 #define E3G_ASIC_NOT_LOADED 0xffff 562 #define E3G_BOX_TYPE_MASK 0xf0 563 564 /* Indigo express control register values */ 565 #define INDIGO_EXPRESS_32000 0x02 566 #define INDIGO_EXPRESS_44100 0x01 567 #define INDIGO_EXPRESS_48000 0x00 568 #define INDIGO_EXPRESS_DOUBLE_SPEED 0x10 569 #define INDIGO_EXPRESS_QUAD_SPEED 0x04 570 #define INDIGO_EXPRESS_CLOCK_MASK 0x17 571 572 573 /* 574 * 575 * Gina20 & Layla20 have input gain controls for the analog inputs; 576 * this is the magic number for the hardware that gives you 0 dB at -10. 577 * 578 */ 579 580 #define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8 581 582 583 /* 584 * 585 * Defines how much time must pass between DSP load attempts 586 * 587 */ 588 589 #define DSP_LOAD_ATTEMPT_PERIOD 1000000L /* One second */ 590 591 592 /* 593 * 594 * Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are 595 * no longer used, but the sizes must still be right for the DSP to see 596 * the comm page correctly. 597 * 598 */ 599 600 #define MONITOR_ARRAY_SIZE 0x180 601 #define VMIXER_ARRAY_SIZE 0x40 602 #define MIDI_OUT_BUFFER_SIZE 32 603 #define MIDI_IN_BUFFER_SIZE 256 604 #define MAX_PLAY_TAPS 168 605 #define MAX_REC_TAPS 192 606 #define DSP_MIDI_OUT_FIFO_SIZE 64 607 608 609 /* sg_entry is a single entry for the scatter-gather list. The array of struct 610 sg_entry struct is read by the DSP, so all values must be little-endian. */ 611 612 #define MAX_SGLIST_ENTRIES 512 613 614 struct sg_entry { 615 __le32 addr; 616 __le32 size; 617 }; 618 619 620 /**************************************************************************** 621 622 The comm page. This structure is read and written by the DSP; the 623 DSP code is a firm believer in the byte offsets written in the comments 624 at the end of each line. This structure should not be changed. 625 626 Any reads from or writes to this structure should be in little-endian format. 627 628 ****************************************************************************/ 629 630 struct comm_page { /* Base Length*/ 631 __le32 comm_size; /* size of this object 0x000 4 */ 632 __le32 flags; /* See Appendix A below 0x004 4 */ 633 __le32 unused; /* Unused entry 0x008 4 */ 634 __le32 sample_rate; /* Card sample rate in Hz 0x00c 4 */ 635 __le32 handshake; /* DSP command handshake 0x010 4 */ 636 __le32 cmd_start; /* Chs. to start mask 0x014 4 */ 637 __le32 cmd_stop; /* Chs. to stop mask 0x018 4 */ 638 __le32 cmd_reset; /* Chs. to reset mask 0x01c 4 */ 639 __le16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */ 640 struct sg_entry sglist_addr[DSP_MAXPIPES]; 641 /* Chs. Physical sglist addrs 0x060 32*8 */ 642 __le32 position[DSP_MAXPIPES]; 643 /* Positions for ea. ch. 0x160 32*4 */ 644 s8 vu_meter[DSP_MAXPIPES]; 645 /* VU meters 0x1e0 32*1 */ 646 s8 peak_meter[DSP_MAXPIPES]; 647 /* Peak meters 0x200 32*1 */ 648 s8 line_out_level[DSP_MAXAUDIOOUTPUTS]; 649 /* Output gain 0x220 16*1 */ 650 s8 line_in_level[DSP_MAXAUDIOINPUTS]; 651 /* Input gain 0x230 16*1 */ 652 s8 monitors[MONITOR_ARRAY_SIZE]; 653 /* Monitor map 0x240 0x180 */ 654 __le32 play_coeff[MAX_PLAY_TAPS]; 655 /* Gina/Darla play filters - obsolete 0x3c0 168*4 */ 656 __le32 rec_coeff[MAX_REC_TAPS]; 657 /* Gina/Darla record filters - obsolete 0x660 192*4 */ 658 __le16 midi_input[MIDI_IN_BUFFER_SIZE]; 659 /* MIDI input data transfer buffer 0x960 256*2 */ 660 u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */ 661 u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */ 662 u8 gd_resampler_state; /* Should always be 3 0xb62 1 */ 663 u8 filler2; /* 0xb63 1 */ 664 __le32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */ 665 __le16 input_clock; /* Chg. Input clock state 0xb68 2 */ 666 __le16 output_clock; /* Chg. Output clock state 0xb6a 2 */ 667 __le32 status_clocks; /* Current Input clock state 0xb6c 4 */ 668 __le32 ext_box_status; /* External box status 0xb70 4 */ 669 __le32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */ 670 __le32 midi_out_free_count; 671 /* # of bytes free in MIDI output FIFO 0xb78 4 */ 672 __le32 unused2; /* Cyclic pipes 0xb7c 4 */ 673 __le32 control_register; 674 /* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */ 675 __le32 e3g_frq_register; /* 3G frequency register 0xb84 4 */ 676 u8 filler[24]; /* filler 0xb88 24*1 */ 677 s8 vmixer[VMIXER_ARRAY_SIZE]; 678 /* Vmixer levels 0xba0 64*1 */ 679 u8 midi_output[MIDI_OUT_BUFFER_SIZE]; 680 /* MIDI output data 0xbe0 32*1 */ 681 }; 682 683 #endif /* _ECHO_DSP_ */ 684