xref: /linux/drivers/ptp/ptp_ocp.c (revision cb8fef4b07f71da01843457b66e579ad248a625e) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3 
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/iopoll.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/nvmem-consumer.h>
26 #include <linux/crc16.h>
27 #include <linux/dpll.h>
28 #include <linux/unaligned.h>
29 #include <linux/delay.h>
30 #include <linux/firmware.h>
31 
32 #define PCI_DEVICE_ID_META_TIMECARD		0x0400
33 
34 #define PCI_VENDOR_ID_CELESTICA			0x18d4
35 #define PCI_DEVICE_ID_CELESTICA_TIMECARD	0x1008
36 
37 #define PCI_VENDOR_ID_OROLIA			0x1ad7
38 #define PCI_DEVICE_ID_OROLIA_ARTCARD		0xa000
39 
40 #define PCI_VENDOR_ID_ADVA			0xad5a
41 #define PCI_DEVICE_ID_ADVA_TIMECARD		0x0400
42 #define PCI_DEVICE_ID_ADVA_TIMECARD_X1		0x0410
43 
44 static struct class timecard_class = {
45 	.name		= "timecard",
46 };
47 
48 struct ocp_reg {
49 	u32	ctrl;
50 	u32	status;
51 	u32	select;
52 	u32	version;
53 	u32	time_ns;
54 	u32	time_sec;
55 	u32	__pad0[2];
56 	u32	adjust_ns;
57 	u32	adjust_sec;
58 	u32	__pad1[2];
59 	u32	offset_ns;
60 	u32	offset_window_ns;
61 	u32	__pad2[2];
62 	u32	drift_ns;
63 	u32	drift_window_ns;
64 	u32	__pad3[6];
65 	u32	servo_offset_p;
66 	u32	servo_offset_i;
67 	u32	servo_drift_p;
68 	u32	servo_drift_i;
69 	u32	status_offset;
70 	u32	status_drift;
71 };
72 
73 struct ptp_ocp_servo_conf {
74 	u32	servo_offset_p;
75 	u32	servo_offset_i;
76 	u32	servo_drift_p;
77 	u32	servo_drift_i;
78 };
79 
80 /*
81  * Combined servo + board-variant parameters for ADVA boards.
82  * Embedded in the resource table .extra so a single ptp_ocp_adva_board_init()
83  * can handle both ADVA and ADVA-X1 without per-variant init functions.
84  */
85 struct ptp_ocp_adva_info {
86 	struct ptp_ocp_servo_conf	servo;
87 	u32				flash_start;
88 	const struct ocp_sma_op		*sma_op;
89 	u8				signals_nr;
90 	u8				freq_in_nr;
91 	const struct ocp_attr_group	*attr_groups;
92 	/* x1: TAP CPLD present */
93 	bool				has_cpld;
94 };
95 
96 #define OCP_CTRL_ENABLE		BIT(0)
97 #define OCP_CTRL_ADJUST_TIME	BIT(1)
98 #define OCP_CTRL_ADJUST_OFFSET	BIT(2)
99 #define OCP_CTRL_ADJUST_DRIFT	BIT(3)
100 #define OCP_CTRL_ADJUST_SERVO	BIT(8)
101 #define OCP_CTRL_READ_TIME_REQ	BIT(30)
102 #define OCP_CTRL_READ_TIME_DONE	BIT(31)
103 
104 #define OCP_STATUS_IN_SYNC	BIT(0)
105 #define OCP_STATUS_IN_HOLDOVER	BIT(1)
106 
107 #define OCP_SELECT_CLK_NONE	0
108 #define OCP_SELECT_CLK_REG	0xfe
109 
110 struct tod_reg {
111 	u32	ctrl;
112 	u32	status;
113 	u32	uart_polarity;
114 	u32	version;
115 	u32	adj_sec;
116 	u32	__pad0[3];
117 	u32	uart_baud;
118 	u32	__pad1[3];
119 	u32	utc_status;
120 	u32	leap;
121 };
122 
123 #define TOD_CTRL_PROTOCOL	BIT(28)
124 #define TOD_CTRL_DISABLE_FMT_A	BIT(17)
125 #define TOD_CTRL_DISABLE_FMT_B	BIT(16)
126 #define TOD_CTRL_ENABLE		BIT(0)
127 #define TOD_CTRL_GNSS_MASK	GENMASK(3, 0)
128 #define TOD_CTRL_GNSS_SHIFT	24
129 
130 #define TOD_STATUS_UTC_MASK		GENMASK(7, 0)
131 #define TOD_STATUS_UTC_VALID		BIT(8)
132 #define TOD_STATUS_LEAP_ANNOUNCE	BIT(12)
133 #define TOD_STATUS_LEAP_VALID		BIT(16)
134 
135 struct ts_reg {
136 	u32	enable;
137 	u32	error;
138 	u32	polarity;
139 	u32	version;
140 	u32	__pad0[4];
141 	u32	cable_delay;
142 	u32	__pad1[3];
143 	u32	intr;
144 	u32	intr_mask;
145 	u32	event_count;
146 	u32	__pad2[1];
147 	u32	ts_count;
148 	u32	time_ns;
149 	u32	time_sec;
150 	u32	data_width;
151 	u32	data;
152 };
153 
154 struct pps_reg {
155 	u32	ctrl;
156 	u32	status;
157 	u32	__pad0[6];
158 	u32	cable_delay;
159 };
160 
161 #define PPS_STATUS_FILTER_ERR	BIT(0)
162 #define PPS_STATUS_SUPERV_ERR	BIT(1)
163 
164 struct img_reg {
165 	u32	version;
166 };
167 
168 struct gpio_reg {
169 	u32	gpio1;
170 	u32	__pad0;
171 	u32	gpio2;
172 	/* adva_x1: I2C bus ownership register; reserved on other variants */
173 	u32	i2c_bus_ctrl;
174 };
175 
176 struct irig_master_reg {
177 	u32	ctrl;
178 	u32	status;
179 	u32	__pad0;
180 	u32	version;
181 	u32	adj_sec;
182 	u32	mode_ctrl;
183 };
184 
185 #define IRIG_M_CTRL_ENABLE	BIT(0)
186 
187 struct irig_slave_reg {
188 	u32	ctrl;
189 	u32	status;
190 	u32	__pad0;
191 	u32	version;
192 	u32	adj_sec;
193 	u32	mode_ctrl;
194 };
195 
196 #define IRIG_S_CTRL_ENABLE	BIT(0)
197 
198 struct dcf_master_reg {
199 	u32	ctrl;
200 	u32	status;
201 	u32	__pad0;
202 	u32	version;
203 	u32	adj_sec;
204 };
205 
206 #define DCF_M_CTRL_ENABLE	BIT(0)
207 
208 struct dcf_slave_reg {
209 	u32	ctrl;
210 	u32	status;
211 	u32	__pad0;
212 	u32	version;
213 	u32	adj_sec;
214 };
215 
216 #define DCF_S_CTRL_ENABLE	BIT(0)
217 
218 struct signal_reg {
219 	u32	enable;
220 	u32	status;
221 	u32	polarity;
222 	u32	version;
223 	u32	__pad0[4];
224 	u32	cable_delay;
225 	u32	__pad1[3];
226 	u32	intr;
227 	u32	intr_mask;
228 	u32	__pad2[2];
229 	u32	start_ns;
230 	u32	start_sec;
231 	u32	pulse_ns;
232 	u32	pulse_sec;
233 	u32	period_ns;
234 	u32	period_sec;
235 	u32	repeat_count;
236 };
237 
238 struct frequency_reg {
239 	u32	ctrl;
240 	u32	status;
241 };
242 
243 struct board_config_reg {
244 	u32 mro50_serial_activate;
245 };
246 
247 #define FREQ_STATUS_VALID	BIT(31)
248 #define FREQ_STATUS_ERROR	BIT(30)
249 #define FREQ_STATUS_OVERRUN	BIT(29)
250 #define FREQ_STATUS_MASK	GENMASK(23, 0)
251 
252 struct ptp_ocp_flash_info {
253 	const char *name;
254 	int pci_offset;
255 	int data_size;
256 	void *data;
257 };
258 
259 struct ptp_ocp_firmware_header {
260 	char magic[4];
261 	__be16 pci_vendor_id;
262 	__be16 pci_device_id;
263 	__be32 image_size;
264 	__be16 hw_revision;
265 	__be16 crc;
266 };
267 
268 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
269 
270 struct ptp_ocp_i2c_info {
271 	const char *name;
272 	unsigned long fixed_rate;
273 	size_t data_size;
274 	void *data;
275 };
276 
277 struct ptp_ocp_ext_info {
278 	int index;
279 	irqreturn_t (*irq_fcn)(int irq, void *priv);
280 	int (*enable)(void *priv, u32 req, bool enable);
281 };
282 
283 struct ptp_ocp_ext_src {
284 	void __iomem		*mem;
285 	struct ptp_ocp		*bp;
286 	struct ptp_ocp_ext_info	*info;
287 	int			irq_vec;
288 };
289 
290 enum ptp_ocp_sma_mode {
291 	SMA_MODE_IN,
292 	SMA_MODE_OUT,
293 };
294 
295 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
296 	DPLL_PIN_FREQUENCY_1PPS,
297 	DPLL_PIN_FREQUENCY_10MHZ,
298 	DPLL_PIN_FREQUENCY_IRIG_B,
299 	DPLL_PIN_FREQUENCY_DCF77,
300 };
301 
302 struct ptp_ocp_sma_connector {
303 	enum	ptp_ocp_sma_mode mode;
304 	bool	fixed_fcn;
305 	bool	fixed_dir;
306 	bool	disabled;
307 	u8	default_fcn;
308 	struct dpll_pin		   *dpll_pin;
309 	struct dpll_pin_properties dpll_prop;
310 	dpll_tracker		   tracker;
311 };
312 
313 struct ocp_attr_group {
314 	u64 cap;
315 	const struct attribute_group *group;
316 };
317 
318 struct ocp_selector {
319 	const char *name;
320 	int value;
321 	u64 frequency;
322 };
323 
324 struct ocp_sma_op {
325 	const struct ocp_selector *tbl[2];
326 	void (*init)(struct ptp_ocp *bp);
327 	u32 (*get)(struct ptp_ocp *bp, int sma_nr);
328 	int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
329 	int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
330 };
331 
332 #define OCP_CAP_BASIC	BIT(0)
333 #define OCP_CAP_SIGNAL	BIT(1)
334 #define OCP_CAP_FREQ	BIT(2)
335 
336 struct ptp_ocp_signal {
337 	ktime_t		period;
338 	ktime_t		pulse;
339 	ktime_t		phase;
340 	ktime_t		start;
341 	int		duty;
342 	bool		polarity;
343 	bool		running;
344 };
345 
346 struct ptp_ocp_serial_port {
347 	struct uart_8250_port *uport;
348 	int baud;
349 };
350 
351 #define OCP_BOARD_ID_LEN		13
352 #define OCP_SERIAL_LEN			6
353 #define OCP_SMA_NUM			4
354 #define OCP_SIGNAL_NUM			4
355 #define OCP_FREQ_NUM			4
356 
357 enum {
358 	PORT_GNSS,
359 	PORT_GNSS2,
360 	PORT_MAC, /* miniature atomic clock */
361 	PORT_NMEA,
362 
363 	__PORT_COUNT,
364 };
365 
366 struct ptp_ocp {
367 	struct pci_dev		*pdev;
368 	struct device		dev;
369 	spinlock_t		lock;
370 	struct ocp_reg __iomem	*reg;
371 	struct tod_reg __iomem	*tod;
372 	struct pps_reg __iomem	*pps_to_ext;
373 	struct pps_reg __iomem	*pps_to_clk;
374 	struct board_config_reg __iomem	*board_config;
375 	struct gpio_reg __iomem	*pps_select;
376 	struct gpio_reg __iomem	*sma_map1;
377 	struct gpio_reg __iomem	*sma_map2;
378 	struct irig_master_reg	__iomem *irig_out;
379 	struct irig_slave_reg	__iomem *irig_in;
380 	struct dcf_master_reg	__iomem *dcf_out;
381 	struct dcf_slave_reg	__iomem *dcf_in;
382 	struct tod_reg		__iomem *nmea_out;
383 	struct frequency_reg	__iomem *freq_in[OCP_FREQ_NUM];
384 	struct ptp_ocp_ext_src	*signal_out[OCP_SIGNAL_NUM];
385 	struct ptp_ocp_ext_src	*pps;
386 	struct ptp_ocp_ext_src	*ts0;
387 	struct ptp_ocp_ext_src	*ts1;
388 	struct ptp_ocp_ext_src	*ts2;
389 	struct ptp_ocp_ext_src	*ts3;
390 	struct ptp_ocp_ext_src	*ts4;
391 	struct ocp_art_gpio_reg __iomem *art_sma;
392 	struct img_reg __iomem	*image;
393 	struct ptp_clock	*ptp;
394 	struct ptp_clock_info	ptp_info;
395 	struct platform_device	*i2c_ctrl;
396 	struct platform_device	*spi_flash;
397 	struct clk_hw		*i2c_clk;
398 	struct timer_list	watchdog;
399 	const struct attribute_group **attr_group;
400 	const struct ptp_ocp_eeprom_map *eeprom_map;
401 	struct dentry		*debug_root;
402 	bool			sync;
403 	time64_t		gnss_lost;
404 	struct delayed_work	sync_work;
405 	int			id;
406 	int			n_irqs;
407 	struct ptp_ocp_serial_port	port[__PORT_COUNT];
408 	bool			fw_loader;
409 	u8			fw_tag;
410 	u16			fw_version;
411 	u8			board_id[OCP_BOARD_ID_LEN];
412 	u8			serial[OCP_SERIAL_LEN];
413 	bool			has_eeprom_data;
414 	u32			pps_req_map;
415 	int			flash_start;
416 	u32			utc_tai_offset;
417 	u32			ts_window_adjust;
418 	u64			fw_cap;
419 	struct ptp_ocp_signal	signal[OCP_SIGNAL_NUM];
420 	struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
421 	const struct ocp_sma_op *sma_op;
422 	struct dpll_device *dpll;
423 	dpll_tracker tracker;
424 	int signals_nr;
425 	int freq_in_nr;
426 	/* adva_x1 CPLD I2C (internal use only) */
427 	/* serialises CPLD operations */
428 	struct mutex		cpld_lock;
429 	/* guards cpld_i2c_adap_nr against the bus notifier */
430 	spinlock_t		cpld_adap_lock;
431 	/* I2C adapter nr; -1 if absent.  Under cpld_adap_lock */
432 	int			cpld_i2c_adap_nr;
433 	/* claimed adapter; valid under cpld_lock */
434 	struct i2c_adapter	*cpld_adap;
435 	/* scratch, write half then read half; valid under cpld_lock */
436 	u8			*cpld_buf;
437 	/* Lattice device ID; 0 if unread */
438 	u32			cpld_id;
439 	/* USERCODE of the image in the part; valid once cpld_usercode_ok */
440 	u32			cpld_usercode;
441 	/* cpld_usercode has been read since the last flash */
442 	bool			cpld_usercode_ok;
443 	/* one-shot ID read finished, successfully or not; under cpld_lock */
444 	bool			cpld_id_tried;
445 	/* failed ID read attempts so far; under cpld_lock */
446 	unsigned int		cpld_id_attempts;
447 	/* x1 TAP CPLD present */
448 	bool			has_cpld;
449 	/* EN_CFG_TP issued but not yet REFRESH'd */
450 	bool			cpld_in_config_mode;
451 };
452 
453 #define OCP_REQ_TIMESTAMP	BIT(0)
454 #define OCP_REQ_PPS		BIT(1)
455 
456 struct ocp_resource {
457 	unsigned long offset;
458 	int size;
459 	int irq_vec;
460 	int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
461 	void *extra;
462 	unsigned long bp_offset;
463 	const char * const name;
464 };
465 
466 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
467 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
468 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
469 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
470 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
471 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
472 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
473 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
474 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
475 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
476 				      struct ptp_perout_request *req);
477 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
478 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
479 
480 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
481 
482 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
483 
484 static const struct ocp_sma_op ocp_adva_sma_op;
485 static const struct ocp_sma_op ocp_adva_x1_sma_op;
486 
487 /* Flash component naming the CPLD image, as reported by ->info_get(). */
488 #define ADVA_CPLD_COMPONENT	"fw.cpld"
489 
490 static int adva_x1_cpld_flash(struct ptp_ocp *bp, struct devlink *devlink,
491 			      const struct firmware *fw,
492 			      struct netlink_ext_ack *extack);
493 
494 static const struct ocp_attr_group fb_timecard_groups[];
495 
496 static const struct ocp_attr_group art_timecard_groups[];
497 
498 static const struct ocp_attr_group adva_timecard_groups[];
499 
500 static const struct ocp_attr_group adva_timecard_x1_groups[];
501 
502 struct ptp_ocp_eeprom_map {
503 	u16	off;
504 	u16	len;
505 	u32	bp_offset;
506 	const void * const tag;
507 };
508 
509 #define EEPROM_ENTRY(addr, member)				\
510 	.off = addr,						\
511 	.len = sizeof_field(struct ptp_ocp, member),		\
512 	.bp_offset = offsetof(struct ptp_ocp, member)
513 
514 #define BP_MAP_ENTRY_ADDR(bp, map) ({				\
515 	(void *)((uintptr_t)(bp) + (map)->bp_offset);		\
516 })
517 
518 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
519 	{ EEPROM_ENTRY(0x43, board_id) },
520 	{ EEPROM_ENTRY(0x00, serial), .tag = "mac" },
521 	{ }
522 };
523 
524 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
525 	{ EEPROM_ENTRY(0x200 + 0x43, board_id) },
526 	{ EEPROM_ENTRY(0x200 + 0x63, serial) },
527 	{ }
528 };
529 
530 #define bp_assign_entry(bp, res, val) ({				\
531 	uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset;		\
532 	*(typeof(val) *)addr = val;					\
533 })
534 
535 #define OCP_RES_LOCATION(member) \
536 	.name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
537 
538 #define OCP_MEM_RESOURCE(member) \
539 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
540 
541 #define OCP_SERIAL_RESOURCE(member) \
542 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
543 
544 #define OCP_I2C_RESOURCE(member) \
545 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
546 
547 #define OCP_SPI_RESOURCE(member) \
548 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
549 
550 #define OCP_EXT_RESOURCE(member) \
551 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
552 
553 /* This is the MSI vector mapping used.
554  * 0: PPS (TS5)
555  * 1: TS0
556  * 2: TS1
557  * 3: GNSS1
558  * 4: GNSS2
559  * 5: MAC
560  * 6: TS2
561  * 7: I2C controller
562  * 8: HWICAP (notused)
563  * 9: SPI Flash
564  * 10: NMEA
565  * 11: Signal Generator 1
566  * 12: Signal Generator 2
567  * 13: Signal Generator 3
568  * 14: Signal Generator 4
569  * 15: TS3
570  * 16: TS4
571  --
572  * 8: Orolia TS1
573  * 10: Orolia TS2
574  * 11: Orolia TS0 (GNSS)
575  * 12: Orolia PPS
576  * 14: Orolia TS3
577  * 15: Orolia TS4
578  */
579 
580 static struct ocp_resource ocp_fb_resource[] = {
581 	{
582 		OCP_MEM_RESOURCE(reg),
583 		.offset = 0x01000000, .size = 0x10000,
584 	},
585 	{
586 		OCP_EXT_RESOURCE(ts0),
587 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
588 		.extra = &(struct ptp_ocp_ext_info) {
589 			.index = 0,
590 			.irq_fcn = ptp_ocp_ts_irq,
591 			.enable = ptp_ocp_ts_enable,
592 		},
593 	},
594 	{
595 		OCP_EXT_RESOURCE(ts1),
596 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
597 		.extra = &(struct ptp_ocp_ext_info) {
598 			.index = 1,
599 			.irq_fcn = ptp_ocp_ts_irq,
600 			.enable = ptp_ocp_ts_enable,
601 		},
602 	},
603 	{
604 		OCP_EXT_RESOURCE(ts2),
605 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
606 		.extra = &(struct ptp_ocp_ext_info) {
607 			.index = 2,
608 			.irq_fcn = ptp_ocp_ts_irq,
609 			.enable = ptp_ocp_ts_enable,
610 		},
611 	},
612 	{
613 		OCP_EXT_RESOURCE(ts3),
614 		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
615 		.extra = &(struct ptp_ocp_ext_info) {
616 			.index = 3,
617 			.irq_fcn = ptp_ocp_ts_irq,
618 			.enable = ptp_ocp_ts_enable,
619 		},
620 	},
621 	{
622 		OCP_EXT_RESOURCE(ts4),
623 		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
624 		.extra = &(struct ptp_ocp_ext_info) {
625 			.index = 4,
626 			.irq_fcn = ptp_ocp_ts_irq,
627 			.enable = ptp_ocp_ts_enable,
628 		},
629 	},
630 	/* Timestamp for PHC and/or PPS generator */
631 	{
632 		OCP_EXT_RESOURCE(pps),
633 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
634 		.extra = &(struct ptp_ocp_ext_info) {
635 			.index = 5,
636 			.irq_fcn = ptp_ocp_ts_irq,
637 			.enable = ptp_ocp_ts_enable,
638 		},
639 	},
640 	{
641 		OCP_EXT_RESOURCE(signal_out[0]),
642 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
643 		.extra = &(struct ptp_ocp_ext_info) {
644 			.index = 1,
645 			.irq_fcn = ptp_ocp_signal_irq,
646 			.enable = ptp_ocp_signal_enable,
647 		},
648 	},
649 	{
650 		OCP_EXT_RESOURCE(signal_out[1]),
651 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
652 		.extra = &(struct ptp_ocp_ext_info) {
653 			.index = 2,
654 			.irq_fcn = ptp_ocp_signal_irq,
655 			.enable = ptp_ocp_signal_enable,
656 		},
657 	},
658 	{
659 		OCP_EXT_RESOURCE(signal_out[2]),
660 		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
661 		.extra = &(struct ptp_ocp_ext_info) {
662 			.index = 3,
663 			.irq_fcn = ptp_ocp_signal_irq,
664 			.enable = ptp_ocp_signal_enable,
665 		},
666 	},
667 	{
668 		OCP_EXT_RESOURCE(signal_out[3]),
669 		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
670 		.extra = &(struct ptp_ocp_ext_info) {
671 			.index = 4,
672 			.irq_fcn = ptp_ocp_signal_irq,
673 			.enable = ptp_ocp_signal_enable,
674 		},
675 	},
676 	{
677 		OCP_MEM_RESOURCE(pps_to_ext),
678 		.offset = 0x01030000, .size = 0x10000,
679 	},
680 	{
681 		OCP_MEM_RESOURCE(pps_to_clk),
682 		.offset = 0x01040000, .size = 0x10000,
683 	},
684 	{
685 		OCP_MEM_RESOURCE(tod),
686 		.offset = 0x01050000, .size = 0x10000,
687 	},
688 	{
689 		OCP_MEM_RESOURCE(irig_in),
690 		.offset = 0x01070000, .size = 0x10000,
691 	},
692 	{
693 		OCP_MEM_RESOURCE(irig_out),
694 		.offset = 0x01080000, .size = 0x10000,
695 	},
696 	{
697 		OCP_MEM_RESOURCE(dcf_in),
698 		.offset = 0x01090000, .size = 0x10000,
699 	},
700 	{
701 		OCP_MEM_RESOURCE(dcf_out),
702 		.offset = 0x010A0000, .size = 0x10000,
703 	},
704 	{
705 		OCP_MEM_RESOURCE(nmea_out),
706 		.offset = 0x010B0000, .size = 0x10000,
707 	},
708 	{
709 		OCP_MEM_RESOURCE(image),
710 		.offset = 0x00020000, .size = 0x1000,
711 	},
712 	{
713 		OCP_MEM_RESOURCE(pps_select),
714 		.offset = 0x00130000, .size = 0x1000,
715 	},
716 	{
717 		OCP_MEM_RESOURCE(sma_map1),
718 		.offset = 0x00140000, .size = 0x1000,
719 	},
720 	{
721 		OCP_MEM_RESOURCE(sma_map2),
722 		.offset = 0x00220000, .size = 0x1000,
723 	},
724 	{
725 		OCP_I2C_RESOURCE(i2c_ctrl),
726 		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
727 		.extra = &(struct ptp_ocp_i2c_info) {
728 			.name = "xiic-i2c",
729 			.fixed_rate = 50000000,
730 			.data_size = sizeof(struct xiic_i2c_platform_data),
731 			.data = &(struct xiic_i2c_platform_data) {
732 				.num_devices = 2,
733 				.devices = (struct i2c_board_info[]) {
734 					{ I2C_BOARD_INFO("24c02", 0x50) },
735 					{ I2C_BOARD_INFO("24mac402", 0x58),
736 					  .platform_data = "mac" },
737 				},
738 			},
739 		},
740 	},
741 	{
742 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
743 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
744 		.extra = &(struct ptp_ocp_serial_port) {
745 			.baud = 115200,
746 		},
747 	},
748 	{
749 		OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
750 		.offset = 0x00170000 + 0x1000, .irq_vec = 4,
751 		.extra = &(struct ptp_ocp_serial_port) {
752 			.baud = 115200,
753 		},
754 	},
755 	{
756 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
757 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
758 		.extra = &(struct ptp_ocp_serial_port) {
759 			.baud = 57600,
760 		},
761 	},
762 	{
763 		OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
764 		.offset = 0x00190000 + 0x1000, .irq_vec = 10,
765 	},
766 	{
767 		OCP_SPI_RESOURCE(spi_flash),
768 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
769 		.extra = &(struct ptp_ocp_flash_info) {
770 			.name = "xilinx_spi", .pci_offset = 0,
771 			.data_size = sizeof(struct xspi_platform_data),
772 			.data = &(struct xspi_platform_data) {
773 				.num_chipselect = 1,
774 				.bits_per_word = 8,
775 				.num_devices = 1,
776 				.force_irq = true,
777 				.devices = &(struct spi_board_info) {
778 					.modalias = "spi-nor",
779 				},
780 			},
781 		},
782 	},
783 	{
784 		OCP_MEM_RESOURCE(freq_in[0]),
785 		.offset = 0x01200000, .size = 0x10000,
786 	},
787 	{
788 		OCP_MEM_RESOURCE(freq_in[1]),
789 		.offset = 0x01210000, .size = 0x10000,
790 	},
791 	{
792 		OCP_MEM_RESOURCE(freq_in[2]),
793 		.offset = 0x01220000, .size = 0x10000,
794 	},
795 	{
796 		OCP_MEM_RESOURCE(freq_in[3]),
797 		.offset = 0x01230000, .size = 0x10000,
798 	},
799 	{
800 		.setup = ptp_ocp_fb_board_init,
801 		.extra = &(struct ptp_ocp_servo_conf) {
802 			.servo_offset_p = 0x2000,
803 			.servo_offset_i = 0x1000,
804 			.servo_drift_p = 0,
805 			.servo_drift_i = 0,
806 		},
807 	},
808 	{ }
809 };
810 
811 #define OCP_ART_CONFIG_SIZE		144
812 #define OCP_ART_TEMP_TABLE_SIZE		368
813 
814 struct ocp_art_gpio_reg {
815 	struct {
816 		u32	gpio;
817 		u32	__pad[3];
818 	} map[4];
819 };
820 
821 static struct ocp_resource ocp_art_resource[] = {
822 	{
823 		OCP_MEM_RESOURCE(reg),
824 		.offset = 0x01000000, .size = 0x10000,
825 	},
826 	{
827 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
828 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
829 		.extra = &(struct ptp_ocp_serial_port) {
830 			.baud = 115200,
831 		},
832 	},
833 	{
834 		OCP_MEM_RESOURCE(art_sma),
835 		.offset = 0x003C0000, .size = 0x1000,
836 	},
837 	/* Timestamp associated with GNSS1 receiver PPS */
838 	{
839 		OCP_EXT_RESOURCE(ts0),
840 		.offset = 0x360000, .size = 0x20, .irq_vec = 12,
841 		.extra = &(struct ptp_ocp_ext_info) {
842 			.index = 0,
843 			.irq_fcn = ptp_ocp_ts_irq,
844 			.enable = ptp_ocp_ts_enable,
845 		},
846 	},
847 	{
848 		OCP_EXT_RESOURCE(ts1),
849 		.offset = 0x380000, .size = 0x20, .irq_vec = 8,
850 		.extra = &(struct ptp_ocp_ext_info) {
851 			.index = 1,
852 			.irq_fcn = ptp_ocp_ts_irq,
853 			.enable = ptp_ocp_ts_enable,
854 		},
855 	},
856 	{
857 		OCP_EXT_RESOURCE(ts2),
858 		.offset = 0x390000, .size = 0x20, .irq_vec = 10,
859 		.extra = &(struct ptp_ocp_ext_info) {
860 			.index = 2,
861 			.irq_fcn = ptp_ocp_ts_irq,
862 			.enable = ptp_ocp_ts_enable,
863 		},
864 	},
865 	{
866 		OCP_EXT_RESOURCE(ts3),
867 		.offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
868 		.extra = &(struct ptp_ocp_ext_info) {
869 			.index = 3,
870 			.irq_fcn = ptp_ocp_ts_irq,
871 			.enable = ptp_ocp_ts_enable,
872 		},
873 	},
874 	{
875 		OCP_EXT_RESOURCE(ts4),
876 		.offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
877 		.extra = &(struct ptp_ocp_ext_info) {
878 			.index = 4,
879 			.irq_fcn = ptp_ocp_ts_irq,
880 			.enable = ptp_ocp_ts_enable,
881 		},
882 	},
883 	/* Timestamp associated with Internal PPS of the card */
884 	{
885 		OCP_EXT_RESOURCE(pps),
886 		.offset = 0x00330000, .size = 0x20, .irq_vec = 11,
887 		.extra = &(struct ptp_ocp_ext_info) {
888 			.index = 5,
889 			.irq_fcn = ptp_ocp_ts_irq,
890 			.enable = ptp_ocp_ts_enable,
891 		},
892 	},
893 	{
894 		OCP_SPI_RESOURCE(spi_flash),
895 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
896 		.extra = &(struct ptp_ocp_flash_info) {
897 			.name = "spi_altera", .pci_offset = 0,
898 			.data_size = sizeof(struct altera_spi_platform_data),
899 			.data = &(struct altera_spi_platform_data) {
900 				.num_chipselect = 1,
901 				.num_devices = 1,
902 				.devices = &(struct spi_board_info) {
903 					.modalias = "spi-nor",
904 				},
905 			},
906 		},
907 	},
908 	{
909 		OCP_I2C_RESOURCE(i2c_ctrl),
910 		.offset = 0x350000, .size = 0x100, .irq_vec = 4,
911 		.extra = &(struct ptp_ocp_i2c_info) {
912 			.name = "ocores-i2c",
913 			.fixed_rate = 400000,
914 			.data_size = sizeof(struct ocores_i2c_platform_data),
915 			.data = &(struct ocores_i2c_platform_data) {
916 				.clock_khz = 125000,
917 				.bus_khz = 400,
918 				.num_devices = 1,
919 				.devices = &(struct i2c_board_info) {
920 					I2C_BOARD_INFO("24c08", 0x50),
921 				},
922 			},
923 		},
924 	},
925 	{
926 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
927 		.offset = 0x00190000, .irq_vec = 7,
928 		.extra = &(struct ptp_ocp_serial_port) {
929 			.baud = 9600,
930 		},
931 	},
932 	{
933 		OCP_MEM_RESOURCE(board_config),
934 		.offset = 0x210000, .size = 0x1000,
935 	},
936 	{
937 		.setup = ptp_ocp_art_board_init,
938 		.extra = &(struct ptp_ocp_servo_conf) {
939 			.servo_offset_p = 0x2000,
940 			.servo_offset_i = 0x1000,
941 			.servo_drift_p = 0,
942 			.servo_drift_i = 0,
943 		},
944 	},
945 	{ }
946 };
947 
948 static struct ocp_resource ocp_adva_resource[] = {
949 	{
950 		OCP_MEM_RESOURCE(reg),
951 		.offset = 0x01000000, .size = 0x10000,
952 	},
953 	{
954 		OCP_EXT_RESOURCE(ts0),
955 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
956 		.extra = &(struct ptp_ocp_ext_info) {
957 			.index = 0,
958 			.irq_fcn = ptp_ocp_ts_irq,
959 			.enable = ptp_ocp_ts_enable,
960 		},
961 	},
962 	{
963 		OCP_EXT_RESOURCE(ts1),
964 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
965 		.extra = &(struct ptp_ocp_ext_info) {
966 			.index = 1,
967 			.irq_fcn = ptp_ocp_ts_irq,
968 			.enable = ptp_ocp_ts_enable,
969 		},
970 	},
971 	{
972 		OCP_EXT_RESOURCE(ts2),
973 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
974 		.extra = &(struct ptp_ocp_ext_info) {
975 			.index = 2,
976 			.irq_fcn = ptp_ocp_ts_irq,
977 			.enable = ptp_ocp_ts_enable,
978 		},
979 	},
980 	/* Timestamp for PHC and/or PPS generator */
981 	{
982 		OCP_EXT_RESOURCE(pps),
983 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
984 		.extra = &(struct ptp_ocp_ext_info) {
985 			.index = 5,
986 			.irq_fcn = ptp_ocp_ts_irq,
987 			.enable = ptp_ocp_ts_enable,
988 		},
989 	},
990 	{
991 		OCP_EXT_RESOURCE(signal_out[0]),
992 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
993 		.extra = &(struct ptp_ocp_ext_info) {
994 			.index = 1,
995 			.irq_fcn = ptp_ocp_signal_irq,
996 			.enable = ptp_ocp_signal_enable,
997 		},
998 	},
999 	{
1000 		OCP_EXT_RESOURCE(signal_out[1]),
1001 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
1002 		.extra = &(struct ptp_ocp_ext_info) {
1003 			.index = 2,
1004 			.irq_fcn = ptp_ocp_signal_irq,
1005 			.enable = ptp_ocp_signal_enable,
1006 		},
1007 	},
1008 	{
1009 		OCP_MEM_RESOURCE(pps_to_ext),
1010 		.offset = 0x01030000, .size = 0x10000,
1011 	},
1012 	{
1013 		OCP_MEM_RESOURCE(pps_to_clk),
1014 		.offset = 0x01040000, .size = 0x10000,
1015 	},
1016 	{
1017 		OCP_MEM_RESOURCE(tod),
1018 		.offset = 0x01050000, .size = 0x10000,
1019 	},
1020 	{
1021 		OCP_MEM_RESOURCE(image),
1022 		.offset = 0x00020000, .size = 0x1000,
1023 	},
1024 	{
1025 		OCP_MEM_RESOURCE(pps_select),
1026 		.offset = 0x00130000, .size = 0x1000,
1027 	},
1028 	{
1029 		OCP_MEM_RESOURCE(sma_map1),
1030 		.offset = 0x00140000, .size = 0x1000,
1031 	},
1032 	{
1033 		OCP_MEM_RESOURCE(sma_map2),
1034 		.offset = 0x00220000, .size = 0x1000,
1035 	},
1036 	{
1037 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
1038 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
1039 		.extra = &(struct ptp_ocp_serial_port) {
1040 			.baud = 9600,
1041 		},
1042 	},
1043 	{
1044 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1045 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
1046 		.extra = &(struct ptp_ocp_serial_port) {
1047 			.baud = 115200,
1048 		},
1049 	},
1050 	{
1051 		OCP_MEM_RESOURCE(freq_in[0]),
1052 		.offset = 0x01200000, .size = 0x10000,
1053 	},
1054 	{
1055 		OCP_MEM_RESOURCE(freq_in[1]),
1056 		.offset = 0x01210000, .size = 0x10000,
1057 	},
1058 	{
1059 		OCP_SPI_RESOURCE(spi_flash),
1060 		.offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
1061 		.extra = &(struct ptp_ocp_flash_info) {
1062 			.name = "spi_altera", .pci_offset = 0,
1063 			.data_size = sizeof(struct altera_spi_platform_data),
1064 			.data = &(struct altera_spi_platform_data) {
1065 				.num_chipselect = 1,
1066 				.num_devices = 1,
1067 				.devices = &(struct spi_board_info) {
1068 					.modalias = "spi-nor",
1069 				},
1070 			},
1071 		},
1072 	},
1073 	{
1074 		OCP_I2C_RESOURCE(i2c_ctrl),
1075 		.offset = 0x150000, .size = 0x100, .irq_vec = 7,
1076 		.extra = &(struct ptp_ocp_i2c_info) {
1077 			.name = "ocores-i2c",
1078 			.fixed_rate = 50000000,
1079 			.data_size = sizeof(struct ocores_i2c_platform_data),
1080 			.data = &(struct ocores_i2c_platform_data) {
1081 				.clock_khz = 50000,
1082 				.bus_khz = 100,
1083 				.reg_io_width = 4, // 32-bit/4-byte
1084 				.reg_shift = 2, // 32-bit addressing
1085 				.num_devices = 2,
1086 				.devices = (struct i2c_board_info[]) {
1087 					{ I2C_BOARD_INFO("24c02", 0x50) },
1088 					{ I2C_BOARD_INFO("24mac402", 0x58),
1089 					 .platform_data = "mac" },
1090 				},
1091 			},
1092 		},
1093 	},
1094 	{
1095 		.setup = ptp_ocp_adva_board_init,
1096 		.extra = &(struct ptp_ocp_adva_info) {
1097 			.servo = {
1098 				.servo_offset_p = 0xc000,
1099 				.servo_offset_i = 0x1000,
1100 				.servo_drift_p = 0,
1101 				.servo_drift_i = 0,
1102 			},
1103 			.flash_start  = 0xA00000,
1104 			.sma_op       = &ocp_adva_sma_op,
1105 			.signals_nr   = 2,
1106 			.freq_in_nr   = 2,
1107 			.attr_groups  = adva_timecard_groups,
1108 		},
1109 	},
1110 	{ }
1111 };
1112 
1113 static struct ocp_resource ocp_adva_x1_resource[] = {
1114 	{
1115 		OCP_MEM_RESOURCE(reg),
1116 		.offset = 0x01000000, .size = 0x10000,
1117 	},
1118 	{
1119 		OCP_EXT_RESOURCE(ts0),
1120 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
1121 		.extra = &(struct ptp_ocp_ext_info) {
1122 			.index = 0,
1123 			.irq_fcn = ptp_ocp_ts_irq,
1124 			.enable = ptp_ocp_ts_enable,
1125 		},
1126 	},
1127 	{
1128 		OCP_EXT_RESOURCE(ts1),
1129 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
1130 		.extra = &(struct ptp_ocp_ext_info) {
1131 			.index = 1,
1132 			.irq_fcn = ptp_ocp_ts_irq,
1133 			.enable = ptp_ocp_ts_enable,
1134 		},
1135 	},
1136 	{
1137 		OCP_EXT_RESOURCE(ts2),
1138 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
1139 		.extra = &(struct ptp_ocp_ext_info) {
1140 			.index = 2,
1141 			.irq_fcn = ptp_ocp_ts_irq,
1142 			.enable = ptp_ocp_ts_enable,
1143 		},
1144 	},
1145 	{
1146 		OCP_EXT_RESOURCE(ts3),
1147 		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
1148 		.extra = &(struct ptp_ocp_ext_info) {
1149 			.index = 3,
1150 			.irq_fcn = ptp_ocp_ts_irq,
1151 			.enable = ptp_ocp_ts_enable,
1152 		},
1153 	},
1154 	{
1155 		OCP_EXT_RESOURCE(ts4),
1156 		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
1157 		.extra = &(struct ptp_ocp_ext_info) {
1158 			.index = 4,
1159 			.irq_fcn = ptp_ocp_ts_irq,
1160 			.enable = ptp_ocp_ts_enable,
1161 		},
1162 	},
1163 	/* Timestamp for PHC and/or PPS generator */
1164 	{
1165 		OCP_EXT_RESOURCE(pps),
1166 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
1167 		.extra = &(struct ptp_ocp_ext_info) {
1168 			.index = 5,
1169 			.irq_fcn = ptp_ocp_ts_irq,
1170 			.enable = ptp_ocp_ts_enable,
1171 		},
1172 	},
1173 	{
1174 		OCP_EXT_RESOURCE(signal_out[0]),
1175 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
1176 		.extra = &(struct ptp_ocp_ext_info) {
1177 			.index = 1,
1178 			.irq_fcn = ptp_ocp_signal_irq,
1179 			.enable = ptp_ocp_signal_enable,
1180 		},
1181 	},
1182 	{
1183 		OCP_EXT_RESOURCE(signal_out[1]),
1184 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
1185 		.extra = &(struct ptp_ocp_ext_info) {
1186 			.index = 2,
1187 			.irq_fcn = ptp_ocp_signal_irq,
1188 			.enable = ptp_ocp_signal_enable,
1189 		},
1190 	},
1191 	{
1192 		OCP_EXT_RESOURCE(signal_out[2]),
1193 		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
1194 		.extra = &(struct ptp_ocp_ext_info) {
1195 			.index = 3,
1196 			.irq_fcn = ptp_ocp_signal_irq,
1197 			.enable = ptp_ocp_signal_enable,
1198 		},
1199 	},
1200 	{
1201 		OCP_EXT_RESOURCE(signal_out[3]),
1202 		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
1203 		.extra = &(struct ptp_ocp_ext_info) {
1204 			.index = 4,
1205 			.irq_fcn = ptp_ocp_signal_irq,
1206 			.enable = ptp_ocp_signal_enable,
1207 		},
1208 	},
1209 	{
1210 		OCP_MEM_RESOURCE(pps_to_ext),
1211 		.offset = 0x01030000, .size = 0x10000,
1212 	},
1213 	{
1214 		OCP_MEM_RESOURCE(pps_to_clk),
1215 		.offset = 0x01040000, .size = 0x10000,
1216 	},
1217 	{
1218 		OCP_MEM_RESOURCE(tod),
1219 		.offset = 0x01050000, .size = 0x10000,
1220 	},
1221 	{
1222 		OCP_MEM_RESOURCE(image),
1223 		.offset = 0x00020000, .size = 0x1000,
1224 	},
1225 	{
1226 		OCP_MEM_RESOURCE(pps_select),
1227 		.offset = 0x00130000, .size = 0x1000,
1228 	},
1229 	{
1230 		OCP_MEM_RESOURCE(sma_map1),
1231 		.offset = 0x00140000, .size = 0x1000,
1232 	},
1233 	{
1234 		OCP_MEM_RESOURCE(sma_map2),
1235 		.offset = 0x00220000, .size = 0x1000,
1236 	},
1237 	{
1238 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
1239 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
1240 		.extra = &(struct ptp_ocp_serial_port) {
1241 			.baud = 9600,
1242 		},
1243 	},
1244 	{
1245 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1246 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
1247 		.extra = &(struct ptp_ocp_serial_port) {
1248 			.baud = 115200,
1249 		},
1250 	},
1251 	{
1252 		OCP_MEM_RESOURCE(freq_in[0]),
1253 		.offset = 0x01200000, .size = 0x10000,
1254 	},
1255 	{
1256 		OCP_MEM_RESOURCE(freq_in[1]),
1257 		.offset = 0x01210000, .size = 0x10000,
1258 	},
1259 	{
1260 		OCP_MEM_RESOURCE(freq_in[2]),
1261 		.offset = 0x01220000, .size = 0x10000,
1262 	},
1263 	{
1264 		OCP_MEM_RESOURCE(freq_in[3]),
1265 		.offset = 0x01230000, .size = 0x10000,
1266 	},
1267 	{
1268 		OCP_SPI_RESOURCE(spi_flash),
1269 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
1270 		.extra = &(struct ptp_ocp_flash_info) {
1271 			.name = "xilinx_spi", .pci_offset = 0,
1272 			.data_size = sizeof(struct xspi_platform_data),
1273 			.data = &(struct xspi_platform_data) {
1274 				.num_chipselect = 1,
1275 				.bits_per_word = 8,
1276 				.num_devices = 1,
1277 				.force_irq = true,
1278 				.devices = &(struct spi_board_info) {
1279 					.modalias = "spi-nor",
1280 				},
1281 			},
1282 		},
1283 	},
1284 	{
1285 		OCP_I2C_RESOURCE(i2c_ctrl),
1286 		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
1287 		.extra = &(struct ptp_ocp_i2c_info) {
1288 			.name = "xiic-i2c",
1289 			.fixed_rate = 50000000,
1290 			.data_size = sizeof(struct xiic_i2c_platform_data),
1291 			.data = &(struct xiic_i2c_platform_data) {
1292 				.num_devices = 2,
1293 				.devices = (struct i2c_board_info[]) {
1294 					{ I2C_BOARD_INFO("24c02", 0x50) },
1295 					{ I2C_BOARD_INFO("24mac402", 0x58),
1296 					  .platform_data = "mac" },
1297 				},
1298 			},
1299 		},
1300 	},
1301 	{
1302 		.setup = ptp_ocp_adva_board_init,
1303 		.extra = &(struct ptp_ocp_adva_info) {
1304 			.servo = {
1305 				.servo_offset_p = 0xc000,
1306 				.servo_offset_i = 0x1000,
1307 				.servo_drift_p = 0,
1308 				.servo_drift_i = 0,
1309 			},
1310 			.flash_start  = 0x1000000,
1311 			.sma_op       = &ocp_adva_x1_sma_op,
1312 			.signals_nr   = 4,
1313 			.freq_in_nr   = 4,
1314 			.attr_groups  = adva_timecard_x1_groups,
1315 			.has_cpld     = true,
1316 		},
1317 	},
1318 	{ }
1319 };
1320 
1321 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1322 	{ PCI_DEVICE_DATA(META, TIMECARD, &ocp_fb_resource) },
1323 	{ PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1324 	{ PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1325 	{ PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1326 	{ PCI_DEVICE_DATA(ADVA, TIMECARD_X1, &ocp_adva_x1_resource) },
1327 	{ }
1328 };
1329 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1330 
1331 static DEFINE_MUTEX(ptp_ocp_lock);
1332 static DEFINE_IDR(ptp_ocp_idr);
1333 
1334 static const struct ocp_selector ptp_ocp_clock[] = {
1335 	{ .name = "NONE",	.value = 0 },
1336 	{ .name = "TOD",	.value = 1 },
1337 	{ .name = "IRIG",	.value = 2 },
1338 	{ .name = "PPS",	.value = 3 },
1339 	{ .name = "PTP",	.value = 4 },
1340 	{ .name = "RTC",	.value = 5 },
1341 	{ .name = "DCF",	.value = 6 },
1342 	{ .name = "REGS",	.value = 0xfe },
1343 	{ .name = "EXT",	.value = 0xff },
1344 	{ }
1345 };
1346 
1347 #define SMA_DISABLE		BIT(16)
1348 #define SMA_ENABLE		BIT(15)
1349 #define SMA_SELECT_MASK		GENMASK(14, 0)
1350 
1351 static const struct ocp_selector ptp_ocp_sma_in[] = {
1352 	{ .name = "10Mhz",  .value = 0x0000,      .frequency = 10000000 },
1353 	{ .name = "PPS1",   .value = 0x0001,      .frequency = 1 },
1354 	{ .name = "PPS2",   .value = 0x0002,      .frequency = 1 },
1355 	{ .name = "TS1",    .value = 0x0004,      .frequency = 0 },
1356 	{ .name = "TS2",    .value = 0x0008,      .frequency = 0 },
1357 	{ .name = "IRIG",   .value = 0x0010,      .frequency = 10000 },
1358 	{ .name = "DCF",    .value = 0x0020,      .frequency = 77500 },
1359 	{ .name = "TS3",    .value = 0x0040,      .frequency = 0 },
1360 	{ .name = "TS4",    .value = 0x0080,      .frequency = 0 },
1361 	{ .name = "FREQ1",  .value = 0x0100,      .frequency = 0 },
1362 	{ .name = "FREQ2",  .value = 0x0200,      .frequency = 0 },
1363 	{ .name = "FREQ3",  .value = 0x0400,      .frequency = 0 },
1364 	{ .name = "FREQ4",  .value = 0x0800,      .frequency = 0 },
1365 	{ .name = "None",   .value = SMA_DISABLE, .frequency = 0 },
1366 	{ }
1367 };
1368 
1369 static const struct ocp_selector ptp_ocp_sma_out[] = {
1370 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000 },
1371 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1372 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1373 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1374 	{ .name = "GNSS2",	.value = 0x0008,  .frequency = 1 },
1375 	{ .name = "IRIG",	.value = 0x0010,  .frequency = 10000 },
1376 	{ .name = "DCF",	.value = 0x0020,  .frequency = 77000 },
1377 	{ .name = "GEN1",	.value = 0x0040 },
1378 	{ .name = "GEN2",	.value = 0x0080 },
1379 	{ .name = "GEN3",	.value = 0x0100 },
1380 	{ .name = "GEN4",	.value = 0x0200 },
1381 	{ .name = "GND",	.value = 0x2000 },
1382 	{ .name = "VCC",	.value = 0x4000 },
1383 	{ }
1384 };
1385 
1386 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1387 	{ .name = "PPS1",	.value = 0x0001,  .frequency = 1 },
1388 	{ .name = "10Mhz",	.value = 0x0008,  .frequency = 1000000 },
1389 	{ }
1390 };
1391 
1392 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1393 	{ .name = "PHC",	.value = 0x0002,  .frequency = 1 },
1394 	{ .name = "GNSS",	.value = 0x0004,  .frequency = 1 },
1395 	{ .name = "10Mhz",	.value = 0x0010,  .frequency = 10000000 },
1396 	{ }
1397 };
1398 
1399 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1400 	{ .name = "10Mhz",	.value = 0x0000,      .frequency = 10000000},
1401 	{ .name = "PPS1",	.value = 0x0001,      .frequency = 1 },
1402 	{ .name = "PPS2",	.value = 0x0002,      .frequency = 1 },
1403 	{ .name = "TS1",	.value = 0x0004,      .frequency = 0 },
1404 	{ .name = "TS2",	.value = 0x0008,      .frequency = 0 },
1405 	{ .name = "FREQ1",	.value = 0x0100,      .frequency = 0 },
1406 	{ .name = "FREQ2",	.value = 0x0200,      .frequency = 0 },
1407 	{ .name = "None",	.value = SMA_DISABLE, .frequency = 0 },
1408 	{ }
1409 };
1410 
1411 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1412 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000},
1413 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1414 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1415 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1416 	{ .name = "GEN1",	.value = 0x0040 },
1417 	{ .name = "GEN2",	.value = 0x0080 },
1418 	{ .name = "GND",	.value = 0x2000 },
1419 	{ .name = "VCC",	.value = 0x4000 },
1420 	{ }
1421 };
1422 
1423 static const struct ocp_selector ptp_ocp_adva_x1_sma_in[] = {
1424 	{ .name = "PPS1",	.value = 0x0001,      .frequency = 1 },
1425 	{ .name = "TS1",	.value = 0x0004,      .frequency = 0 },
1426 	{ .name = "TS2",	.value = 0x0008,      .frequency = 0 },
1427 	{ .name = "TS3",    .value = 0x0040,      .frequency = 0 },
1428 	{ .name = "TS4",    .value = 0x0080,      .frequency = 0 },
1429 	{ .name = "FREQ1",	.value = 0x0100,      .frequency = 0 },
1430 	{ .name = "FREQ2",	.value = 0x0200,      .frequency = 0 },
1431 	{ .name = "FREQ3",  .value = 0x0400,      .frequency = 0 },
1432 	{ .name = "FREQ4",  .value = 0x0800,      .frequency = 0 },
1433 	{ .name = "None",	.value = SMA_DISABLE, .frequency = 0 },
1434 	{ }
1435 };
1436 
1437 static const struct ocp_selector ptp_ocp_adva_x1_sma_out[] = {
1438 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000},
1439 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1440 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1441 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1442 	{ .name = "GEN1",	.value = 0x0040 },
1443 	{ .name = "GEN2",	.value = 0x0080 },
1444 	{ .name = "GEN3",	.value = 0x0100 },
1445 	{ .name = "GEN4",	.value = 0x0200 },
1446 	{ .name = "GND",	.value = 0x2000 },
1447 	{ .name = "VCC",	.value = 0x4000 },
1448 	{ }
1449 };
1450 
1451 static void
1452 ptp_ocp_sma_init(struct ptp_ocp *bp)
1453 {
1454 	return bp->sma_op->init(bp);
1455 }
1456 
1457 static u32
1458 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1459 {
1460 	return bp->sma_op->get(bp, sma_nr);
1461 }
1462 
1463 static int
1464 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1465 {
1466 	return bp->sma_op->set_inputs(bp, sma_nr, val);
1467 }
1468 
1469 static int
1470 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1471 {
1472 	return bp->sma_op->set_output(bp, sma_nr, val);
1473 }
1474 
1475 static const char *
1476 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1477 {
1478 	int i;
1479 
1480 	for (i = 0; tbl[i].name; i++)
1481 		if (tbl[i].value == val)
1482 			return tbl[i].name;
1483 	return NULL;
1484 }
1485 
1486 static int
1487 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1488 {
1489 	const char *select;
1490 	int i;
1491 
1492 	for (i = 0; tbl[i].name; i++) {
1493 		select = tbl[i].name;
1494 		if (!strncasecmp(name, select, strlen(select)))
1495 			return tbl[i].value;
1496 	}
1497 	return -EINVAL;
1498 }
1499 
1500 static ssize_t
1501 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1502 {
1503 	ssize_t count;
1504 	int i;
1505 
1506 	count = 0;
1507 	for (i = 0; tbl[i].name; i++)
1508 		count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1509 	if (count)
1510 		count--;
1511 	count += sysfs_emit_at(buf, count, "\n");
1512 	return count;
1513 }
1514 
1515 static int
1516 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1517 			 struct ptp_system_timestamp *sts)
1518 {
1519 	u32 ctrl, time_sec, time_ns;
1520 	int i;
1521 
1522 	ptp_read_system_prets(sts);
1523 
1524 	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1525 	iowrite32(ctrl, &bp->reg->ctrl);
1526 
1527 	for (i = 0; i < 100; i++) {
1528 		ctrl = ioread32(&bp->reg->ctrl);
1529 		if (ctrl & OCP_CTRL_READ_TIME_DONE)
1530 			break;
1531 	}
1532 	ptp_read_system_postts(sts);
1533 
1534 	if (sts && bp->ts_window_adjust)
1535 		sts->post_sts.systime -= bp->ts_window_adjust;
1536 
1537 	time_ns = ioread32(&bp->reg->time_ns);
1538 	time_sec = ioread32(&bp->reg->time_sec);
1539 
1540 	ts->tv_sec = time_sec;
1541 	ts->tv_nsec = time_ns;
1542 
1543 	return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1544 }
1545 
1546 static int
1547 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1548 		 struct ptp_system_timestamp *sts)
1549 {
1550 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1551 	unsigned long flags;
1552 	int err;
1553 
1554 	spin_lock_irqsave(&bp->lock, flags);
1555 	err = __ptp_ocp_gettime_locked(bp, ts, sts);
1556 	spin_unlock_irqrestore(&bp->lock, flags);
1557 
1558 	return err;
1559 }
1560 
1561 static void
1562 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1563 {
1564 	u32 ctrl, time_sec, time_ns;
1565 	u32 select;
1566 
1567 	time_ns = ts->tv_nsec;
1568 	time_sec = ts->tv_sec;
1569 
1570 	select = ioread32(&bp->reg->select);
1571 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1572 
1573 	iowrite32(time_ns, &bp->reg->adjust_ns);
1574 	iowrite32(time_sec, &bp->reg->adjust_sec);
1575 
1576 	ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1577 	iowrite32(ctrl, &bp->reg->ctrl);
1578 
1579 	/* restore clock selection */
1580 	iowrite32(select >> 16, &bp->reg->select);
1581 }
1582 
1583 static int
1584 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1585 {
1586 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1587 	unsigned long flags;
1588 
1589 	spin_lock_irqsave(&bp->lock, flags);
1590 	__ptp_ocp_settime_locked(bp, ts);
1591 	spin_unlock_irqrestore(&bp->lock, flags);
1592 
1593 	return 0;
1594 }
1595 
1596 static void
1597 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1598 {
1599 	u32 select, ctrl;
1600 
1601 	select = ioread32(&bp->reg->select);
1602 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1603 
1604 	iowrite32(adj_val, &bp->reg->offset_ns);
1605 	iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1606 
1607 	ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1608 	iowrite32(ctrl, &bp->reg->ctrl);
1609 
1610 	/* restore clock selection */
1611 	iowrite32(select >> 16, &bp->reg->select);
1612 }
1613 
1614 static void
1615 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1616 {
1617 	struct timespec64 ts;
1618 	unsigned long flags;
1619 	int err;
1620 
1621 	spin_lock_irqsave(&bp->lock, flags);
1622 	err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1623 	if (likely(!err)) {
1624 		set_normalized_timespec64(&ts, ts.tv_sec,
1625 					  ts.tv_nsec + delta_ns);
1626 		__ptp_ocp_settime_locked(bp, &ts);
1627 	}
1628 	spin_unlock_irqrestore(&bp->lock, flags);
1629 }
1630 
1631 static int
1632 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1633 {
1634 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1635 	unsigned long flags;
1636 	u32 adj_ns, sign;
1637 
1638 	if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1639 		ptp_ocp_adjtime_coarse(bp, delta_ns);
1640 		return 0;
1641 	}
1642 
1643 	sign = delta_ns < 0 ? BIT(31) : 0;
1644 	adj_ns = sign ? -delta_ns : delta_ns;
1645 
1646 	spin_lock_irqsave(&bp->lock, flags);
1647 	__ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1648 	spin_unlock_irqrestore(&bp->lock, flags);
1649 
1650 	return 0;
1651 }
1652 
1653 static int
1654 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1655 {
1656 	if (scaled_ppm == 0)
1657 		return 0;
1658 
1659 	return -EOPNOTSUPP;
1660 }
1661 
1662 static s32
1663 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1664 {
1665 	return 0;
1666 }
1667 
1668 static int
1669 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1670 {
1671 	return -EOPNOTSUPP;
1672 }
1673 
1674 static int
1675 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1676 	       int on)
1677 {
1678 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1679 	struct ptp_ocp_ext_src *ext = NULL;
1680 	u32 req;
1681 	int err;
1682 
1683 	switch (rq->type) {
1684 	case PTP_CLK_REQ_EXTTS:
1685 		req = OCP_REQ_TIMESTAMP;
1686 		switch (rq->extts.index) {
1687 		case 0:
1688 			ext = bp->ts0;
1689 			break;
1690 		case 1:
1691 			ext = bp->ts1;
1692 			break;
1693 		case 2:
1694 			ext = bp->ts2;
1695 			break;
1696 		case 3:
1697 			ext = bp->ts3;
1698 			break;
1699 		case 4:
1700 			ext = bp->ts4;
1701 			break;
1702 		case 5:
1703 			ext = bp->pps;
1704 			break;
1705 		}
1706 		break;
1707 	case PTP_CLK_REQ_PPS:
1708 		req = OCP_REQ_PPS;
1709 		ext = bp->pps;
1710 		break;
1711 	case PTP_CLK_REQ_PEROUT:
1712 		switch (rq->perout.index) {
1713 		case 0:
1714 			/* This is a request for 1PPS on an output SMA.
1715 			 * Allow, but assume manual configuration.
1716 			 */
1717 			if (on && (rq->perout.period.sec != 1 ||
1718 				   rq->perout.period.nsec != 0))
1719 				return -EINVAL;
1720 			return 0;
1721 		case 1:
1722 		case 2:
1723 		case 3:
1724 		case 4:
1725 			req = rq->perout.index - 1;
1726 			ext = bp->signal_out[req];
1727 			err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1728 			if (err)
1729 				return err;
1730 			break;
1731 		}
1732 		break;
1733 	default:
1734 		return -EOPNOTSUPP;
1735 	}
1736 
1737 	err = -ENXIO;
1738 	if (ext)
1739 		err = ext->info->enable(ext, req, on);
1740 
1741 	return err;
1742 }
1743 
1744 static int
1745 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1746 	       enum ptp_pin_function func, unsigned chan)
1747 {
1748 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1749 	char buf[16];
1750 
1751 	switch (func) {
1752 	case PTP_PF_NONE:
1753 		snprintf(buf, sizeof(buf), "IN: None");
1754 		break;
1755 	case PTP_PF_EXTTS:
1756 		/* Allow timestamps, but require sysfs configuration. */
1757 		return 0;
1758 	case PTP_PF_PEROUT:
1759 		/* channel 0 is 1PPS from PHC.
1760 		 * channels 1..4 are the frequency generators.
1761 		 */
1762 		if (chan)
1763 			snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1764 		else
1765 			snprintf(buf, sizeof(buf), "OUT: PHC");
1766 		break;
1767 	default:
1768 		return -EOPNOTSUPP;
1769 	}
1770 
1771 	return ptp_ocp_sma_store(bp, buf, pin + 1);
1772 }
1773 
1774 static const struct ptp_clock_info ptp_ocp_clock_info = {
1775 	.owner		= THIS_MODULE,
1776 	.name		= KBUILD_MODNAME,
1777 	.max_adj	= 100000000,
1778 	.gettimex64	= ptp_ocp_gettimex,
1779 	.settime64	= ptp_ocp_settime,
1780 	.adjtime	= ptp_ocp_adjtime,
1781 	.adjfine	= ptp_ocp_null_adjfine,
1782 	.adjphase	= ptp_ocp_null_adjphase,
1783 	.getmaxphase	= ptp_ocp_null_getmaxphase,
1784 	.enable		= ptp_ocp_enable,
1785 	.verify		= ptp_ocp_verify,
1786 	.pps		= true,
1787 	.n_ext_ts	= 6,
1788 	.n_per_out	= 5,
1789 	.supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE,
1790 	.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE,
1791 };
1792 
1793 static void
1794 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1795 {
1796 	u32 ctrl, select;
1797 
1798 	select = ioread32(&bp->reg->select);
1799 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1800 
1801 	iowrite32(0, &bp->reg->drift_ns);
1802 
1803 	ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1804 	iowrite32(ctrl, &bp->reg->ctrl);
1805 
1806 	/* restore clock selection */
1807 	iowrite32(select >> 16, &bp->reg->select);
1808 }
1809 
1810 static void
1811 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1812 {
1813 	unsigned long flags;
1814 
1815 	spin_lock_irqsave(&bp->lock, flags);
1816 
1817 	bp->utc_tai_offset = val;
1818 
1819 	if (bp->irig_out)
1820 		iowrite32(val, &bp->irig_out->adj_sec);
1821 	if (bp->dcf_out)
1822 		iowrite32(val, &bp->dcf_out->adj_sec);
1823 	if (bp->nmea_out)
1824 		iowrite32(val, &bp->nmea_out->adj_sec);
1825 
1826 	spin_unlock_irqrestore(&bp->lock, flags);
1827 }
1828 
1829 static void
1830 ptp_ocp_watchdog(struct timer_list *t)
1831 {
1832 	struct ptp_ocp *bp = timer_container_of(bp, t, watchdog);
1833 	unsigned long flags;
1834 	u32 status, utc_offset;
1835 
1836 	status = ioread32(&bp->pps_to_clk->status);
1837 
1838 	if (status & PPS_STATUS_SUPERV_ERR) {
1839 		iowrite32(status, &bp->pps_to_clk->status);
1840 		if (!bp->gnss_lost) {
1841 			spin_lock_irqsave(&bp->lock, flags);
1842 			__ptp_ocp_clear_drift_locked(bp);
1843 			spin_unlock_irqrestore(&bp->lock, flags);
1844 			bp->gnss_lost = ktime_get_real_seconds();
1845 		}
1846 
1847 	} else if (bp->gnss_lost) {
1848 		bp->gnss_lost = 0;
1849 	}
1850 
1851 	/* if GNSS provides correct data we can rely on
1852 	 * it to get leap second information
1853 	 */
1854 	if (bp->tod) {
1855 		status = ioread32(&bp->tod->utc_status);
1856 		utc_offset = status & TOD_STATUS_UTC_MASK;
1857 		if (status & TOD_STATUS_UTC_VALID &&
1858 		    utc_offset != bp->utc_tai_offset)
1859 			ptp_ocp_utc_distribute(bp, utc_offset);
1860 	}
1861 
1862 	mod_timer(&bp->watchdog, jiffies + HZ);
1863 }
1864 
1865 static void
1866 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1867 {
1868 	ktime_t start, end, delay = KTIME_MAX;
1869 	u32 ctrl;
1870 	int i;
1871 
1872 	for (i = 0; i < 3; i++) {
1873 		ctrl = ioread32(&bp->reg->ctrl);
1874 		ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1875 
1876 		iowrite32(ctrl, &bp->reg->ctrl);
1877 
1878 		start = ktime_get_raw_ns();
1879 
1880 		ctrl = ioread32(&bp->reg->ctrl);
1881 
1882 		end = ktime_get_raw_ns();
1883 
1884 		delay = min(delay, end - start);
1885 	}
1886 	bp->ts_window_adjust = (delay >> 5) * 3;
1887 }
1888 
1889 static int
1890 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1891 {
1892 	struct timespec64 ts;
1893 	u32 ctrl;
1894 
1895 	ctrl = OCP_CTRL_ENABLE;
1896 	iowrite32(ctrl, &bp->reg->ctrl);
1897 
1898 	/* servo configuration */
1899 	iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1900 	iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1901 	iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1902 	iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1903 
1904 	/* latch servo values */
1905 	ctrl |= OCP_CTRL_ADJUST_SERVO;
1906 	iowrite32(ctrl, &bp->reg->ctrl);
1907 
1908 	if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1909 		dev_err(&bp->pdev->dev, "clock not enabled\n");
1910 		return -ENODEV;
1911 	}
1912 
1913 	ptp_ocp_estimate_pci_timing(bp);
1914 
1915 	bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1916 	if (!bp->sync) {
1917 		ktime_get_clocktai_ts64(&ts);
1918 		ptp_ocp_settime(&bp->ptp_info, &ts);
1919 	}
1920 
1921 	/* If there is a clock supervisor, then enable the watchdog */
1922 	if (bp->pps_to_clk) {
1923 		timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1924 		mod_timer(&bp->watchdog, jiffies + HZ);
1925 	}
1926 
1927 	return 0;
1928 }
1929 
1930 static void
1931 ptp_ocp_tod_init(struct ptp_ocp *bp)
1932 {
1933 	u32 ctrl, reg;
1934 
1935 	ctrl = ioread32(&bp->tod->ctrl);
1936 	ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1937 	ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1938 	iowrite32(ctrl, &bp->tod->ctrl);
1939 
1940 	reg = ioread32(&bp->tod->utc_status);
1941 	if (reg & TOD_STATUS_UTC_VALID)
1942 		ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1943 }
1944 
1945 static const char *
1946 ptp_ocp_tod_proto_name(const int idx)
1947 {
1948 	static const char * const proto_name[] = {
1949 		"NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1950 		"UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1951 	};
1952 	return proto_name[idx];
1953 }
1954 
1955 static const char *
1956 ptp_ocp_tod_gnss_name(int idx)
1957 {
1958 	static const char * const gnss_name[] = {
1959 		"ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1960 		"Unknown"
1961 	};
1962 	if (idx >= ARRAY_SIZE(gnss_name))
1963 		idx = ARRAY_SIZE(gnss_name) - 1;
1964 	return gnss_name[idx];
1965 }
1966 
1967 static const char *
1968 ptp_ocp_tty_port_name(int idx)
1969 {
1970 	static const char * const tty_name[] = {
1971 		"GNSS", "GNSS2", "MAC", "NMEA"
1972 	};
1973 	return tty_name[idx];
1974 }
1975 
1976 struct ptp_ocp_nvmem_match_info {
1977 	struct ptp_ocp *bp;
1978 	const void * const tag;
1979 };
1980 
1981 static int
1982 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1983 {
1984 	const struct ptp_ocp_nvmem_match_info *info = data;
1985 
1986 	dev = dev->parent;
1987 	if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1988 		return 0;
1989 
1990 	while ((dev = dev->parent))
1991 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1992 			return info->bp == dev_get_drvdata(dev);
1993 	return 0;
1994 }
1995 
1996 static inline struct nvmem_device *
1997 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1998 {
1999 	struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
2000 
2001 	return nvmem_device_find(&info, ptp_ocp_nvmem_match);
2002 }
2003 
2004 static inline void
2005 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
2006 {
2007 	if (!IS_ERR_OR_NULL(*nvmemp))
2008 		nvmem_device_put(*nvmemp);
2009 	*nvmemp = NULL;
2010 }
2011 
2012 static void
2013 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
2014 {
2015 	const struct ptp_ocp_eeprom_map *map;
2016 	struct nvmem_device *nvmem;
2017 	const void *tag;
2018 	int ret;
2019 
2020 	if (!bp->i2c_ctrl)
2021 		return;
2022 
2023 	tag = NULL;
2024 	nvmem = NULL;
2025 
2026 	for (map = bp->eeprom_map; map->len; map++) {
2027 		if (map->tag != tag) {
2028 			tag = map->tag;
2029 			ptp_ocp_nvmem_device_put(&nvmem);
2030 		}
2031 		if (!nvmem) {
2032 			nvmem = ptp_ocp_nvmem_device_get(bp, tag);
2033 			if (IS_ERR(nvmem)) {
2034 				ret = PTR_ERR(nvmem);
2035 				goto fail;
2036 			}
2037 		}
2038 		ret = nvmem_device_read(nvmem, map->off, map->len,
2039 					BP_MAP_ENTRY_ADDR(bp, map));
2040 		if (ret != map->len)
2041 			goto fail;
2042 	}
2043 
2044 	bp->has_eeprom_data = true;
2045 
2046 out:
2047 	ptp_ocp_nvmem_device_put(&nvmem);
2048 	return;
2049 
2050 fail:
2051 	dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
2052 	goto out;
2053 }
2054 
2055 static struct device *
2056 ptp_ocp_find_flash(struct ptp_ocp *bp)
2057 {
2058 	struct device *dev, *last;
2059 
2060 	last = NULL;
2061 	dev = &bp->spi_flash->dev;
2062 
2063 	while ((dev = device_find_any_child(dev))) {
2064 		if (!strcmp("mtd", dev_bus_name(dev)))
2065 			break;
2066 		put_device(last);
2067 		last = dev;
2068 	}
2069 	put_device(last);
2070 
2071 	return dev;
2072 }
2073 
2074 static int
2075 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
2076 			 const u8 **data, size_t *size)
2077 {
2078 	struct ptp_ocp *bp = devlink_priv(devlink);
2079 	const struct ptp_ocp_firmware_header *hdr;
2080 	size_t offset, length;
2081 	u16 crc;
2082 
2083 	hdr = (const struct ptp_ocp_firmware_header *)fw->data;
2084 	if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
2085 		devlink_flash_update_status_notify(devlink,
2086 			"No firmware header found, cancel firmware upgrade",
2087 			NULL, 0, 0);
2088 		return -EINVAL;
2089 	}
2090 
2091 	if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
2092 	    be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
2093 		devlink_flash_update_status_notify(devlink,
2094 			"Firmware image compatibility check failed",
2095 			NULL, 0, 0);
2096 		return -EINVAL;
2097 	}
2098 
2099 	offset = sizeof(*hdr);
2100 	length = be32_to_cpu(hdr->image_size);
2101 	if (length != (fw->size - offset)) {
2102 		devlink_flash_update_status_notify(devlink,
2103 			"Firmware image size check failed",
2104 			NULL, 0, 0);
2105 		return -EINVAL;
2106 	}
2107 
2108 	crc = crc16(0xffff, &fw->data[offset], length);
2109 	if (be16_to_cpu(hdr->crc) != crc) {
2110 		devlink_flash_update_status_notify(devlink,
2111 			"Firmware image CRC check failed",
2112 			NULL, 0, 0);
2113 		return -EINVAL;
2114 	}
2115 
2116 	*data = &fw->data[offset];
2117 	*size = length;
2118 
2119 	return 0;
2120 }
2121 
2122 static int
2123 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
2124 		      const struct firmware *fw)
2125 {
2126 	struct mtd_info *mtd = dev_get_drvdata(dev);
2127 	struct ptp_ocp *bp = devlink_priv(devlink);
2128 	size_t off, len, size, resid, wrote;
2129 	struct erase_info erase;
2130 	size_t base, blksz;
2131 	const u8 *data;
2132 	int err;
2133 
2134 	err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
2135 	if (err)
2136 		goto out;
2137 
2138 	off = 0;
2139 	base = bp->flash_start;
2140 	blksz = 4096;
2141 	resid = size;
2142 
2143 	while (resid) {
2144 		devlink_flash_update_status_notify(devlink, "Flashing",
2145 						   NULL, off, size);
2146 
2147 		len = min_t(size_t, resid, blksz);
2148 		erase.addr = base + off;
2149 		erase.len = blksz;
2150 
2151 		err = mtd_erase(mtd, &erase);
2152 		if (err)
2153 			goto out;
2154 
2155 		err = mtd_write(mtd, base + off, len, &wrote, data + off);
2156 		if (err)
2157 			goto out;
2158 
2159 		off += blksz;
2160 		resid -= len;
2161 	}
2162 out:
2163 	return err;
2164 }
2165 
2166 static int
2167 ptp_ocp_devlink_flash_update(struct devlink *devlink,
2168 			     struct devlink_flash_update_params *params,
2169 			     struct netlink_ext_ack *extack)
2170 {
2171 	struct ptp_ocp *bp = devlink_priv(devlink);
2172 	struct device *dev;
2173 	const char *msg;
2174 	int err;
2175 
2176 	if (params->component) {
2177 		if (!bp->has_cpld ||
2178 		    strcmp(params->component, ADVA_CPLD_COMPONENT)) {
2179 			NL_SET_ERR_MSG_MOD(extack,
2180 					   "unsupported flash component");
2181 			return -EOPNOTSUPP;
2182 		}
2183 
2184 		err = adva_x1_cpld_flash(bp, devlink, params->fw, extack);
2185 		msg = err ? "Flash error" : "Flash complete";
2186 		devlink_flash_update_status_notify(devlink, msg,
2187 						   ADVA_CPLD_COMPONENT, 0, 0);
2188 		return err;
2189 	}
2190 
2191 	dev = ptp_ocp_find_flash(bp);
2192 	if (!dev) {
2193 		dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
2194 		return -ENODEV;
2195 	}
2196 
2197 	devlink_flash_update_status_notify(devlink, "Preparing to flash",
2198 					   NULL, 0, 0);
2199 
2200 	err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
2201 
2202 	msg = err ? "Flash error" : "Flash complete";
2203 	devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
2204 
2205 	put_device(dev);
2206 	return err;
2207 }
2208 
2209 static int
2210 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
2211 			 struct netlink_ext_ack *extack)
2212 {
2213 	enum devlink_info_version_type ver_type =
2214 					DEVLINK_INFO_VERSION_TYPE_COMPONENT;
2215 	struct ptp_ocp *bp = devlink_priv(devlink);
2216 	const char *fw_image;
2217 	char buf[32];
2218 	int err;
2219 	u32 id;
2220 
2221 	fw_image = bp->fw_loader ? "loader" : "fw";
2222 	sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
2223 	err = devlink_info_version_running_put(req, fw_image, buf);
2224 	if (err)
2225 		return err;
2226 
2227 	if (bp->has_cpld) {
2228 		/* Read by the worker, not here: this command is unprivileged
2229 		 * and reading the ID claims the I2C bus.  0 means unread -
2230 		 * skip it rather than fail, devlink discards the whole reply
2231 		 * on error.
2232 		 */
2233 		id = READ_ONCE(bp->cpld_id);
2234 		if (id) {
2235 			sprintf(buf, "0x%08x", id);
2236 			err = devlink_info_version_fixed_put(req, "cpld.id",
2237 							     buf);
2238 			if (err)
2239 				return err;
2240 		}
2241 
2242 		/* The flashable component.  Naming it here is what lets
2243 		 * "devlink dev flash ... component fw.cpld" through, as the
2244 		 * core matches the name against the versions reported here,
2245 		 * so it is reported for every board that has the part and not
2246 		 * only once its USERCODE has been read: a part left holding a
2247 		 * bad image answers neither, and gating the component on the
2248 		 * read would make that state unrecoverable.
2249 		 */
2250 		if (smp_load_acquire(&bp->cpld_usercode_ok))
2251 			sprintf(buf, "0x%08x", READ_ONCE(bp->cpld_usercode));
2252 		else
2253 			strscpy(buf, "unknown", sizeof(buf));
2254 		err = devlink_info_version_running_put_ext(req, "fw.cpld", buf,
2255 							   ver_type);
2256 		if (err)
2257 			return err;
2258 	}
2259 
2260 	if (!bp->has_eeprom_data) {
2261 		ptp_ocp_read_eeprom(bp);
2262 		if (!bp->has_eeprom_data)
2263 			return 0;
2264 	}
2265 
2266 	sprintf(buf, "%pM", bp->serial);
2267 	err = devlink_info_serial_number_put(req, buf);
2268 	if (err)
2269 		return err;
2270 
2271 	snprintf(buf, sizeof(buf), "%.*s", OCP_BOARD_ID_LEN,
2272 		 (const char *)bp->board_id);
2273 	err = devlink_info_version_fixed_put(req,
2274 			DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
2275 			buf);
2276 	if (err)
2277 		return err;
2278 
2279 	return 0;
2280 }
2281 
2282 static const struct devlink_ops ptp_ocp_devlink_ops = {
2283 	.flash_update = ptp_ocp_devlink_flash_update,
2284 	.info_get = ptp_ocp_devlink_info_get,
2285 };
2286 
2287 static void __iomem *
2288 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
2289 {
2290 	struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
2291 
2292 	return devm_ioremap_resource(&bp->pdev->dev, &res);
2293 }
2294 
2295 static void __iomem *
2296 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2297 {
2298 	resource_size_t start;
2299 
2300 	start = pci_resource_start(bp->pdev, 0) + r->offset;
2301 	return __ptp_ocp_get_mem(bp, start, r->size);
2302 }
2303 
2304 static int
2305 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
2306 {
2307 	struct ptp_ocp_flash_info *info;
2308 	struct pci_dev *pdev = bp->pdev;
2309 	struct platform_device *p;
2310 	struct resource res[2];
2311 	resource_size_t start;
2312 	int id;
2313 
2314 	start = pci_resource_start(pdev, 0) + r->offset;
2315 	res[0] = DEFINE_RES_MEM(start, r->size);
2316 	res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2317 
2318 	info = r->extra;
2319 	id = pci_dev_id(pdev) << 1;
2320 	id += info->pci_offset;
2321 
2322 	p = platform_device_register_resndata(&pdev->dev, info->name, id,
2323 					      res, ARRAY_SIZE(res), info->data,
2324 					      info->data_size);
2325 	if (IS_ERR(p))
2326 		return PTR_ERR(p);
2327 
2328 	bp_assign_entry(bp, r, p);
2329 
2330 	return 0;
2331 }
2332 
2333 static struct platform_device *
2334 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
2335 {
2336 	struct ptp_ocp_i2c_info *info;
2337 	struct resource res[2];
2338 	resource_size_t start;
2339 
2340 	info = r->extra;
2341 	start = pci_resource_start(pdev, 0) + r->offset;
2342 	res[0] = DEFINE_RES_MEM(start, r->size);
2343 	res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2344 
2345 	return platform_device_register_resndata(&pdev->dev, info->name,
2346 						 id, res, ARRAY_SIZE(res),
2347 						 info->data, info->data_size);
2348 }
2349 
2350 static int
2351 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
2352 {
2353 	struct pci_dev *pdev = bp->pdev;
2354 	struct ptp_ocp_i2c_info *info;
2355 	struct platform_device *p;
2356 	struct clk_hw *clk;
2357 	char buf[32];
2358 	int id;
2359 
2360 	info = r->extra;
2361 	id = pci_dev_id(bp->pdev);
2362 
2363 	sprintf(buf, "AXI.%d", id);
2364 	clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2365 					 info->fixed_rate);
2366 	if (IS_ERR(clk))
2367 		return PTR_ERR(clk);
2368 	bp->i2c_clk = clk;
2369 
2370 	sprintf(buf, "%s.%d", info->name, id);
2371 	devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2372 	p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2373 	if (IS_ERR(p))
2374 		return PTR_ERR(p);
2375 
2376 	bp_assign_entry(bp, r, p);
2377 
2378 	return 0;
2379 }
2380 
2381 /* The expectation is that this is triggered only on error. */
2382 static irqreturn_t
2383 ptp_ocp_signal_irq(int irq, void *priv)
2384 {
2385 	struct ptp_ocp_ext_src *ext = priv;
2386 	struct signal_reg __iomem *reg = ext->mem;
2387 	struct ptp_ocp *bp = ext->bp;
2388 	u32 enable, status;
2389 	int gen;
2390 
2391 	gen = ext->info->index - 1;
2392 
2393 	enable = ioread32(&reg->enable);
2394 	status = ioread32(&reg->status);
2395 
2396 	/* disable generator on error */
2397 	if (status || !enable) {
2398 		iowrite32(0, &reg->intr_mask);
2399 		iowrite32(0, &reg->enable);
2400 		bp->signal[gen].running = false;
2401 	}
2402 
2403 	iowrite32(0, &reg->intr);	/* ack interrupt */
2404 
2405 	return IRQ_HANDLED;
2406 }
2407 
2408 static int
2409 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2410 {
2411 	struct ptp_system_timestamp sts;
2412 	struct timespec64 ts;
2413 	ktime_t start_ns;
2414 	int err;
2415 
2416 	if (!s->period)
2417 		return 0;
2418 
2419 	if (!s->pulse)
2420 		s->pulse = ktime_divns(s->period * s->duty, 100);
2421 
2422 	err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2423 	if (err)
2424 		return err;
2425 
2426 	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2427 	if (!s->start) {
2428 		/* roundup() does not work on 32-bit systems */
2429 		s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2430 		s->start *= s->period;
2431 		s->start = ktime_add(s->start, s->phase);
2432 	}
2433 
2434 	if (s->duty < 1 || s->duty > 99)
2435 		return -EINVAL;
2436 
2437 	if (s->pulse < 1 || s->pulse > s->period)
2438 		return -EINVAL;
2439 
2440 	if (s->start < start_ns)
2441 		return -EINVAL;
2442 
2443 	bp->signal[gen] = *s;
2444 
2445 	return 0;
2446 }
2447 
2448 static int
2449 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2450 			   struct ptp_perout_request *req)
2451 {
2452 	struct ptp_ocp_signal s = { };
2453 
2454 	s.polarity = bp->signal[gen].polarity;
2455 	s.period = ktime_set(req->period.sec, req->period.nsec);
2456 	if (!s.period)
2457 		return 0;
2458 
2459 	if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2460 		s.pulse = ktime_set(req->on.sec, req->on.nsec);
2461 		s.duty = ktime_divns(s.pulse * 100, s.period);
2462 	}
2463 
2464 	if (req->flags & PTP_PEROUT_PHASE)
2465 		s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2466 	else
2467 		s.start = ktime_set(req->start.sec, req->start.nsec);
2468 
2469 	return ptp_ocp_signal_set(bp, gen, &s);
2470 }
2471 
2472 static int
2473 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2474 {
2475 	struct ptp_ocp_ext_src *ext = priv;
2476 	struct signal_reg __iomem *reg = ext->mem;
2477 	struct ptp_ocp *bp = ext->bp;
2478 	struct timespec64 ts;
2479 	int gen;
2480 
2481 	gen = ext->info->index - 1;
2482 
2483 	iowrite32(0, &reg->intr_mask);
2484 	iowrite32(0, &reg->enable);
2485 	bp->signal[gen].running = false;
2486 	if (!enable)
2487 		return 0;
2488 
2489 	ts = ktime_to_timespec64(bp->signal[gen].start);
2490 	iowrite32(ts.tv_sec, &reg->start_sec);
2491 	iowrite32(ts.tv_nsec, &reg->start_ns);
2492 
2493 	ts = ktime_to_timespec64(bp->signal[gen].period);
2494 	iowrite32(ts.tv_sec, &reg->period_sec);
2495 	iowrite32(ts.tv_nsec, &reg->period_ns);
2496 
2497 	ts = ktime_to_timespec64(bp->signal[gen].pulse);
2498 	iowrite32(ts.tv_sec, &reg->pulse_sec);
2499 	iowrite32(ts.tv_nsec, &reg->pulse_ns);
2500 
2501 	iowrite32(bp->signal[gen].polarity, &reg->polarity);
2502 	iowrite32(0, &reg->repeat_count);
2503 
2504 	iowrite32(0, &reg->intr);		/* clear interrupt state */
2505 	iowrite32(1, &reg->intr_mask);		/* enable interrupt */
2506 	iowrite32(3, &reg->enable);		/* valid & enable */
2507 
2508 	bp->signal[gen].running = true;
2509 
2510 	return 0;
2511 }
2512 
2513 static irqreturn_t
2514 ptp_ocp_ts_irq(int irq, void *priv)
2515 {
2516 	struct ptp_ocp_ext_src *ext = priv;
2517 	struct ts_reg __iomem *reg = ext->mem;
2518 	struct ptp_clock_event ev;
2519 	u32 sec, nsec;
2520 
2521 	if (ext == ext->bp->pps) {
2522 		if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2523 			ev.type = PTP_CLOCK_PPS;
2524 			ptp_clock_event(ext->bp->ptp, &ev);
2525 		}
2526 
2527 		if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2528 			goto out;
2529 	}
2530 
2531 	/* XXX should fix API - this converts s/ns -> ts -> s/ns */
2532 	sec = ioread32(&reg->time_sec);
2533 	nsec = ioread32(&reg->time_ns);
2534 
2535 	ev.type = PTP_CLOCK_EXTTS;
2536 	ev.index = ext->info->index;
2537 	ev.timestamp = sec * NSEC_PER_SEC + nsec;
2538 
2539 	ptp_clock_event(ext->bp->ptp, &ev);
2540 
2541 out:
2542 	iowrite32(1, &reg->intr);	/* write 1 to ack */
2543 
2544 	return IRQ_HANDLED;
2545 }
2546 
2547 static int
2548 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2549 {
2550 	struct ptp_ocp_ext_src *ext = priv;
2551 	struct ts_reg __iomem *reg = ext->mem;
2552 	struct ptp_ocp *bp = ext->bp;
2553 
2554 	if (ext == bp->pps) {
2555 		u32 old_map = bp->pps_req_map;
2556 
2557 		if (enable)
2558 			bp->pps_req_map |= req;
2559 		else
2560 			bp->pps_req_map &= ~req;
2561 
2562 		/* if no state change, just return */
2563 		if ((!!old_map ^ !!bp->pps_req_map) == 0)
2564 			return 0;
2565 	}
2566 
2567 	if (enable) {
2568 		iowrite32(1, &reg->enable);
2569 		iowrite32(1, &reg->intr_mask);
2570 		iowrite32(1, &reg->intr);
2571 	} else {
2572 		int irq_vec = pci_irq_vector(bp->pdev, ext->irq_vec);
2573 
2574 		iowrite32(0, &reg->intr_mask);
2575 		iowrite32(0, &reg->enable);
2576 		ioread32(&reg->intr_mask);
2577 		if (irq_vec > 0)
2578 			synchronize_irq(irq_vec);
2579 	}
2580 
2581 	return 0;
2582 }
2583 
2584 static void
2585 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2586 {
2587 	if (!ext)
2588 		return;
2589 
2590 	ext->info->enable(ext, ~0, false);
2591 	pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2592 	kfree(ext);
2593 }
2594 
2595 static int
2596 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2597 {
2598 	struct pci_dev *pdev = bp->pdev;
2599 	struct ptp_ocp_ext_src *ext;
2600 	int err;
2601 
2602 	ext = kzalloc_obj(*ext);
2603 	if (!ext)
2604 		return -ENOMEM;
2605 
2606 	ext->mem = ptp_ocp_get_mem(bp, r);
2607 	if (IS_ERR(ext->mem)) {
2608 		err = PTR_ERR(ext->mem);
2609 		goto out;
2610 	}
2611 
2612 	ext->bp = bp;
2613 	ext->info = r->extra;
2614 	ext->irq_vec = r->irq_vec;
2615 
2616 	err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2617 			      ext, "ocp%d.%s", bp->id, r->name);
2618 	if (err) {
2619 		dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2620 		goto out;
2621 	}
2622 
2623 	bp_assign_entry(bp, r, ext);
2624 
2625 	return 0;
2626 
2627 out:
2628 	kfree(ext);
2629 	return err;
2630 }
2631 
2632 static struct uart_8250_port *
2633 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2634 {
2635 	struct pci_dev *pdev = bp->pdev;
2636 	struct uart_8250_port uart;
2637 
2638 	/* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2639 	 * the serial port device claim and release the pci resource.
2640 	 */
2641 	memset(&uart, 0, sizeof(uart));
2642 	uart.port.dev = &pdev->dev;
2643 	uart.port.iotype = UPIO_MEM;
2644 	uart.port.regshift = 2;
2645 	uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2646 	uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2647 	uart.port.uartclk = 50000000;
2648 	uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2649 	uart.port.type = PORT_16550A;
2650 
2651 	return serial8250_register_8250_port(&uart);
2652 }
2653 
2654 static int
2655 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2656 {
2657 	struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2658 	struct ptp_ocp_serial_port port = {};
2659 
2660 	struct uart_8250_port *uport = ptp_ocp_serial_line(bp, r);
2661 	if (IS_ERR(uport))
2662 		return PTR_ERR(uport);
2663 
2664 	port.uport = uport;
2665 
2666 	if (p)
2667 		port.baud = p->baud;
2668 
2669 	bp_assign_entry(bp, r, port);
2670 
2671 	return 0;
2672 }
2673 
2674 static int
2675 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2676 {
2677 	void __iomem *mem;
2678 
2679 	mem = ptp_ocp_get_mem(bp, r);
2680 	if (IS_ERR(mem))
2681 		return PTR_ERR(mem);
2682 
2683 	bp_assign_entry(bp, r, mem);
2684 
2685 	return 0;
2686 }
2687 
2688 static void
2689 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2690 {
2691 	if (!bp->nmea_out)
2692 		return;
2693 
2694 	iowrite32(0, &bp->nmea_out->ctrl);		/* disable */
2695 	iowrite32(7, &bp->nmea_out->uart_baud);		/* 115200 */
2696 	iowrite32(1, &bp->nmea_out->ctrl);		/* enable */
2697 }
2698 
2699 static void
2700 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2701 {
2702 	u32 val;
2703 
2704 	iowrite32(0, &reg->enable);		/* disable */
2705 
2706 	val = ioread32(&reg->polarity);
2707 	s->polarity = val ? true : false;
2708 	s->duty = 50;
2709 }
2710 
2711 static void
2712 ptp_ocp_signal_init(struct ptp_ocp *bp)
2713 {
2714 	int i;
2715 
2716 	for (i = 0; i < 4; i++)
2717 		if (bp->signal_out[i])
2718 			_ptp_ocp_signal_init(&bp->signal[i],
2719 					     bp->signal_out[i]->mem);
2720 }
2721 
2722 static void
2723 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2724 {
2725 	sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2726 	kfree(bp->attr_group);
2727 }
2728 
2729 static int
2730 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2731 		       const struct ocp_attr_group *attr_tbl)
2732 {
2733 	int count, i;
2734 	int err;
2735 
2736 	count = 0;
2737 	for (i = 0; attr_tbl[i].cap; i++)
2738 		if (attr_tbl[i].cap & bp->fw_cap)
2739 			count++;
2740 
2741 	bp->attr_group = kzalloc_objs(*bp->attr_group, count + 1);
2742 	if (!bp->attr_group)
2743 		return -ENOMEM;
2744 
2745 	count = 0;
2746 	for (i = 0; attr_tbl[i].cap; i++)
2747 		if (attr_tbl[i].cap & bp->fw_cap)
2748 			bp->attr_group[count++] = attr_tbl[i].group;
2749 
2750 	err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2751 	if (err)
2752 		bp->attr_group[0] = NULL;
2753 
2754 	return err;
2755 }
2756 
2757 static void
2758 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2759 {
2760 	u32 ctrl;
2761 	bool on;
2762 
2763 	ctrl = ioread32(reg);
2764 	on = ctrl & bit;
2765 	if (on ^ enable) {
2766 		ctrl &= ~bit;
2767 		ctrl |= enable ? bit : 0;
2768 		iowrite32(ctrl, reg);
2769 	}
2770 }
2771 
2772 static void
2773 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2774 {
2775 	return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2776 				   IRIG_M_CTRL_ENABLE, enable);
2777 }
2778 
2779 static void
2780 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2781 {
2782 	return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2783 				   IRIG_S_CTRL_ENABLE, enable);
2784 }
2785 
2786 static void
2787 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2788 {
2789 	return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2790 				   DCF_M_CTRL_ENABLE, enable);
2791 }
2792 
2793 static void
2794 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2795 {
2796 	return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2797 				   DCF_S_CTRL_ENABLE, enable);
2798 }
2799 
2800 static void
2801 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2802 {
2803 	ptp_ocp_irig_out(bp, val & 0x00100010);
2804 	ptp_ocp_dcf_out(bp, val & 0x00200020);
2805 }
2806 
2807 static void
2808 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2809 {
2810 	ptp_ocp_irig_in(bp, val & 0x00100010);
2811 	ptp_ocp_dcf_in(bp, val & 0x00200020);
2812 }
2813 
2814 static u32
2815 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2816 {
2817 	u32 __iomem *gpio;
2818 	u32 shift;
2819 
2820 	if (bp->sma[sma_nr - 1].fixed_fcn)
2821 		return (sma_nr - 1) & 1;
2822 
2823 	if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2824 		gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2825 	else
2826 		gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2827 	shift = sma_nr & 1 ? 0 : 16;
2828 
2829 	return (ioread32(gpio) >> shift) & 0xffff;
2830 }
2831 
2832 static int
2833 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2834 {
2835 	u32 reg, mask, shift;
2836 	unsigned long flags;
2837 	u32 __iomem *gpio;
2838 
2839 	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2840 	shift = sma_nr & 1 ? 0 : 16;
2841 
2842 	mask = 0xffff << (16 - shift);
2843 
2844 	spin_lock_irqsave(&bp->lock, flags);
2845 
2846 	reg = ioread32(gpio);
2847 	reg = (reg & mask) | (val << shift);
2848 
2849 	__handle_signal_outputs(bp, reg);
2850 
2851 	iowrite32(reg, gpio);
2852 
2853 	spin_unlock_irqrestore(&bp->lock, flags);
2854 
2855 	return 0;
2856 }
2857 
2858 static int
2859 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2860 {
2861 	u32 reg, mask, shift;
2862 	unsigned long flags;
2863 	u32 __iomem *gpio;
2864 
2865 	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2866 	shift = sma_nr & 1 ? 0 : 16;
2867 
2868 	mask = 0xffff << (16 - shift);
2869 
2870 	spin_lock_irqsave(&bp->lock, flags);
2871 
2872 	reg = ioread32(gpio);
2873 	reg = (reg & mask) | (val << shift);
2874 
2875 	__handle_signal_inputs(bp, reg);
2876 
2877 	iowrite32(reg, gpio);
2878 
2879 	spin_unlock_irqrestore(&bp->lock, flags);
2880 
2881 	return 0;
2882 }
2883 
2884 static void
2885 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2886 {
2887 	struct dpll_pin_properties prop = {
2888 		.board_label = NULL,
2889 		.type = DPLL_PIN_TYPE_EXT,
2890 		.capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2891 		.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2892 		.freq_supported = ptp_ocp_sma_freq,
2893 
2894 	};
2895 	u32 reg;
2896 	int i;
2897 
2898 	/* defaults */
2899 	for (i = 0; i < OCP_SMA_NUM; i++) {
2900 		bp->sma[i].default_fcn = i & 1;
2901 		bp->sma[i].dpll_prop = prop;
2902 		bp->sma[i].dpll_prop.board_label =
2903 			bp->ptp_info.pin_config[i].name;
2904 	}
2905 	bp->sma[0].mode = SMA_MODE_IN;
2906 	bp->sma[1].mode = SMA_MODE_IN;
2907 	bp->sma[2].mode = SMA_MODE_OUT;
2908 	bp->sma[3].mode = SMA_MODE_OUT;
2909 	/* If no SMA1 map, the pin functions and directions are fixed. */
2910 	if (!bp->sma_map1) {
2911 		for (i = 0; i < OCP_SMA_NUM; i++) {
2912 			bp->sma[i].fixed_fcn = true;
2913 			bp->sma[i].fixed_dir = true;
2914 			bp->sma[i].dpll_prop.capabilities &=
2915 				~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2916 		}
2917 		return;
2918 	}
2919 
2920 	/* If SMA2 GPIO output map is all 1, it is not present.
2921 	 * This indicates the firmware has fixed direction SMA pins.
2922 	 */
2923 	reg = ioread32(&bp->sma_map2->gpio2);
2924 	if (reg == 0xffffffff) {
2925 		for (i = 0; i < OCP_SMA_NUM; i++)
2926 			bp->sma[i].fixed_dir = true;
2927 	} else {
2928 		reg = ioread32(&bp->sma_map1->gpio1);
2929 		bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2930 		bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2931 
2932 		reg = ioread32(&bp->sma_map1->gpio2);
2933 		bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2934 		bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2935 	}
2936 }
2937 
2938 static const struct ocp_sma_op ocp_fb_sma_op = {
2939 	.tbl		= { ptp_ocp_sma_in, ptp_ocp_sma_out },
2940 	.init		= ptp_ocp_sma_fb_init,
2941 	.get		= ptp_ocp_sma_fb_get,
2942 	.set_inputs	= ptp_ocp_sma_fb_set_inputs,
2943 	.set_output	= ptp_ocp_sma_fb_set_output,
2944 };
2945 
2946 static int
2947 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2948 {
2949 	u32 reg, mask, shift;
2950 	unsigned long flags;
2951 	u32 __iomem *gpio;
2952 
2953 	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2954 	shift = sma_nr & 1 ? 0 : 16;
2955 
2956 	mask = 0xffff << (16 - shift);
2957 
2958 	spin_lock_irqsave(&bp->lock, flags);
2959 
2960 	reg = ioread32(gpio);
2961 	reg = (reg & mask) | (val << shift);
2962 
2963 	iowrite32(reg, gpio);
2964 
2965 	spin_unlock_irqrestore(&bp->lock, flags);
2966 
2967 	return 0;
2968 }
2969 
2970 static int
2971 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2972 {
2973 	u32 reg, mask, shift;
2974 	unsigned long flags;
2975 	u32 __iomem *gpio;
2976 
2977 	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2978 	shift = sma_nr & 1 ? 0 : 16;
2979 
2980 	mask = 0xffff << (16 - shift);
2981 
2982 	spin_lock_irqsave(&bp->lock, flags);
2983 
2984 	reg = ioread32(gpio);
2985 	reg = (reg & mask) | (val << shift);
2986 
2987 	iowrite32(reg, gpio);
2988 
2989 	spin_unlock_irqrestore(&bp->lock, flags);
2990 
2991 	return 0;
2992 }
2993 
2994 static const struct ocp_sma_op ocp_adva_sma_op = {
2995 	.tbl		= { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2996 	.init		= ptp_ocp_sma_fb_init,
2997 	.get		= ptp_ocp_sma_fb_get,
2998 	.set_inputs	= ptp_ocp_sma_adva_set_inputs,
2999 	.set_output	= ptp_ocp_sma_adva_set_output,
3000 };
3001 
3002 static const struct ocp_sma_op ocp_adva_x1_sma_op = {
3003 	.tbl		= { ptp_ocp_adva_x1_sma_in, ptp_ocp_adva_x1_sma_out },
3004 	.init		= ptp_ocp_sma_fb_init,
3005 	.get		= ptp_ocp_sma_fb_get,
3006 	.set_inputs	= ptp_ocp_sma_adva_set_inputs,
3007 	.set_output	= ptp_ocp_sma_adva_set_output,
3008 };
3009 
3010 static int
3011 ptp_ocp_set_pins(struct ptp_ocp *bp)
3012 {
3013 	struct ptp_pin_desc *config;
3014 	int i;
3015 
3016 	config = kzalloc_objs(*config, 4);
3017 	if (!config)
3018 		return -ENOMEM;
3019 
3020 	for (i = 0; i < 4; i++) {
3021 		sprintf(config[i].name, "sma%d", i + 1);
3022 		config[i].index = i;
3023 	}
3024 
3025 	bp->ptp_info.n_pins = 4;
3026 	bp->ptp_info.pin_config = config;
3027 
3028 	return 0;
3029 }
3030 
3031 static void
3032 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
3033 {
3034 	u64 cap = OCP_CAP_BASIC;
3035 	u32 version;
3036 
3037 	version = ioread32(&bp->image->version);
3038 
3039 	/* if lower 16 bits are empty, this is the fw loader. */
3040 	if ((version & 0xffff) == 0) {
3041 		version = version >> 16;
3042 		bp->fw_loader = true;
3043 	}
3044 
3045 	bp->fw_tag = version >> 15;
3046 	bp->fw_version = version & 0x7fff;
3047 
3048 	if (bp->fw_tag) {
3049 		/* FPGA firmware */
3050 		if (version >= 5)
3051 			cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
3052 	} else {
3053 		/* SOM firmware */
3054 		if (version >= 19)
3055 			cap |= OCP_CAP_SIGNAL;
3056 		if (version >= 20)
3057 			cap |= OCP_CAP_FREQ;
3058 	}
3059 
3060 	bp->fw_cap = cap;
3061 }
3062 
3063 /* FB specific board initializers; last "resource" registered. */
3064 static int
3065 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3066 {
3067 	int err;
3068 
3069 	bp->flash_start = 1024 * 4096;
3070 	bp->eeprom_map = fb_eeprom_map;
3071 	bp->fw_version = ioread32(&bp->image->version);
3072 	bp->sma_op = &ocp_fb_sma_op;
3073 	bp->signals_nr = 4;
3074 	bp->freq_in_nr = 4;
3075 
3076 	ptp_ocp_fb_set_version(bp);
3077 
3078 	ptp_ocp_tod_init(bp);
3079 	ptp_ocp_nmea_out_init(bp);
3080 	ptp_ocp_signal_init(bp);
3081 
3082 	err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
3083 	if (err)
3084 		return err;
3085 
3086 	err = ptp_ocp_set_pins(bp);
3087 	if (err)
3088 		return err;
3089 	ptp_ocp_sma_init(bp);
3090 
3091 	return ptp_ocp_init_clock(bp, r->extra);
3092 }
3093 
3094 static bool
3095 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
3096 {
3097 	bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
3098 
3099 	if (!allow)
3100 		dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
3101 			r->irq_vec, r->name);
3102 	return allow;
3103 }
3104 
3105 static int
3106 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
3107 {
3108 	struct ocp_resource *r, *table;
3109 	int err = 0;
3110 
3111 	table = (struct ocp_resource *)driver_data;
3112 	for (r = table; r->setup; r++) {
3113 		if (!ptp_ocp_allow_irq(bp, r))
3114 			continue;
3115 		err = r->setup(bp, r);
3116 		if (err) {
3117 			dev_err(&bp->pdev->dev,
3118 				"Could not register %s: err %d\n",
3119 				r->name, err);
3120 			break;
3121 		}
3122 	}
3123 	return err;
3124 }
3125 
3126 static void
3127 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
3128 {
3129 	struct dpll_pin_properties prop = {
3130 		.board_label = NULL,
3131 		.type = DPLL_PIN_TYPE_EXT,
3132 		.capabilities = 0,
3133 		.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
3134 		.freq_supported = ptp_ocp_sma_freq,
3135 
3136 	};
3137 	u32 reg;
3138 	int i;
3139 
3140 	/* defaults */
3141 	bp->sma[0].mode = SMA_MODE_IN;
3142 	bp->sma[1].mode = SMA_MODE_IN;
3143 	bp->sma[2].mode = SMA_MODE_OUT;
3144 	bp->sma[3].mode = SMA_MODE_OUT;
3145 
3146 	bp->sma[0].default_fcn = 0x08;	/* IN: 10Mhz */
3147 	bp->sma[1].default_fcn = 0x01;	/* IN: PPS1 */
3148 	bp->sma[2].default_fcn = 0x10;	/* OUT: 10Mhz */
3149 	bp->sma[3].default_fcn = 0x02;	/* OUT: PHC */
3150 
3151 	for (i = 0; i < OCP_SMA_NUM; i++) {
3152 		/* If no SMA map, the pin functions and directions are fixed. */
3153 		bp->sma[i].dpll_prop = prop;
3154 		bp->sma[i].dpll_prop.board_label =
3155 			bp->ptp_info.pin_config[i].name;
3156 		if (!bp->art_sma) {
3157 			bp->sma[i].fixed_fcn = true;
3158 			bp->sma[i].fixed_dir = true;
3159 			continue;
3160 		}
3161 		reg = ioread32(&bp->art_sma->map[i].gpio);
3162 
3163 		switch (reg & 0xff) {
3164 		case 0:
3165 			bp->sma[i].fixed_fcn = true;
3166 			bp->sma[i].fixed_dir = true;
3167 			break;
3168 		case 1:
3169 		case 8:
3170 			bp->sma[i].mode = SMA_MODE_IN;
3171 			bp->sma[i].dpll_prop.capabilities =
3172 				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3173 			break;
3174 		default:
3175 			bp->sma[i].mode = SMA_MODE_OUT;
3176 			bp->sma[i].dpll_prop.capabilities =
3177 				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3178 			break;
3179 		}
3180 	}
3181 }
3182 
3183 static u32
3184 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
3185 {
3186 	if (bp->sma[sma_nr - 1].fixed_fcn)
3187 		return bp->sma[sma_nr - 1].default_fcn;
3188 
3189 	return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
3190 }
3191 
3192 /* note: store 0 is considered invalid. */
3193 static int
3194 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
3195 {
3196 	unsigned long flags;
3197 	u32 __iomem *gpio;
3198 	int err = 0;
3199 	u32 reg;
3200 
3201 	val &= SMA_SELECT_MASK;
3202 	if (hweight32(val) > 1)
3203 		return -EINVAL;
3204 
3205 	gpio = &bp->art_sma->map[sma_nr - 1].gpio;
3206 
3207 	spin_lock_irqsave(&bp->lock, flags);
3208 	reg = ioread32(gpio);
3209 	if (((reg >> 16) & val) == 0) {
3210 		err = -EOPNOTSUPP;
3211 	} else {
3212 		reg = (reg & 0xff00) | (val & 0xff);
3213 		iowrite32(reg, gpio);
3214 	}
3215 	spin_unlock_irqrestore(&bp->lock, flags);
3216 
3217 	return err;
3218 }
3219 
3220 static const struct ocp_sma_op ocp_art_sma_op = {
3221 	.tbl		= { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
3222 	.init		= ptp_ocp_art_sma_init,
3223 	.get		= ptp_ocp_art_sma_get,
3224 	.set_inputs	= ptp_ocp_art_sma_set,
3225 	.set_output	= ptp_ocp_art_sma_set,
3226 };
3227 
3228 /* ART specific board initializers; last "resource" registered. */
3229 static int
3230 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3231 {
3232 	int err;
3233 
3234 	bp->flash_start = 0x1000000;
3235 	bp->eeprom_map = art_eeprom_map;
3236 	bp->fw_cap = OCP_CAP_BASIC;
3237 	bp->fw_version = ioread32(&bp->reg->version);
3238 	bp->fw_tag = 2;
3239 	bp->sma_op = &ocp_art_sma_op;
3240 	bp->signals_nr = 4;
3241 	bp->freq_in_nr = 4;
3242 
3243 	/* Enable MAC serial port during initialisation */
3244 	iowrite32(1, &bp->board_config->mro50_serial_activate);
3245 
3246 	err = ptp_ocp_set_pins(bp);
3247 	if (err)
3248 		return err;
3249 	ptp_ocp_sma_init(bp);
3250 
3251 	err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
3252 	if (err)
3253 		return err;
3254 
3255 	return ptp_ocp_init_clock(bp, r->extra);
3256 }
3257 
3258 /* ADVA board initializer; variant differences come from r->extra. */
3259 static int
3260 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3261 {
3262 	struct ptp_ocp_adva_info *info = r->extra;
3263 	u32 version;
3264 	int err;
3265 
3266 	bp->flash_start = info->flash_start;
3267 	bp->eeprom_map  = fb_eeprom_map;
3268 	bp->sma_op      = info->sma_op;
3269 	bp->signals_nr  = info->signals_nr;
3270 	bp->freq_in_nr  = info->freq_in_nr;
3271 
3272 	version = ioread32(&bp->image->version);
3273 	/* if lower 16 bits are empty, this is the fw loader. */
3274 	if ((version & 0xffff) == 0) {
3275 		version = version >> 16;
3276 		bp->fw_loader = true;
3277 	}
3278 	bp->fw_tag     = 3;
3279 	bp->fw_version = version & 0xffff;
3280 	bp->fw_cap     = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
3281 
3282 	ptp_ocp_tod_init(bp);
3283 	ptp_ocp_nmea_out_init(bp);
3284 	ptp_ocp_signal_init(bp);
3285 
3286 	err = ptp_ocp_attr_group_add(bp, info->attr_groups);
3287 	if (err)
3288 		return err;
3289 
3290 	err = ptp_ocp_set_pins(bp);
3291 	if (err)
3292 		return err;
3293 	ptp_ocp_sma_init(bp);
3294 
3295 	bp->has_cpld = info->has_cpld;
3296 
3297 	return ptp_ocp_init_clock(bp, &info->servo);
3298 }
3299 
3300 static ssize_t
3301 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
3302 		    int def_val)
3303 {
3304 	const char *name;
3305 	ssize_t count;
3306 
3307 	count = sysfs_emit(buf, "OUT: ");
3308 	name = ptp_ocp_select_name_from_val(tbl, val);
3309 	if (!name)
3310 		name = ptp_ocp_select_name_from_val(tbl, def_val);
3311 	count += sysfs_emit_at(buf, count, "%s\n", name);
3312 	return count;
3313 }
3314 
3315 static ssize_t
3316 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
3317 		    int def_val)
3318 {
3319 	const char *name;
3320 	ssize_t count;
3321 	int i;
3322 
3323 	count = sysfs_emit(buf, "IN: ");
3324 	for (i = 0; tbl[i].name; i++) {
3325 		if (val & tbl[i].value) {
3326 			name = tbl[i].name;
3327 			count += sysfs_emit_at(buf, count, "%s ", name);
3328 		}
3329 	}
3330 	if (!val && def_val >= 0) {
3331 		name = ptp_ocp_select_name_from_val(tbl, def_val);
3332 		count += sysfs_emit_at(buf, count, "%s ", name);
3333 	}
3334 	if (count)
3335 		count--;
3336 	count += sysfs_emit_at(buf, count, "\n");
3337 	return count;
3338 }
3339 
3340 static int
3341 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
3342 		 enum ptp_ocp_sma_mode *mode)
3343 {
3344 	int idx, count, dir;
3345 	char **argv;
3346 	int ret;
3347 
3348 	argv = argv_split(GFP_KERNEL, buf, &count);
3349 	if (!argv)
3350 		return -ENOMEM;
3351 
3352 	ret = -EINVAL;
3353 	if (!count)
3354 		goto out;
3355 
3356 	idx = 0;
3357 	dir = *mode == SMA_MODE_IN ? 0 : 1;
3358 	if (!strcasecmp("IN:", argv[0])) {
3359 		dir = 0;
3360 		idx++;
3361 	}
3362 	if (!strcasecmp("OUT:", argv[0])) {
3363 		dir = 1;
3364 		idx++;
3365 	}
3366 	*mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
3367 
3368 	ret = 0;
3369 	for (; idx < count; idx++)
3370 		ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
3371 	if (ret < 0)
3372 		ret = -EINVAL;
3373 
3374 out:
3375 	argv_free(argv);
3376 	return ret;
3377 }
3378 
3379 static ssize_t
3380 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3381 		 int default_in_val, int default_out_val)
3382 {
3383 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3384 	const struct ocp_selector * const *tbl;
3385 	u32 val;
3386 
3387 	tbl = bp->sma_op->tbl;
3388 	val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3389 
3390 	if (sma->mode == SMA_MODE_IN) {
3391 		if (sma->disabled)
3392 			val = SMA_DISABLE;
3393 		return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3394 	}
3395 
3396 	return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3397 }
3398 
3399 static ssize_t
3400 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3401 {
3402 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3403 
3404 	return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3405 }
3406 
3407 static ssize_t
3408 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3409 {
3410 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3411 
3412 	return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3413 }
3414 
3415 static ssize_t
3416 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3417 {
3418 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3419 
3420 	return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3421 }
3422 
3423 static ssize_t
3424 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3425 {
3426 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3427 
3428 	return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3429 }
3430 
3431 static int
3432 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3433 {
3434 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3435 
3436 	if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3437 		return -EOPNOTSUPP;
3438 
3439 	if (sma->fixed_fcn) {
3440 		if (val != sma->default_fcn)
3441 			return -EOPNOTSUPP;
3442 		return 0;
3443 	}
3444 
3445 	sma->disabled = !!(val & SMA_DISABLE);
3446 
3447 	if (mode != sma->mode) {
3448 		if (mode == SMA_MODE_IN)
3449 			ptp_ocp_sma_set_output(bp, sma_nr, 0);
3450 		else
3451 			ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3452 		sma->mode = mode;
3453 	}
3454 
3455 	if (!sma->fixed_dir)
3456 		val |= SMA_ENABLE;		/* add enable bit */
3457 
3458 	if (sma->disabled)
3459 		val = 0;
3460 
3461 	if (mode == SMA_MODE_IN)
3462 		val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3463 	else
3464 		val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3465 
3466 	return val;
3467 }
3468 
3469 static int
3470 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3471 {
3472 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3473 	enum ptp_ocp_sma_mode mode;
3474 	int val;
3475 
3476 	mode = sma->mode;
3477 	val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3478 	if (val < 0)
3479 		return val;
3480 	return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3481 }
3482 
3483 static ssize_t
3484 sma1_store(struct device *dev, struct device_attribute *attr,
3485 	   const char *buf, size_t count)
3486 {
3487 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3488 	int err;
3489 
3490 	err = ptp_ocp_sma_store(bp, buf, 1);
3491 	return err ? err : count;
3492 }
3493 
3494 static ssize_t
3495 sma2_store(struct device *dev, struct device_attribute *attr,
3496 	   const char *buf, size_t count)
3497 {
3498 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3499 	int err;
3500 
3501 	err = ptp_ocp_sma_store(bp, buf, 2);
3502 	return err ? err : count;
3503 }
3504 
3505 static ssize_t
3506 sma3_store(struct device *dev, struct device_attribute *attr,
3507 	   const char *buf, size_t count)
3508 {
3509 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3510 	int err;
3511 
3512 	err = ptp_ocp_sma_store(bp, buf, 3);
3513 	return err ? err : count;
3514 }
3515 
3516 static ssize_t
3517 sma4_store(struct device *dev, struct device_attribute *attr,
3518 	   const char *buf, size_t count)
3519 {
3520 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3521 	int err;
3522 
3523 	err = ptp_ocp_sma_store(bp, buf, 4);
3524 	return err ? err : count;
3525 }
3526 static DEVICE_ATTR_RW(sma1);
3527 static DEVICE_ATTR_RW(sma2);
3528 static DEVICE_ATTR_RW(sma3);
3529 static DEVICE_ATTR_RW(sma4);
3530 
3531 static ssize_t
3532 available_sma_inputs_show(struct device *dev,
3533 			  struct device_attribute *attr, char *buf)
3534 {
3535 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3536 
3537 	return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3538 }
3539 static DEVICE_ATTR_RO(available_sma_inputs);
3540 
3541 static ssize_t
3542 available_sma_outputs_show(struct device *dev,
3543 			   struct device_attribute *attr, char *buf)
3544 {
3545 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3546 
3547 	return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3548 }
3549 static DEVICE_ATTR_RO(available_sma_outputs);
3550 
3551 #define EXT_ATTR_RO(_group, _name, _val)				\
3552 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
3553 		{ __ATTR_RO(_name), (void *)_val }
3554 #define EXT_ATTR_RW(_group, _name, _val)				\
3555 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
3556 		{ __ATTR_RW(_name), (void *)_val }
3557 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3558 
3559 /* period [duty [phase [polarity]]] */
3560 static ssize_t
3561 signal_store(struct device *dev, struct device_attribute *attr,
3562 	     const char *buf, size_t count)
3563 {
3564 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3565 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3566 	struct ptp_ocp_signal s = { };
3567 	int gen = (uintptr_t)ea->var;
3568 	int argc, err;
3569 	char **argv;
3570 
3571 	argv = argv_split(GFP_KERNEL, buf, &argc);
3572 	if (!argv)
3573 		return -ENOMEM;
3574 
3575 	err = -EINVAL;
3576 	s.duty = bp->signal[gen].duty;
3577 	s.phase = bp->signal[gen].phase;
3578 	s.period = bp->signal[gen].period;
3579 	s.polarity = bp->signal[gen].polarity;
3580 
3581 	switch (argc) {
3582 	case 4:
3583 		argc--;
3584 		err = kstrtobool(argv[argc], &s.polarity);
3585 		if (err)
3586 			goto out;
3587 		fallthrough;
3588 	case 3:
3589 		argc--;
3590 		err = kstrtou64(argv[argc], 0, &s.phase);
3591 		if (err)
3592 			goto out;
3593 		fallthrough;
3594 	case 2:
3595 		argc--;
3596 		err = kstrtoint(argv[argc], 0, &s.duty);
3597 		if (err)
3598 			goto out;
3599 		fallthrough;
3600 	case 1:
3601 		argc--;
3602 		err = kstrtou64(argv[argc], 0, &s.period);
3603 		if (err)
3604 			goto out;
3605 		break;
3606 	default:
3607 		goto out;
3608 	}
3609 
3610 	err = ptp_ocp_signal_set(bp, gen, &s);
3611 	if (err)
3612 		goto out;
3613 
3614 	err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3615 
3616 out:
3617 	argv_free(argv);
3618 	return err ? err : count;
3619 }
3620 
3621 static ssize_t
3622 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3623 {
3624 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3625 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3626 	struct ptp_ocp_signal *signal;
3627 	int gen = (uintptr_t)ea->var;
3628 	struct timespec64 ts;
3629 
3630 	signal = &bp->signal[gen];
3631 
3632 	ts = ktime_to_timespec64(signal->start);
3633 
3634 	return sysfs_emit(buf, "%llu %d %llu %d %ptT TAI\n",
3635 			  signal->period, signal->duty, signal->phase, signal->polarity,
3636 			  &ts.tv_sec);
3637 }
3638 static EXT_ATTR_RW(signal, signal, 0);
3639 static EXT_ATTR_RW(signal, signal, 1);
3640 static EXT_ATTR_RW(signal, signal, 2);
3641 static EXT_ATTR_RW(signal, signal, 3);
3642 
3643 static ssize_t
3644 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3645 {
3646 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3647 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3648 	int i = (uintptr_t)ea->var;
3649 
3650 	return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3651 }
3652 static EXT_ATTR_RO(signal, duty, 0);
3653 static EXT_ATTR_RO(signal, duty, 1);
3654 static EXT_ATTR_RO(signal, duty, 2);
3655 static EXT_ATTR_RO(signal, duty, 3);
3656 
3657 static ssize_t
3658 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3659 {
3660 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3661 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3662 	int i = (uintptr_t)ea->var;
3663 
3664 	return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3665 }
3666 static EXT_ATTR_RO(signal, period, 0);
3667 static EXT_ATTR_RO(signal, period, 1);
3668 static EXT_ATTR_RO(signal, period, 2);
3669 static EXT_ATTR_RO(signal, period, 3);
3670 
3671 static ssize_t
3672 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3673 {
3674 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3675 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3676 	int i = (uintptr_t)ea->var;
3677 
3678 	return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3679 }
3680 static EXT_ATTR_RO(signal, phase, 0);
3681 static EXT_ATTR_RO(signal, phase, 1);
3682 static EXT_ATTR_RO(signal, phase, 2);
3683 static EXT_ATTR_RO(signal, phase, 3);
3684 
3685 static ssize_t
3686 polarity_show(struct device *dev, struct device_attribute *attr,
3687 	      char *buf)
3688 {
3689 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3690 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3691 	int i = (uintptr_t)ea->var;
3692 
3693 	return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3694 }
3695 static EXT_ATTR_RO(signal, polarity, 0);
3696 static EXT_ATTR_RO(signal, polarity, 1);
3697 static EXT_ATTR_RO(signal, polarity, 2);
3698 static EXT_ATTR_RO(signal, polarity, 3);
3699 
3700 static ssize_t
3701 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3702 {
3703 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3704 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3705 	int i = (uintptr_t)ea->var;
3706 
3707 	return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3708 }
3709 static EXT_ATTR_RO(signal, running, 0);
3710 static EXT_ATTR_RO(signal, running, 1);
3711 static EXT_ATTR_RO(signal, running, 2);
3712 static EXT_ATTR_RO(signal, running, 3);
3713 
3714 static ssize_t
3715 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3716 {
3717 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3718 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3719 	int i = (uintptr_t)ea->var;
3720 	struct timespec64 ts;
3721 
3722 	ts = ktime_to_timespec64(bp->signal[i].start);
3723 	return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3724 }
3725 static EXT_ATTR_RO(signal, start, 0);
3726 static EXT_ATTR_RO(signal, start, 1);
3727 static EXT_ATTR_RO(signal, start, 2);
3728 static EXT_ATTR_RO(signal, start, 3);
3729 
3730 static ssize_t
3731 seconds_store(struct device *dev, struct device_attribute *attr,
3732 	      const char *buf, size_t count)
3733 {
3734 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3735 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3736 	int idx = (uintptr_t)ea->var;
3737 	u32 val;
3738 	int err;
3739 
3740 	err = kstrtou32(buf, 0, &val);
3741 	if (err)
3742 		return err;
3743 	if (val > 0xff)
3744 		return -EINVAL;
3745 
3746 	if (val)
3747 		val = (val << 8) | 0x1;
3748 
3749 	iowrite32(val, &bp->freq_in[idx]->ctrl);
3750 
3751 	return count;
3752 }
3753 
3754 static ssize_t
3755 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3756 {
3757 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3758 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3759 	int idx = (uintptr_t)ea->var;
3760 	u32 val;
3761 
3762 	val = ioread32(&bp->freq_in[idx]->ctrl);
3763 	if (val & 1)
3764 		val = (val >> 8) & 0xff;
3765 	else
3766 		val = 0;
3767 
3768 	return sysfs_emit(buf, "%u\n", val);
3769 }
3770 static EXT_ATTR_RW(freq, seconds, 0);
3771 static EXT_ATTR_RW(freq, seconds, 1);
3772 static EXT_ATTR_RW(freq, seconds, 2);
3773 static EXT_ATTR_RW(freq, seconds, 3);
3774 
3775 static ssize_t
3776 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3777 {
3778 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3779 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3780 	int idx = (uintptr_t)ea->var;
3781 	u32 val;
3782 
3783 	val = ioread32(&bp->freq_in[idx]->status);
3784 	if (val & FREQ_STATUS_ERROR)
3785 		return sysfs_emit(buf, "error\n");
3786 	if (val & FREQ_STATUS_OVERRUN)
3787 		return sysfs_emit(buf, "overrun\n");
3788 	if (val & FREQ_STATUS_VALID)
3789 		return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3790 	return 0;
3791 }
3792 static EXT_ATTR_RO(freq, frequency, 0);
3793 static EXT_ATTR_RO(freq, frequency, 1);
3794 static EXT_ATTR_RO(freq, frequency, 2);
3795 static EXT_ATTR_RO(freq, frequency, 3);
3796 
3797 static ssize_t
3798 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3799 {
3800 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3801 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3802 
3803 	/*
3804 	 * NOTE: This output does not include a trailing newline for backward
3805 	 * compatibility. Existing userspace software uses this value directly
3806 	 * as a device path (e.g., "/dev/ttyS4"), and adding a newline would
3807 	 * break those applications. Do not add a newline to this output.
3808 	 */
3809 	return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].uport->port.line);
3810 }
3811 
3812 static umode_t
3813 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3814 {
3815 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3816 	struct ptp_ocp_serial_port *port;
3817 	struct device_attribute *dattr;
3818 	struct dev_ext_attribute *ea;
3819 
3820 	if (strncmp(attr->name, "tty", 3))
3821 		return attr->mode;
3822 
3823 	dattr = container_of(attr, struct device_attribute, attr);
3824 	ea = container_of(dattr, struct dev_ext_attribute, attr);
3825 	port = &bp->port[(uintptr_t)ea->var];
3826 	return port->uport ? 0444 : 0;
3827 }
3828 
3829 #define EXT_TTY_ATTR_RO(_name, _val)			\
3830 	struct dev_ext_attribute dev_attr_tty##_name =	\
3831 		{ __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3832 
3833 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3834 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3835 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3836 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3837 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3838 	&dev_attr_ttyGNSS.attr.attr,
3839 	&dev_attr_ttyGNSS2.attr.attr,
3840 	&dev_attr_ttyMAC.attr.attr,
3841 	&dev_attr_ttyNMEA.attr.attr,
3842 	NULL,
3843 };
3844 
3845 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3846 	.name = "tty",
3847 	.attrs = ptp_ocp_timecard_tty_attrs,
3848 	.is_visible = ptp_ocp_timecard_tty_is_visible,
3849 };
3850 
3851 static ssize_t
3852 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3853 {
3854 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3855 
3856 	if (!bp->has_eeprom_data)
3857 		ptp_ocp_read_eeprom(bp);
3858 
3859 	return sysfs_emit(buf, "%pM\n", bp->serial);
3860 }
3861 static DEVICE_ATTR_RO(serialnum);
3862 
3863 static ssize_t
3864 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3865 {
3866 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3867 	ssize_t ret;
3868 
3869 	if (bp->gnss_lost)
3870 		ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3871 	else
3872 		ret = sysfs_emit(buf, "SYNC\n");
3873 
3874 	return ret;
3875 }
3876 static DEVICE_ATTR_RO(gnss_sync);
3877 
3878 static ssize_t
3879 utc_tai_offset_show(struct device *dev,
3880 		    struct device_attribute *attr, char *buf)
3881 {
3882 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3883 
3884 	return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3885 }
3886 
3887 static ssize_t
3888 utc_tai_offset_store(struct device *dev,
3889 		     struct device_attribute *attr,
3890 		     const char *buf, size_t count)
3891 {
3892 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3893 	int err;
3894 	u32 val;
3895 
3896 	err = kstrtou32(buf, 0, &val);
3897 	if (err)
3898 		return err;
3899 
3900 	ptp_ocp_utc_distribute(bp, val);
3901 
3902 	return count;
3903 }
3904 static DEVICE_ATTR_RW(utc_tai_offset);
3905 
3906 static ssize_t
3907 ts_window_adjust_show(struct device *dev,
3908 		      struct device_attribute *attr, char *buf)
3909 {
3910 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3911 
3912 	return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3913 }
3914 
3915 static ssize_t
3916 ts_window_adjust_store(struct device *dev,
3917 		       struct device_attribute *attr,
3918 		       const char *buf, size_t count)
3919 {
3920 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3921 	int err;
3922 	u32 val;
3923 
3924 	err = kstrtou32(buf, 0, &val);
3925 	if (err)
3926 		return err;
3927 
3928 	bp->ts_window_adjust = val;
3929 
3930 	return count;
3931 }
3932 static DEVICE_ATTR_RW(ts_window_adjust);
3933 
3934 static ssize_t
3935 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3936 {
3937 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3938 	u32 val;
3939 
3940 	val = ioread32(&bp->irig_out->ctrl);
3941 	val = (val >> 16) & 0x07;
3942 	return sysfs_emit(buf, "%d\n", val);
3943 }
3944 
3945 static ssize_t
3946 irig_b_mode_store(struct device *dev,
3947 		  struct device_attribute *attr,
3948 		  const char *buf, size_t count)
3949 {
3950 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3951 	unsigned long flags;
3952 	int err;
3953 	u32 reg;
3954 	u8 val;
3955 
3956 	err = kstrtou8(buf, 0, &val);
3957 	if (err)
3958 		return err;
3959 	if (val > 7)
3960 		return -EINVAL;
3961 
3962 	reg = ((val & 0x7) << 16);
3963 
3964 	spin_lock_irqsave(&bp->lock, flags);
3965 	iowrite32(0, &bp->irig_out->ctrl);		/* disable */
3966 	iowrite32(reg, &bp->irig_out->ctrl);		/* change mode */
3967 	iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3968 	spin_unlock_irqrestore(&bp->lock, flags);
3969 
3970 	return count;
3971 }
3972 static DEVICE_ATTR_RW(irig_b_mode);
3973 
3974 static ssize_t
3975 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3976 {
3977 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3978 	const char *p;
3979 	u32 select;
3980 
3981 	select = ioread32(&bp->reg->select);
3982 	p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3983 
3984 	return sysfs_emit(buf, "%s\n", p);
3985 }
3986 
3987 static ssize_t
3988 clock_source_store(struct device *dev, struct device_attribute *attr,
3989 		   const char *buf, size_t count)
3990 {
3991 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3992 	unsigned long flags;
3993 	int val;
3994 
3995 	val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3996 	if (val < 0)
3997 		return val;
3998 
3999 	spin_lock_irqsave(&bp->lock, flags);
4000 	iowrite32(val, &bp->reg->select);
4001 	spin_unlock_irqrestore(&bp->lock, flags);
4002 
4003 	return count;
4004 }
4005 static DEVICE_ATTR_RW(clock_source);
4006 
4007 static ssize_t
4008 available_clock_sources_show(struct device *dev,
4009 			     struct device_attribute *attr, char *buf)
4010 {
4011 	return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
4012 }
4013 static DEVICE_ATTR_RO(available_clock_sources);
4014 
4015 static ssize_t
4016 clock_status_drift_show(struct device *dev,
4017 			struct device_attribute *attr, char *buf)
4018 {
4019 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4020 	u32 val;
4021 	int res;
4022 
4023 	val = ioread32(&bp->reg->status_drift);
4024 	res = (val & ~INT_MAX) ? -1 : 1;
4025 	res *= (val & INT_MAX);
4026 	return sysfs_emit(buf, "%d\n", res);
4027 }
4028 static DEVICE_ATTR_RO(clock_status_drift);
4029 
4030 static ssize_t
4031 clock_status_offset_show(struct device *dev,
4032 			 struct device_attribute *attr, char *buf)
4033 {
4034 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4035 	u32 val;
4036 	int res;
4037 
4038 	val = ioread32(&bp->reg->status_offset);
4039 	res = (val & ~INT_MAX) ? -1 : 1;
4040 	res *= (val & INT_MAX);
4041 	return sysfs_emit(buf, "%d\n", res);
4042 }
4043 static DEVICE_ATTR_RO(clock_status_offset);
4044 
4045 static ssize_t
4046 tod_correction_show(struct device *dev,
4047 		    struct device_attribute *attr, char *buf)
4048 {
4049 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4050 	u32 val;
4051 	int res;
4052 
4053 	val = ioread32(&bp->tod->adj_sec);
4054 	res = (val & ~INT_MAX) ? -1 : 1;
4055 	res *= (val & INT_MAX);
4056 	return sysfs_emit(buf, "%d\n", res);
4057 }
4058 
4059 static ssize_t
4060 tod_correction_store(struct device *dev, struct device_attribute *attr,
4061 		     const char *buf, size_t count)
4062 {
4063 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4064 	unsigned long flags;
4065 	int err, res;
4066 	u32 val = 0;
4067 
4068 	err = kstrtos32(buf, 0, &res);
4069 	if (err)
4070 		return err;
4071 	if (res < 0) {
4072 		res *= -1;
4073 		val |= BIT(31);
4074 	}
4075 	val |= res;
4076 
4077 	spin_lock_irqsave(&bp->lock, flags);
4078 	iowrite32(val, &bp->tod->adj_sec);
4079 	spin_unlock_irqrestore(&bp->lock, flags);
4080 
4081 	return count;
4082 }
4083 static DEVICE_ATTR_RW(tod_correction);
4084 
4085 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr)					\
4086 	static struct attribute *fb_timecard_signal##_nr##_attrs[] = {	\
4087 		&dev_attr_signal##_nr##_signal.attr.attr,		\
4088 		&dev_attr_signal##_nr##_duty.attr.attr,			\
4089 		&dev_attr_signal##_nr##_phase.attr.attr,		\
4090 		&dev_attr_signal##_nr##_period.attr.attr,		\
4091 		&dev_attr_signal##_nr##_polarity.attr.attr,		\
4092 		&dev_attr_signal##_nr##_running.attr.attr,		\
4093 		&dev_attr_signal##_nr##_start.attr.attr,		\
4094 		NULL,							\
4095 	}
4096 
4097 #define DEVICE_SIGNAL_GROUP(_name, _nr)					\
4098 	_DEVICE_SIGNAL_GROUP_ATTRS(_nr);				\
4099 	static const struct attribute_group				\
4100 			fb_timecard_signal##_nr##_group = {		\
4101 		.name = #_name,						\
4102 		.attrs = fb_timecard_signal##_nr##_attrs,		\
4103 }
4104 
4105 DEVICE_SIGNAL_GROUP(gen1, 0);
4106 DEVICE_SIGNAL_GROUP(gen2, 1);
4107 DEVICE_SIGNAL_GROUP(gen3, 2);
4108 DEVICE_SIGNAL_GROUP(gen4, 3);
4109 
4110 #define _DEVICE_FREQ_GROUP_ATTRS(_nr)					\
4111 	static struct attribute *fb_timecard_freq##_nr##_attrs[] = {	\
4112 		&dev_attr_freq##_nr##_seconds.attr.attr,		\
4113 		&dev_attr_freq##_nr##_frequency.attr.attr,		\
4114 		NULL,							\
4115 	}
4116 
4117 #define DEVICE_FREQ_GROUP(_name, _nr)					\
4118 	_DEVICE_FREQ_GROUP_ATTRS(_nr);					\
4119 	static const struct attribute_group				\
4120 			fb_timecard_freq##_nr##_group = {		\
4121 		.name = #_name,						\
4122 		.attrs = fb_timecard_freq##_nr##_attrs,			\
4123 }
4124 
4125 DEVICE_FREQ_GROUP(freq1, 0);
4126 DEVICE_FREQ_GROUP(freq2, 1);
4127 DEVICE_FREQ_GROUP(freq3, 2);
4128 DEVICE_FREQ_GROUP(freq4, 3);
4129 
4130 static ssize_t
4131 disciplining_config_read(struct file *filp, struct kobject *kobj,
4132 			 const struct bin_attribute *bin_attr, char *buf,
4133 			 loff_t off, size_t count)
4134 {
4135 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4136 	size_t size = OCP_ART_CONFIG_SIZE;
4137 	struct nvmem_device *nvmem;
4138 	ssize_t err;
4139 
4140 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4141 	if (IS_ERR(nvmem))
4142 		return PTR_ERR(nvmem);
4143 
4144 	if (off > size) {
4145 		err = 0;
4146 		goto out;
4147 	}
4148 
4149 	if (off + count > size)
4150 		count = size - off;
4151 
4152 	// the configuration is in the very beginning of the EEPROM
4153 	err = nvmem_device_read(nvmem, off, count, buf);
4154 	if (err != count) {
4155 		err = -EFAULT;
4156 		goto out;
4157 	}
4158 
4159 out:
4160 	ptp_ocp_nvmem_device_put(&nvmem);
4161 
4162 	return err;
4163 }
4164 
4165 static ssize_t
4166 disciplining_config_write(struct file *filp, struct kobject *kobj,
4167 			  const struct bin_attribute *bin_attr, char *buf,
4168 			  loff_t off, size_t count)
4169 {
4170 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4171 	struct nvmem_device *nvmem;
4172 	ssize_t err;
4173 
4174 	/* Allow write of the whole area only */
4175 	if (off || count != OCP_ART_CONFIG_SIZE)
4176 		return -EFAULT;
4177 
4178 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4179 	if (IS_ERR(nvmem))
4180 		return PTR_ERR(nvmem);
4181 
4182 	err = nvmem_device_write(nvmem, 0x00, count, buf);
4183 	if (err != count)
4184 		err = -EFAULT;
4185 
4186 	ptp_ocp_nvmem_device_put(&nvmem);
4187 
4188 	return err;
4189 }
4190 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
4191 
4192 static ssize_t
4193 temperature_table_read(struct file *filp, struct kobject *kobj,
4194 		       const struct bin_attribute *bin_attr, char *buf,
4195 		       loff_t off, size_t count)
4196 {
4197 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4198 	size_t size = OCP_ART_TEMP_TABLE_SIZE;
4199 	struct nvmem_device *nvmem;
4200 	ssize_t err;
4201 
4202 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4203 	if (IS_ERR(nvmem))
4204 		return PTR_ERR(nvmem);
4205 
4206 	if (off > size) {
4207 		err = 0;
4208 		goto out;
4209 	}
4210 
4211 	if (off + count > size)
4212 		count = size - off;
4213 
4214 	// the configuration is in the very beginning of the EEPROM
4215 	err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
4216 	if (err != count) {
4217 		err = -EFAULT;
4218 		goto out;
4219 	}
4220 
4221 out:
4222 	ptp_ocp_nvmem_device_put(&nvmem);
4223 
4224 	return err;
4225 }
4226 
4227 static ssize_t
4228 temperature_table_write(struct file *filp, struct kobject *kobj,
4229 			const struct bin_attribute *bin_attr, char *buf,
4230 			loff_t off, size_t count)
4231 {
4232 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4233 	struct nvmem_device *nvmem;
4234 	ssize_t err;
4235 
4236 	/* Allow write of the whole area only */
4237 	if (off || count != OCP_ART_TEMP_TABLE_SIZE)
4238 		return -EFAULT;
4239 
4240 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4241 	if (IS_ERR(nvmem))
4242 		return PTR_ERR(nvmem);
4243 
4244 	err = nvmem_device_write(nvmem, 0x90, count, buf);
4245 	if (err != count)
4246 		err = -EFAULT;
4247 
4248 	ptp_ocp_nvmem_device_put(&nvmem);
4249 
4250 	return err;
4251 }
4252 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
4253 
4254 static struct attribute *fb_timecard_attrs[] = {
4255 	&dev_attr_serialnum.attr,
4256 	&dev_attr_gnss_sync.attr,
4257 	&dev_attr_clock_source.attr,
4258 	&dev_attr_available_clock_sources.attr,
4259 	&dev_attr_sma1.attr,
4260 	&dev_attr_sma2.attr,
4261 	&dev_attr_sma3.attr,
4262 	&dev_attr_sma4.attr,
4263 	&dev_attr_available_sma_inputs.attr,
4264 	&dev_attr_available_sma_outputs.attr,
4265 	&dev_attr_clock_status_drift.attr,
4266 	&dev_attr_clock_status_offset.attr,
4267 	&dev_attr_irig_b_mode.attr,
4268 	&dev_attr_utc_tai_offset.attr,
4269 	&dev_attr_ts_window_adjust.attr,
4270 	&dev_attr_tod_correction.attr,
4271 	NULL,
4272 };
4273 
4274 static const struct attribute_group fb_timecard_group = {
4275 	.attrs = fb_timecard_attrs,
4276 };
4277 
4278 static const struct ocp_attr_group fb_timecard_groups[] = {
4279 	{ .cap = OCP_CAP_BASIC,	    .group = &fb_timecard_group },
4280 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
4281 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
4282 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
4283 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
4284 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
4285 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
4286 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
4287 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
4288 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
4289 	{ },
4290 };
4291 
4292 static struct attribute *art_timecard_attrs[] = {
4293 	&dev_attr_serialnum.attr,
4294 	&dev_attr_clock_source.attr,
4295 	&dev_attr_available_clock_sources.attr,
4296 	&dev_attr_utc_tai_offset.attr,
4297 	&dev_attr_ts_window_adjust.attr,
4298 	&dev_attr_sma1.attr,
4299 	&dev_attr_sma2.attr,
4300 	&dev_attr_sma3.attr,
4301 	&dev_attr_sma4.attr,
4302 	&dev_attr_available_sma_inputs.attr,
4303 	&dev_attr_available_sma_outputs.attr,
4304 	NULL,
4305 };
4306 
4307 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
4308 	&bin_attr_disciplining_config,
4309 	&bin_attr_temperature_table,
4310 	NULL,
4311 };
4312 
4313 static const struct attribute_group art_timecard_group = {
4314 	.attrs = art_timecard_attrs,
4315 	.bin_attrs = bin_art_timecard_attrs,
4316 };
4317 
4318 static const struct ocp_attr_group art_timecard_groups[] = {
4319 	{ .cap = OCP_CAP_BASIC,	    .group = &art_timecard_group },
4320 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
4321 	{ },
4322 };
4323 
4324 /*
4325  * adva_x1 TAP CPLD (Lattice LCMXO3LF-2100) helpers.
4326  *
4327  * The card has two I2C controllers; Linux registers only 0x00150000.
4328  * The i2c_bus_ctrl handshake re-routes what each is wired to:
4329  *
4330  *   grant 0:  0x150000 -> EEPROMs     0x120000 -> TMC or M.2, MB's choice
4331  *   grant 1:  0x150000 -> TMC bus     0x120000 -> M.2
4332  *
4333  * The PCA9548 at 0x74 and the CPLD at 0x40 behind its channel 0 are on the
4334  * TMC bus, reachable only while the grant is held.  The EEPROMs are not
4335  * behind the adapter for that window, so a CPLD operation holds cpld_lock
4336  * and the adapter lock to keep the EEPROM and nvmem paths off it.
4337  */
4338 
4339 #define ADVA_MUX_ADDR     0x74
4340 #define ADVA_CPLD_ADDR    0x40
4341 #define ADVA_MUX_CHANNEL  0
4342 
4343 /* Longest command or reply; bounds each half of the per-claim scratch. */
4344 #define ADVA_CPLD_XFER_MAX 32
4345 
4346 /* i2c_bus_ctrl carries a host-written request half and a firmware-written
4347  * grant half.  MBLAZE_GRANTED is what a granted register reads while our
4348  * request still stands; the release write clears the request half, so from
4349  * then on only the grant field can be tested.  Measured on an ADVA
4350  * TimeCard X1: the register reads 0x00000012 once the firmware has handed
4351  * the segment back, about 670 ms after the release write, so the low half
4352  * is not zero then and only the grant field is a valid test.
4353  */
4354 #define MBLAZE_REQUEST    0x0000aaaaU
4355 #define MBLAZE_GRANTED    0x5555aaaaU
4356 #define MBLAZE_RELEASE    0x55550000U
4357 #define MBLAZE_GRANT_MASK 0xffff0000U
4358 #define MBLAZE_GRANT      0x55550000U
4359 #define MBLAZE_RETRIES    200
4360 #define MBLAZE_RETRY_US   10000
4361 
4362 /* Lattice LCMXO3LF ISC command codes */
4363 #define CPLD_CMD_READ_ID      0xE0000000UL
4364 /* The USERCODE lives in the configuration flash that ERASE wipes, and the
4365  * page writes carry it: after programming an image whose JEDEC UH field is
4366  * 0x00000004 the part reads back 0x00000004, not an erased value.  So there
4367  * is no separate ISC_PROGRAM_USERCODE step here.
4368  */
4369 #define CPLD_CMD_READ_USERCODE 0xC0000000UL
4370 #define CPLD_CMD_READ_STATUS  0x3C000000UL
4371 #define CPLD_CMD_EN_CFG_TP    0x74   /* enable config, transparent mode */
4372 #define CPLD_CMD_DIS_CFG      0x26
4373 #define CPLD_CMD_ERASE        0x0E
4374 #define CPLD_CMD_RESET_ADDR   0x46
4375 #define CPLD_CMD_WRITE_PAGE   0x70
4376 #define CPLD_CMD_SET_DONE     0x5E
4377 #define CPLD_CMD_REFRESH      0x79
4378 #define CPLD_PAGE_SIZE        16
4379 #define CPLD_POLL_US          10000  /* status poll interval while busy */
4380 /* Bounds how long a claim can hold the i2c root lock, not image validity:
4381  * far above any bitstream this part takes.
4382  */
4383 #define CPLD_MAX_IMAGE_SZ     (256 * 1024)
4384 #define CPLD_EXIT_CFG_TRIES   3
4385 #define CPLD_ERASE_MS         15000  /* config sector erase, datasheet max */
4386 #define CPLD_ID_MAX_ATTEMPTS  10     /* one per sync_work tick */
4387 
4388 /* Status register bit positions (Lattice LCMXO3LF datasheet) */
4389 #define CPLD_STATUS_DONE   BIT(8)
4390 #define CPLD_STATUS_ENAB   BIT(9)
4391 #define CPLD_STATUS_BUSY   BIT(12)
4392 #define CPLD_STATUS_FAILED BIT(13)
4393 #define CPLD_STATUS_ERR    GENMASK(25, 23)
4394 
4395 /*
4396  * Issue one I2C transaction on the TMC bus: @cmd if not negative, then
4397  * @wlen bytes of @wdata (NULL sends zeros), then @rlen bytes read back.
4398  * The message is built in the scratch buffer from adva_x1_bus_claim(), so
4399  * a run of transfers costs one allocation, not one each.  I2C_M_DMA_SAFE
4400  * is not set: the two halves are not separately aligned, so let the core
4401  * bounce.  Caller holds the claim, hence __i2c_transfer().
4402  */
4403 static int adva_x1_i2c_xfer(struct ptp_ocp *bp, u8 addr, int cmd,
4404 			    const void *wdata, u8 wlen,
4405 			    void *rdata, u8 rlen)
4406 {
4407 	u8 *wbuf, *rbuf;
4408 	struct i2c_adapter *adap;
4409 	struct i2c_msg msgs[2];
4410 	int nmsgs = 0, ret;
4411 	u16 hdr = cmd >= 0;
4412 
4413 	lockdep_assert_held(&bp->cpld_lock);
4414 
4415 	adap = bp->cpld_adap;
4416 	if (!adap || !bp->cpld_buf)
4417 		return -ENODEV;
4418 
4419 	if (hdr + wlen > ADVA_CPLD_XFER_MAX || rlen > ADVA_CPLD_XFER_MAX)
4420 		return -EINVAL;
4421 
4422 	wbuf = bp->cpld_buf;
4423 	rbuf = bp->cpld_buf + ADVA_CPLD_XFER_MAX;
4424 
4425 	if (hdr + wlen) {
4426 		if (hdr)
4427 			wbuf[0] = cmd;
4428 		if (wdata)
4429 			memcpy(wbuf + hdr, wdata, wlen);
4430 		else
4431 			memset(wbuf + hdr, 0, wlen);
4432 		msgs[nmsgs++] = (struct i2c_msg){
4433 			.addr  = addr,
4434 			.flags = 0,
4435 			.len   = hdr + wlen,
4436 			.buf   = wbuf,
4437 		};
4438 	}
4439 	if (rlen) {
4440 		msgs[nmsgs++] = (struct i2c_msg){
4441 			.addr  = addr,
4442 			.flags = I2C_M_RD,
4443 			.len   = rlen,
4444 			.buf   = rbuf,
4445 		};
4446 	}
4447 
4448 	ret = __i2c_transfer(adap, msgs, nmsgs);
4449 	if (ret != nmsgs)
4450 		return (ret < 0) ? ret : -EIO;
4451 
4452 	if (rdata && rlen)
4453 		memcpy(rdata, rbuf, rlen);
4454 
4455 	return 0;
4456 }
4457 
4458 /* Hand the segment back, and wait for the firmware to drop the grant before
4459  * the caller unlocks the adapter: a transfer queued behind us would
4460  * otherwise be clocked out while the controller is still on the TMC bus,
4461  * which is what holding the adapter lock across the grant exists to stop.
4462  */
4463 static int adva_x1_mblaze_release(struct ptp_ocp *bp)
4464 {
4465 	u32 val = 0;
4466 	int i;
4467 
4468 	if (!bp->pps_select)
4469 		return 0;
4470 
4471 	iowrite32(MBLAZE_RELEASE, &bp->pps_select->i2c_bus_ctrl);
4472 	/* Flush the posted write, as the acquire path does. */
4473 	ioread32(&bp->pps_select->i2c_bus_ctrl);
4474 
4475 	for (i = 0; i < MBLAZE_RETRIES; i++) {
4476 		val = ioread32(&bp->pps_select->i2c_bus_ctrl);
4477 		if ((val & MBLAZE_GRANT_MASK) != MBLAZE_GRANT)
4478 			return 0;
4479 		usleep_range(MBLAZE_RETRY_US, MBLAZE_RETRY_US + 1000);
4480 	}
4481 
4482 	dev_err(&bp->pdev->dev,
4483 		"TMC bus still granted after release, i2c_bus_ctrl 0x%08x\n",
4484 		val);
4485 
4486 	return -ETIMEDOUT;
4487 }
4488 
4489 /* Acquire the shared I2C bus from the MicroBlaze firmware.  Returns with no
4490  * request outstanding on failure, so the firmware is never left granting a
4491  * segment to a host that has given up waiting for it.
4492  */
4493 static int adva_x1_mblaze_acquire(struct ptp_ocp *bp)
4494 {
4495 	u32 val;
4496 	int i;
4497 
4498 	if (!bp->pps_select)
4499 		return -ENODEV;
4500 
4501 	/* Drop a request left by a caller that died mid-sequence; cpld_lock
4502 	 * keeps live ones out.  The read back only flushes the posted write.
4503 	 */
4504 	iowrite32(0, &bp->pps_select->i2c_bus_ctrl);
4505 	ioread32(&bp->pps_select->i2c_bus_ctrl);
4506 
4507 	iowrite32(MBLAZE_REQUEST, &bp->pps_select->i2c_bus_ctrl);
4508 	for (i = 0; i < MBLAZE_RETRIES; i++) {
4509 		usleep_range(MBLAZE_RETRY_US, MBLAZE_RETRY_US + 1000);
4510 		val = ioread32(&bp->pps_select->i2c_bus_ctrl);
4511 		if (val == MBLAZE_GRANTED)
4512 			return 0;
4513 	}
4514 
4515 	/* Drop the request we gave up on.  Any error from the hand-back is
4516 	 * subsumed by the -ETIMEDOUT we are already returning.
4517 	 */
4518 	adva_x1_mblaze_release(bp);
4519 	return -ETIMEDOUT;
4520 }
4521 
4522 /* Route the host controller back to the EEPROMs and release the adapter.
4523  * Safe after a failed claim: it also clears a request that was never granted.
4524  *
4525  * The adapter is unlocked even when the hand-back timed out: keeping the
4526  * root lock would stall every other user of the controller for good, with
4527  * no way to recover it.  The error is returned instead, so the operation
4528  * that held the claim fails rather than reporting success over a bus that
4529  * may still be routed to the TMC segment.
4530  */
4531 static int adva_x1_bus_release(struct ptp_ocp *bp)
4532 {
4533 	struct i2c_adapter *adap = bp->cpld_adap;
4534 	int err;
4535 
4536 	if (!adap)
4537 		return 0;
4538 
4539 	err = adva_x1_mblaze_release(bp);
4540 	bp->cpld_adap = NULL;
4541 	kfree(bp->cpld_buf);
4542 	bp->cpld_buf = NULL;
4543 	i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
4544 	i2c_put_adapter(adap);
4545 
4546 	return err;
4547 }
4548 
4549 static int adva_x1_i2c_adap_match(struct device *dev, const void *data)
4550 {
4551 	return !!i2c_verify_adapter(dev);
4552 }
4553 
4554 /*
4555  * Cache the adapter the CPLD hangs off.  ptp_ocp_i2c_notifier_call() misses
4556  * it when the i2c controller driver is already loaded: the adapter is then
4557  * added from inside platform_device_register(), before bp->i2c_ctrl is set.
4558  * Only direct children are searched, so a mux adapter cannot match.
4559  *
4560  * Called from the worker rather than once from probe: device_add() notifies
4561  * before it links the device to its parent, so with asynchronous probing
4562  * both the notifier and a single lookup here can miss the same adapter.
4563  * Retrying costs a short klist walk per tick until one of them succeeds.
4564  */
4565 static void adva_x1_cache_i2c_adap(struct ptp_ocp *bp)
4566 {
4567 	struct device *child;
4568 
4569 	if (!bp->has_cpld || !bp->i2c_ctrl ||
4570 	    READ_ONCE(bp->cpld_i2c_adap_nr) >= 0)
4571 		return;
4572 
4573 	child = device_find_child(&bp->i2c_ctrl->dev, NULL,
4574 				  adva_x1_i2c_adap_match);
4575 	if (!child)
4576 		return;
4577 
4578 	/* Re-test under the lock so this does not overwrite a number the
4579 	 * notifier published meanwhile.  It cannot tell that apart from a
4580 	 * number the notifier has just invalidated, so an adapter removed in
4581 	 * this window can still be cached; adva_x1_bus_claim() rejects it on
4582 	 * the parent check and forgets it, and the next tick looks again.
4583 	 */
4584 	scoped_guard(spinlock, &bp->cpld_adap_lock) {
4585 		if (bp->cpld_i2c_adap_nr < 0)
4586 			bp->cpld_i2c_adap_nr = i2c_verify_adapter(child)->nr;
4587 	}
4588 
4589 	put_device(child);
4590 }
4591 
4592 /*
4593  * Claim the TMC bus.  The adapter lock is held across the handshake to keep
4594  * the EEPROM, nvmem and at24 paths off the controller while it is routed
4595  * away from the EEPROMs; an EEPROM read blocks until the claim is dropped.
4596  */
4597 static int adva_x1_bus_claim(struct ptp_ocp *bp)
4598 {
4599 	struct i2c_adapter *adap;
4600 	int ret;
4601 
4602 	lockdep_assert_held(&bp->cpld_lock);
4603 
4604 	adap = i2c_get_adapter(READ_ONCE(bp->cpld_i2c_adap_nr));
4605 	if (!adap)
4606 		return -ENODEV;
4607 
4608 	/* The number is freed before the notifier clears it, so it can
4609 	 * already be another adapter's.  Check this is still ours, and drop
4610 	 * a number that is not: otherwise every later claim fails the same
4611 	 * way, where forgetting it lets the worker look the adapter up again.
4612 	 */
4613 	if (!bp->i2c_ctrl || adap->dev.parent != &bp->i2c_ctrl->dev) {
4614 		scoped_guard(spinlock, &bp->cpld_adap_lock) {
4615 			if (bp->cpld_i2c_adap_nr == adap->nr)
4616 				bp->cpld_i2c_adap_nr = -1;
4617 		}
4618 		i2c_put_adapter(adap);
4619 		return -ENODEV;
4620 	}
4621 
4622 	/* One scratch buffer per claim rather than per transfer: a claim can
4623 	 * cover many transfers.
4624 	 */
4625 	bp->cpld_buf = kzalloc(2 * ADVA_CPLD_XFER_MAX, GFP_KERNEL);
4626 	if (!bp->cpld_buf) {
4627 		i2c_put_adapter(adap);
4628 		return -ENOMEM;
4629 	}
4630 
4631 	i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
4632 	bp->cpld_adap = adap;
4633 
4634 	ret = adva_x1_mblaze_acquire(bp);
4635 	if (ret)
4636 		adva_x1_bus_release(bp);	/* keeps the acquire error */
4637 
4638 	return ret;
4639 }
4640 
4641 /* Select a mux channel, or deselect all with ch < 0 - the power-on state.
4642  * The mux is on the TMC bus, so what it is left set to never affects the
4643  * EEPROM paths.
4644  */
4645 static int adva_x1_mux_select(struct ptp_ocp *bp, int ch)
4646 {
4647 	u8 val = (ch >= 0) ? BIT(ch) : 0;
4648 
4649 	return adva_x1_i2c_xfer(bp, ADVA_MUX_ADDR, val, NULL, 0, NULL, 0);
4650 }
4651 
4652 /*
4653  * Argument bytes that follow an ISC opcode.  Returns NULL with @nargs set
4654  * when the arguments are all zero: adva_x1_i2c_xfer() zeroes the buffer.
4655  *
4656  * EN_CFG_TP, DIS_CFG and REFRESH take two operand bytes here where the SPI
4657  * drivers in drivers/fpga send three.  These are the frames the part on this
4658  * board answers: the sequence below has programmed and refreshed it
4659  * successfully over I2C, so the counts are kept as validated rather than
4660  * aligned with the SPI framing.
4661  */
4662 static const u8 *adva_x1_cpld_args(u8 cmd, u8 *nargs)
4663 {
4664 	static const u8 en_cfg_tp[] = { 0x08, 0x00 };
4665 	/* cfg sector only */
4666 	static const u8 erase_cfg[] = { 0x04, 0x00, 0x00 };
4667 
4668 	switch (cmd) {
4669 	case CPLD_CMD_EN_CFG_TP:
4670 		*nargs = sizeof(en_cfg_tp);
4671 		return en_cfg_tp;
4672 	case CPLD_CMD_ERASE:
4673 		*nargs = sizeof(erase_cfg);
4674 		return erase_cfg;
4675 	case CPLD_CMD_RESET_ADDR:
4676 	case CPLD_CMD_SET_DONE:
4677 		*nargs = 3;
4678 		return NULL;
4679 	case CPLD_CMD_DIS_CFG:
4680 	case CPLD_CMD_REFRESH:
4681 		*nargs = 2;
4682 		return NULL;
4683 	default:
4684 		*nargs = 0;
4685 		return NULL;
4686 	}
4687 }
4688 
4689 /* Send an ISC command with the fixed arguments that belong to it. */
4690 static int adva_x1_cpld_write(struct ptp_ocp *bp, u8 cmd)
4691 {
4692 	const u8 *args;
4693 	u8 nargs;
4694 
4695 	args = adva_x1_cpld_args(cmd, &nargs);
4696 
4697 	return adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, cmd, args, nargs, NULL, 0);
4698 }
4699 
4700 /*
4701  * Send a 4-byte command and read back without an intermediate STOP: two
4702  * messages in one transfer is the Lattice write -> repeated START -> read,
4703  * so no protocol-mangling flag is needed.
4704  */
4705 static int adva_x1_cpld_cmd_read(struct ptp_ocp *bp,
4706 				 u32 cmd_be, u8 *out, u8 out_len)
4707 {
4708 	__be32 cmd = cpu_to_be32(cmd_be);
4709 
4710 	return adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, -1, &cmd, 4, out, out_len);
4711 }
4712 
4713 static int adva_x1_cpld_read_status(struct ptp_ocp *bp, u32 *status)
4714 {
4715 	u8 buf[4];
4716 	int ret;
4717 
4718 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_STATUS, buf, 4);
4719 	if (ret)
4720 		return ret;
4721 	*status = get_unaligned_be32(buf);
4722 	return 0;
4723 }
4724 
4725 /* Poll the status register until the CPLD goes idle, or @max_ms elapses.
4726  * The deadline is on wall time, so the I2C transactions count against it,
4727  * and the status is read once more after it expires before giving up.
4728  */
4729 static int adva_x1_cpld_wait_ready(struct ptp_ocp *bp, unsigned int max_ms)
4730 {
4731 	u32 status = 0;
4732 	int err = 0, ret;
4733 
4734 	ret = read_poll_timeout(adva_x1_cpld_read_status, err,
4735 				err || (status & CPLD_STATUS_FAILED) ||
4736 				!(status & CPLD_STATUS_BUSY),
4737 				CPLD_POLL_US, max_ms * USEC_PER_MSEC, false,
4738 				bp, &status);
4739 	if (ret)
4740 		return ret;
4741 	/* Keep the transport errno so it reaches userspace as-is; -EIO is
4742 	 * reserved for the CPLD itself reporting FAILED.
4743 	 */
4744 	if (err)
4745 		return err;
4746 	if (status & CPLD_STATUS_FAILED)
4747 		return -EIO;
4748 
4749 	return 0;
4750 }
4751 
4752 /* Wait for BUSY to clear.  Unlike adva_x1_cpld_wait_ready() a latched FAILED
4753  * status is not an error here: this is used on the exit path, where an ISC
4754  * command issued while the part is still erasing or programming may not
4755  * latch, so the operation has to be waited out whatever its outcome.
4756  */
4757 static int adva_x1_cpld_wait_idle(struct ptp_ocp *bp, unsigned int max_ms)
4758 {
4759 	u32 status = 0;
4760 	int err = 0, ret;
4761 
4762 	ret = read_poll_timeout(adva_x1_cpld_read_status, err,
4763 				err || !(status & CPLD_STATUS_BUSY),
4764 				CPLD_POLL_US, max_ms * USEC_PER_MSEC, false,
4765 				bp, &status);
4766 	if (ret)
4767 		return ret;
4768 
4769 	return err;
4770 }
4771 
4772 /* Leave transparent configuration mode.
4773  *
4774  * A DIS_CFG issued while the part is still busy may not latch, so the wait
4775  * has to succeed before the write is believed - an ACKed write after a
4776  * timed-out wait says nothing about whether the part left the mode.  Retry
4777  * a few times rather than leaving it latched on one bad attempt; there is
4778  * no other caller that would try again.
4779  */
4780 static void adva_x1_cpld_exit_config(struct ptp_ocp *bp)
4781 {
4782 	int err, i;
4783 
4784 	if (!bp->cpld_in_config_mode)
4785 		return;
4786 
4787 	for (i = 0; i < CPLD_EXIT_CFG_TRIES; i++) {
4788 		err = adva_x1_cpld_wait_idle(bp, CPLD_ERASE_MS);
4789 		if (!err)
4790 			err = adva_x1_cpld_write(bp, CPLD_CMD_DIS_CFG);
4791 		if (!err) {
4792 			bp->cpld_in_config_mode = false;
4793 			return;
4794 		}
4795 	}
4796 
4797 	dev_err(&bp->pdev->dev, "CPLD left in configuration mode: %d\n", err);
4798 }
4799 
4800 /*
4801  * Read the Lattice device ID and the image USERCODE under one bus claim.
4802  * Done once, off the unprivileged devlink path, which reports the cached
4803  * values.  -EBUSY means cpld_lock is held, so the caller can retry rather
4804  * than wait behind a long CPLD operation.
4805  */
4806 static int adva_x1_cpld_read_id(struct ptp_ocp *bp)
4807 {
4808 	u8 data[4];
4809 	int err, ret;
4810 
4811 	if (!mutex_trylock(&bp->cpld_lock))
4812 		return -EBUSY;
4813 
4814 	ret = adva_x1_bus_claim(bp);
4815 	if (ret)
4816 		goto out;
4817 	/* A select reported as failed may still have been ACKed, so the
4818 	 * deselect runs either way rather than handing the mux back with a
4819 	 * channel possibly left open.
4820 	 */
4821 	ret = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4822 	if (ret)
4823 		goto deselect;
4824 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_ID, data, 4);
4825 	if (ret)
4826 		goto deselect;
4827 	/* Publish the ID before the USERCODE is attempted: a part that does
4828 	 * not answer 0xC0 must not cost us the device ID as well.
4829 	 */
4830 	WRITE_ONCE(bp->cpld_id, get_unaligned_be32(data));
4831 
4832 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_USERCODE, data, 4);
4833 	if (ret)
4834 		goto deselect;
4835 	WRITE_ONCE(bp->cpld_usercode, get_unaligned_be32(data));
4836 	/* Pairs with the acquire in ptp_ocp_devlink_info_get(): the value has
4837 	 * to be visible before the flag that declares it valid.
4838 	 */
4839 	smp_store_release(&bp->cpld_usercode_ok, true);
4840 deselect:
4841 	err = adva_x1_mux_select(bp, -1);
4842 	if (!ret)
4843 		ret = err;
4844 	err = adva_x1_bus_release(bp);
4845 	if (!ret)
4846 		ret = err;
4847 out:
4848 	/* Under cpld_lock, so an operation that resets this bookkeeping
4849 	 * while holding the lock cannot have it overwritten afterwards by a
4850 	 * worker that had already finished reading.
4851 	 */
4852 	if (!ret || ++bp->cpld_id_attempts >= CPLD_ID_MAX_ATTEMPTS)
4853 		bp->cpld_id_tried = true;
4854 	mutex_unlock(&bp->cpld_lock);
4855 	if (ret)
4856 		dev_dbg(&bp->pdev->dev,
4857 			"CPLD device ID unavailable: %d\n", ret);
4858 
4859 	return ret;
4860 }
4861 
4862 /* cpld_status - show the flags set in the TAP CPLD status register. */
4863 static ssize_t
4864 cpld_status_show(struct device *dev, struct device_attribute *attr,
4865 		 char *buf)
4866 {
4867 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4868 	int count = 0;
4869 	u32 st = 0;
4870 	int err, ret;
4871 
4872 	/* A CPLD operation can hold cpld_lock a long time; stay killable. */
4873 	ret = mutex_lock_interruptible(&bp->cpld_lock);
4874 	if (ret)
4875 		return ret;
4876 
4877 	ret = adva_x1_bus_claim(bp);
4878 	if (ret)
4879 		goto out;
4880 	ret = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4881 	if (ret)
4882 		goto deselect;
4883 	ret = adva_x1_cpld_read_status(bp, &st);
4884 deselect:
4885 	err = adva_x1_mux_select(bp, -1);
4886 	if (!ret)
4887 		ret = err;
4888 	err = adva_x1_bus_release(bp);
4889 	if (!ret)
4890 		ret = err;
4891 out:
4892 	mutex_unlock(&bp->cpld_lock);
4893 	if (ret)
4894 		return ret;
4895 
4896 	/* Flags: the names of the bits that are set, nothing when none is,
4897 	 * rather than a value per bit in one file.
4898 	 */
4899 	if (st & CPLD_STATUS_DONE)
4900 		count += sysfs_emit_at(buf, count, "done");
4901 	if (st & CPLD_STATUS_BUSY)
4902 		count += sysfs_emit_at(buf, count, "%sbusy", count ? " " : "");
4903 	if (st & CPLD_STATUS_FAILED)
4904 		count += sysfs_emit_at(buf, count, "%sfailed",
4905 				       count ? " " : "");
4906 
4907 	return count + sysfs_emit_at(buf, count, "\n");
4908 }
4909 static DEVICE_ATTR_ADMIN_RO(cpld_status);
4910 
4911 /*
4912  * Program the CPLD configuration flash from @fw and activate it.  Selected
4913  * by the "fw.cpld" flash component; the SPI flash keeps the default path.
4914  * Runs under cpld_lock with the i2c adapter lock held, so an EEPROM read
4915  * blocks for as long as programming takes.
4916  */
4917 static int adva_x1_cpld_flash(struct ptp_ocp *bp, struct devlink *devlink,
4918 			      const struct firmware *fw,
4919 			      struct netlink_ext_ack *extack)
4920 {
4921 	size_t offset;
4922 	int err, ret;
4923 	u32 st;
4924 
4925 	if (!fw->size || fw->size % CPLD_PAGE_SIZE) {
4926 		NL_SET_ERR_MSG_MOD(extack,
4927 				   "image must be a whole number of 16-byte pages");
4928 		return -EINVAL;
4929 	}
4930 	if (fw->size > CPLD_MAX_IMAGE_SZ) {
4931 		NL_SET_ERR_MSG_MOD(extack, "image too large for this part");
4932 		return -EINVAL;
4933 	}
4934 
4935 	mutex_lock(&bp->cpld_lock);
4936 
4937 	err = adva_x1_bus_claim(bp);
4938 	if (err)
4939 		goto unlock;
4940 	/* A select reported as failed may still have been ACKed, so hand the
4941 	 * mux back deselected either way.
4942 	 */
4943 	err = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4944 	if (err)
4945 		goto deselect;
4946 
4947 	/* A previous flash may have failed to leave configuration mode.  Now
4948 	 * that the bus is claimed again, retry the exit before re-entering;
4949 	 * a no-op when the flag is already clear.
4950 	 */
4951 	adva_x1_cpld_exit_config(bp);
4952 
4953 	/* Set before EN_CFG_TP, not after: the CPLD may have entered config
4954 	 * mode even if the write errors or the wait times out, and only this
4955 	 * makes the exit path send DIS_CFG.  A stray DIS_CFG is harmless;
4956 	 * leaving config mode enabled is not.
4957 	 */
4958 	bp->cpld_in_config_mode = true;
4959 
4960 	err = adva_x1_cpld_write(bp, CPLD_CMD_EN_CFG_TP);
4961 	if (!err)
4962 		err = adva_x1_cpld_wait_ready(bp, 5000);
4963 	if (err)
4964 		goto exit_config;
4965 
4966 	/* Confirm the part really entered configuration mode.  An enable
4967 	 * frame that did not latch leaves an idle part reporting neither
4968 	 * BUSY nor FAILED, the erase and page writes are ignored, and DONE
4969 	 * is still set from the old image - so every later check passes and
4970 	 * the update would be reported successful with the flash untouched.
4971 	 */
4972 	err = adva_x1_cpld_read_status(bp, &st);
4973 	if (err)
4974 		goto exit_config;
4975 	if (!(st & CPLD_STATUS_ENAB)) {
4976 		dev_err(&bp->pdev->dev,
4977 			"CPLD did not enter configuration mode, status 0x%08x\n",
4978 			st);
4979 		NL_SET_ERR_MSG_MOD(extack,
4980 				   "CPLD did not enter configuration mode");
4981 		err = -EIO;
4982 		goto exit_config;
4983 	}
4984 
4985 	devlink_flash_update_status_notify(devlink, "Erasing",
4986 					   ADVA_CPLD_COMPONENT, 0, 0);
4987 	err = adva_x1_cpld_write(bp, CPLD_CMD_ERASE);
4988 	if (!err)
4989 		err = adva_x1_cpld_wait_ready(bp, CPLD_ERASE_MS);
4990 	if (err)
4991 		goto exit_config;
4992 
4993 	/* The old image is gone from here on, so stop reporting its
4994 	 * identity even if the rest of the sequence fails.  Written under
4995 	 * cpld_lock, which adva_x1_cpld_read_id() also holds across its own
4996 	 * bookkeeping, so the worker cannot resurrect any of it.
4997 	 */
4998 	WRITE_ONCE(bp->cpld_id, 0);
4999 	WRITE_ONCE(bp->cpld_usercode_ok, false);
5000 	bp->cpld_id_tried = false;
5001 	bp->cpld_id_attempts = 0;
5002 
5003 	err = adva_x1_cpld_write(bp, CPLD_CMD_RESET_ADDR);
5004 	if (err)
5005 		goto exit_config;
5006 
5007 	for (offset = 0; offset < fw->size; offset += CPLD_PAGE_SIZE) {
5008 		u8 args[3 + CPLD_PAGE_SIZE] = { 0x00, 0x00, 0x01 };
5009 
5010 		/* The loop holds cpld_lock and the i2c root lock for the
5011 		 * whole image, so give a dying task a way out.  The part is
5012 		 * left unconfigured, which is recoverable: fw.cpld stays
5013 		 * advertised so the image can be written again.
5014 		 */
5015 		if (fatal_signal_pending(current)) {
5016 			err = -EINTR;
5017 			goto exit_config;
5018 		}
5019 
5020 		memcpy(&args[3], fw->data + offset, CPLD_PAGE_SIZE);
5021 		err = adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, CPLD_CMD_WRITE_PAGE,
5022 				       args, sizeof(args), NULL, 0);
5023 		if (!err)
5024 			err = adva_x1_cpld_wait_ready(bp, 100);
5025 		if (err)
5026 			goto exit_config;
5027 
5028 		if (!(offset % (CPLD_PAGE_SIZE * 64)))
5029 			devlink_flash_update_status_notify(devlink,
5030 							   "Programming",
5031 							   ADVA_CPLD_COMPONENT,
5032 							   offset, fw->size);
5033 	}
5034 	devlink_flash_update_status_notify(devlink, "Programming",
5035 					   ADVA_CPLD_COMPONENT,
5036 					   fw->size, fw->size);
5037 
5038 	err = adva_x1_cpld_write(bp, CPLD_CMD_SET_DONE);
5039 	if (!err)
5040 		err = adva_x1_cpld_wait_ready(bp, 1000);
5041 	if (err)
5042 		goto exit_config;
5043 
5044 	err = adva_x1_cpld_read_status(bp, &st);
5045 	if (err)
5046 		goto exit_config;
5047 	if (!(st & CPLD_STATUS_DONE)) {
5048 		dev_err(&bp->pdev->dev,
5049 			"CPLD SET_DONE left status 0x%08x\n", st);
5050 		NL_SET_ERR_MSG_MOD(extack, "CPLD did not accept the image");
5051 		err = -EIO;
5052 		goto exit_config;
5053 	}
5054 
5055 	devlink_flash_update_status_notify(devlink, "Activating",
5056 					   ADVA_CPLD_COMPONENT, 0, 0);
5057 	err = adva_x1_cpld_write(bp, CPLD_CMD_REFRESH);
5058 	if (err)
5059 		goto exit_config;
5060 
5061 	/* REFRESH reboots the CPLD out of configuration mode, so the exit
5062 	 * path must not send DIS_CFG afterwards even if a check below fails.
5063 	 */
5064 	bp->cpld_in_config_mode = false;
5065 
5066 	/* The new image is already running, so a segment that is not back
5067 	 * yet must not be reported as a failed update: retry the reselect
5068 	 * rather than sampling the mux once at a fixed delay.
5069 	 */
5070 	msleep(1500);
5071 	err = read_poll_timeout(adva_x1_mux_select, err, !err, CPLD_POLL_US,
5072 				3000 * USEC_PER_MSEC, false,
5073 				bp, ADVA_MUX_CHANNEL);
5074 	if (err)
5075 		goto deselect;
5076 
5077 	err = adva_x1_cpld_wait_ready(bp, 3000);
5078 	if (err)
5079 		goto deselect;
5080 
5081 	/* Require DONE set, not busy and no error code, as machxo2-spi.c does
5082 	 * after a refresh: without it a CRC or preamble error reads back as a
5083 	 * successful update.
5084 	 */
5085 	err = adva_x1_cpld_read_status(bp, &st);
5086 	if (err)
5087 		goto deselect;
5088 	if (!(st & CPLD_STATUS_DONE) || (st & CPLD_STATUS_BUSY) ||
5089 	    (st & CPLD_STATUS_ERR)) {
5090 		dev_err(&bp->pdev->dev,
5091 			"CPLD refresh left status 0x%08x\n", st);
5092 		NL_SET_ERR_MSG_MOD(extack, "CPLD did not come back configured");
5093 		err = -EIO;
5094 		goto deselect;
5095 	}
5096 
5097 exit_config:
5098 	adva_x1_cpld_exit_config(bp);
5099 deselect:
5100 	ret = adva_x1_mux_select(bp, -1);
5101 	if (!err)
5102 		err = ret;
5103 	ret = adva_x1_bus_release(bp);
5104 	if (!err)
5105 		err = ret;
5106 unlock:
5107 	mutex_unlock(&bp->cpld_lock);
5108 
5109 	return err;
5110 }
5111 
5112 static struct attribute *adva_timecard_attrs[] = {
5113 	&dev_attr_serialnum.attr,
5114 	&dev_attr_gnss_sync.attr,
5115 	&dev_attr_clock_source.attr,
5116 	&dev_attr_available_clock_sources.attr,
5117 	&dev_attr_sma1.attr,
5118 	&dev_attr_sma2.attr,
5119 	&dev_attr_sma3.attr,
5120 	&dev_attr_sma4.attr,
5121 	&dev_attr_available_sma_inputs.attr,
5122 	&dev_attr_available_sma_outputs.attr,
5123 	&dev_attr_clock_status_drift.attr,
5124 	&dev_attr_clock_status_offset.attr,
5125 	&dev_attr_ts_window_adjust.attr,
5126 	&dev_attr_tod_correction.attr,
5127 	NULL,
5128 };
5129 
5130 static const struct attribute_group adva_timecard_group = {
5131 	.attrs = adva_timecard_attrs,
5132 };
5133 
5134 static const struct ocp_attr_group adva_timecard_groups[] = {
5135 	{ .cap = OCP_CAP_BASIC,	    .group = &adva_timecard_group },
5136 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
5137 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
5138 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
5139 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
5140 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
5141 	{ },
5142 };
5143 
5144 static struct attribute *adva_timecard_x1_attrs[] = {
5145 	&dev_attr_serialnum.attr,
5146 	&dev_attr_gnss_sync.attr,
5147 	&dev_attr_clock_source.attr,
5148 	&dev_attr_available_clock_sources.attr,
5149 	&dev_attr_sma1.attr,
5150 	&dev_attr_sma2.attr,
5151 	&dev_attr_sma3.attr,
5152 	&dev_attr_sma4.attr,
5153 	&dev_attr_available_sma_inputs.attr,
5154 	&dev_attr_available_sma_outputs.attr,
5155 	&dev_attr_clock_status_drift.attr,
5156 	&dev_attr_clock_status_offset.attr,
5157 	&dev_attr_ts_window_adjust.attr,
5158 	&dev_attr_utc_tai_offset.attr,
5159 	&dev_attr_tod_correction.attr,
5160 	&dev_attr_cpld_status.attr,
5161 	NULL,
5162 };
5163 
5164 static const struct attribute_group adva_timecard_x1_group = {
5165 	.attrs = adva_timecard_x1_attrs,
5166 };
5167 
5168 static const struct ocp_attr_group adva_timecard_x1_groups[] = {
5169 	{ .cap = OCP_CAP_BASIC,	    .group = &adva_timecard_x1_group },
5170 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
5171 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
5172 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
5173 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
5174 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
5175 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
5176 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
5177 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
5178 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
5179 	{ },
5180 };
5181 
5182 static void
5183 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
5184 	       const char *def)
5185 {
5186 	int i;
5187 
5188 	for (i = 0; i < 4; i++) {
5189 		if (bp->sma[i].mode != SMA_MODE_IN)
5190 			continue;
5191 		if (map[i][0] & (1 << bit)) {
5192 			sprintf(buf, "sma%d", i + 1);
5193 			return;
5194 		}
5195 	}
5196 	if (!def)
5197 		def = "----";
5198 	strcpy(buf, def);
5199 }
5200 
5201 static void
5202 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
5203 {
5204 	char *ans = buf;
5205 	int i;
5206 
5207 	strcpy(ans, "----");
5208 	for (i = 0; i < 4; i++) {
5209 		if (bp->sma[i].mode != SMA_MODE_OUT)
5210 			continue;
5211 		if (map[i][1] & (1 << bit))
5212 			ans += sprintf(ans, "sma%d ", i + 1);
5213 	}
5214 }
5215 
5216 static void
5217 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
5218 {
5219 	struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
5220 	struct ptp_ocp_signal *signal = &bp->signal[nr];
5221 	char label[16];
5222 	bool on;
5223 	u32 val;
5224 
5225 	on = signal->running;
5226 	sprintf(label, "GEN%d", nr + 1);
5227 	seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
5228 		   label, on ? " ON" : "OFF",
5229 		   signal->period, signal->duty, signal->phase,
5230 		   signal->polarity);
5231 
5232 	val = ioread32(&reg->enable);
5233 	seq_printf(s, " [%x", val);
5234 	val = ioread32(&reg->status);
5235 	seq_printf(s, " %x]", val);
5236 
5237 	seq_printf(s, " start:%llu\n", signal->start);
5238 }
5239 
5240 static void
5241 _frequency_summary_show(struct seq_file *s, int nr,
5242 			struct frequency_reg __iomem *reg)
5243 {
5244 	char label[16];
5245 	bool on;
5246 	u32 val;
5247 
5248 	if (!reg)
5249 		return;
5250 
5251 	sprintf(label, "FREQ%d", nr + 1);
5252 	val = ioread32(&reg->ctrl);
5253 	on = val & 1;
5254 	val = (val >> 8) & 0xff;
5255 	seq_printf(s, "%7s: %s, sec:%u",
5256 		   label,
5257 		   on ? " ON" : "OFF",
5258 		   val);
5259 
5260 	val = ioread32(&reg->status);
5261 	if (val & FREQ_STATUS_ERROR)
5262 		seq_printf(s, ", error");
5263 	if (val & FREQ_STATUS_OVERRUN)
5264 		seq_printf(s, ", overrun");
5265 	if (val & FREQ_STATUS_VALID)
5266 		seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
5267 	seq_printf(s, "  reg:%x\n", val);
5268 }
5269 
5270 static int
5271 ptp_ocp_summary_show(struct seq_file *s, void *data)
5272 {
5273 	struct device *dev = s->private;
5274 	struct ptp_system_timestamp sts;
5275 	struct ts_reg __iomem *ts_reg;
5276 	char *buf, *src, *mac_src;
5277 	struct timespec64 ts;
5278 	struct ptp_ocp *bp;
5279 	u16 sma_val[4][2];
5280 	u32 ctrl, val;
5281 	bool on, map;
5282 	int i;
5283 
5284 	buf = (char *)__get_free_page(GFP_KERNEL);
5285 	if (!buf)
5286 		return -ENOMEM;
5287 
5288 	bp = dev_get_drvdata(dev);
5289 
5290 	seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
5291 	for (i = 0; i < __PORT_COUNT; i++) {
5292 		if (bp->port[i].uport)
5293 			seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
5294 				   bp->port[i].uport->port.line);
5295 	}
5296 
5297 	memset(sma_val, 0xff, sizeof(sma_val));
5298 	if (bp->sma_map1) {
5299 		u32 reg;
5300 
5301 		reg = ioread32(&bp->sma_map1->gpio1);
5302 		sma_val[0][0] = reg & 0xffff;
5303 		sma_val[1][0] = reg >> 16;
5304 
5305 		reg = ioread32(&bp->sma_map1->gpio2);
5306 		sma_val[2][1] = reg & 0xffff;
5307 		sma_val[3][1] = reg >> 16;
5308 
5309 		reg = ioread32(&bp->sma_map2->gpio1);
5310 		sma_val[2][0] = reg & 0xffff;
5311 		sma_val[3][0] = reg >> 16;
5312 
5313 		reg = ioread32(&bp->sma_map2->gpio2);
5314 		sma_val[0][1] = reg & 0xffff;
5315 		sma_val[1][1] = reg >> 16;
5316 	}
5317 
5318 	sma1_show(dev, NULL, buf);
5319 	seq_printf(s, "   sma1: %04x,%04x %s",
5320 		   sma_val[0][0], sma_val[0][1], buf);
5321 
5322 	sma2_show(dev, NULL, buf);
5323 	seq_printf(s, "   sma2: %04x,%04x %s",
5324 		   sma_val[1][0], sma_val[1][1], buf);
5325 
5326 	sma3_show(dev, NULL, buf);
5327 	seq_printf(s, "   sma3: %04x,%04x %s",
5328 		   sma_val[2][0], sma_val[2][1], buf);
5329 
5330 	sma4_show(dev, NULL, buf);
5331 	seq_printf(s, "   sma4: %04x,%04x %s",
5332 		   sma_val[3][0], sma_val[3][1], buf);
5333 
5334 	if (bp->ts0) {
5335 		ts_reg = bp->ts0->mem;
5336 		on = ioread32(&ts_reg->enable);
5337 		src = "GNSS1";
5338 		seq_printf(s, "%7s: %s, src: %s\n", "TS0",
5339 			   on ? " ON" : "OFF", src);
5340 	}
5341 
5342 	if (bp->ts1) {
5343 		ts_reg = bp->ts1->mem;
5344 		on = ioread32(&ts_reg->enable);
5345 		gpio_input_map(buf, bp, sma_val, 2, NULL);
5346 		seq_printf(s, "%7s: %s, src: %s\n", "TS1",
5347 			   on ? " ON" : "OFF", buf);
5348 	}
5349 
5350 	if (bp->ts2) {
5351 		ts_reg = bp->ts2->mem;
5352 		on = ioread32(&ts_reg->enable);
5353 		gpio_input_map(buf, bp, sma_val, 3, NULL);
5354 		seq_printf(s, "%7s: %s, src: %s\n", "TS2",
5355 			   on ? " ON" : "OFF", buf);
5356 	}
5357 
5358 	if (bp->ts3) {
5359 		ts_reg = bp->ts3->mem;
5360 		on = ioread32(&ts_reg->enable);
5361 		gpio_input_map(buf, bp, sma_val, 6, NULL);
5362 		seq_printf(s, "%7s: %s, src: %s\n", "TS3",
5363 			   on ? " ON" : "OFF", buf);
5364 	}
5365 
5366 	if (bp->ts4) {
5367 		ts_reg = bp->ts4->mem;
5368 		on = ioread32(&ts_reg->enable);
5369 		gpio_input_map(buf, bp, sma_val, 7, NULL);
5370 		seq_printf(s, "%7s: %s, src: %s\n", "TS4",
5371 			   on ? " ON" : "OFF", buf);
5372 	}
5373 
5374 	if (bp->pps) {
5375 		ts_reg = bp->pps->mem;
5376 		src = "PHC";
5377 		on = ioread32(&ts_reg->enable);
5378 		map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
5379 		seq_printf(s, "%7s: %s, src: %s\n", "TS5",
5380 			   on && map ? " ON" : "OFF", src);
5381 
5382 		map = !!(bp->pps_req_map & OCP_REQ_PPS);
5383 		seq_printf(s, "%7s: %s, src: %s\n", "PPS",
5384 			   on && map ? " ON" : "OFF", src);
5385 	}
5386 
5387 	if (bp->fw_cap & OCP_CAP_SIGNAL)
5388 		for (i = 0; i < bp->signals_nr; i++)
5389 			_signal_summary_show(s, bp, i);
5390 
5391 	if (bp->fw_cap & OCP_CAP_FREQ)
5392 		for (i = 0; i < bp->freq_in_nr; i++)
5393 			_frequency_summary_show(s, i, bp->freq_in[i]);
5394 
5395 	if (bp->irig_out) {
5396 		ctrl = ioread32(&bp->irig_out->ctrl);
5397 		on = ctrl & IRIG_M_CTRL_ENABLE;
5398 		val = ioread32(&bp->irig_out->status);
5399 		gpio_output_map(buf, bp, sma_val, 4);
5400 		seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
5401 			   on ? " ON" : "OFF", val, (ctrl >> 16), buf);
5402 	}
5403 
5404 	if (bp->irig_in) {
5405 		on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
5406 		val = ioread32(&bp->irig_in->status);
5407 		gpio_input_map(buf, bp, sma_val, 4, NULL);
5408 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
5409 			   on ? " ON" : "OFF", val, buf);
5410 	}
5411 
5412 	if (bp->dcf_out) {
5413 		on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
5414 		val = ioread32(&bp->dcf_out->status);
5415 		gpio_output_map(buf, bp, sma_val, 5);
5416 		seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
5417 			   on ? " ON" : "OFF", val, buf);
5418 	}
5419 
5420 	if (bp->dcf_in) {
5421 		on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
5422 		val = ioread32(&bp->dcf_in->status);
5423 		gpio_input_map(buf, bp, sma_val, 5, NULL);
5424 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
5425 			   on ? " ON" : "OFF", val, buf);
5426 	}
5427 
5428 	if (bp->nmea_out) {
5429 		on = ioread32(&bp->nmea_out->ctrl) & 1;
5430 		val = ioread32(&bp->nmea_out->status);
5431 		seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
5432 			   on ? " ON" : "OFF", val);
5433 	}
5434 
5435 	/* compute src for PPS1, used below. */
5436 	if (bp->pps_select) {
5437 		val = ioread32(&bp->pps_select->gpio1);
5438 		src = &buf[80];
5439 		mac_src = "GNSS1";
5440 		if (val & 0x01) {
5441 			gpio_input_map(src, bp, sma_val, 0, NULL);
5442 			mac_src = src;
5443 		} else if (val & 0x02) {
5444 			src = "MAC";
5445 		} else if (val & 0x04) {
5446 			src = "GNSS1";
5447 		} else {
5448 			src = "----";
5449 			mac_src = src;
5450 		}
5451 	} else {
5452 		src = "?";
5453 		mac_src = src;
5454 	}
5455 	seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
5456 
5457 	gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
5458 	seq_printf(s, "MAC PPS2 src: %s\n", buf);
5459 
5460 	/* assumes automatic switchover/selection */
5461 	val = ioread32(&bp->reg->select);
5462 	switch (val >> 16) {
5463 	case 0:
5464 		sprintf(buf, "----");
5465 		break;
5466 	case 2:
5467 		sprintf(buf, "IRIG");
5468 		break;
5469 	case 3:
5470 		sprintf(buf, "%s via PPS1", src);
5471 		break;
5472 	case 6:
5473 		sprintf(buf, "DCF");
5474 		break;
5475 	default:
5476 		strcpy(buf, "unknown");
5477 		break;
5478 	}
5479 	seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
5480 		   bp->sync ? "sync" : "unsynced");
5481 
5482 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
5483 		struct timespec64 sys_ts;
5484 		s64 pre_ns, post_ns, ns;
5485 
5486 		pre_ns = ktime_to_ns(sts.pre_sts.systime);
5487 		post_ns = ktime_to_ns(sts.post_sts.systime);
5488 		ns = (pre_ns + post_ns) / 2;
5489 		ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
5490 		sys_ts = ns_to_timespec64(ns);
5491 
5492 		seq_printf(s, "%7s: %ptSp == %ptS TAI\n", "PHC", &ts, &ts);
5493 		seq_printf(s, "%7s: %ptSp == %ptS UTC offset %d\n", "SYS",
5494 			   &sys_ts, &sys_ts, bp->utc_tai_offset);
5495 		seq_printf(s, "%7s: PHC:SYS offset: %lld  window: %lld\n", "",
5496 			   timespec64_to_ns(&ts) - ns,
5497 			   post_ns - pre_ns);
5498 	}
5499 
5500 	free_page((unsigned long)buf);
5501 	return 0;
5502 }
5503 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
5504 
5505 static int
5506 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
5507 {
5508 	struct device *dev = s->private;
5509 	struct ptp_ocp *bp;
5510 	u32 val;
5511 	int idx;
5512 
5513 	bp = dev_get_drvdata(dev);
5514 
5515 	val = ioread32(&bp->tod->ctrl);
5516 	if (!(val & TOD_CTRL_ENABLE)) {
5517 		seq_printf(s, "TOD Slave disabled\n");
5518 		return 0;
5519 	}
5520 	seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
5521 
5522 	idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
5523 	idx += (val >> 16) & 3;
5524 	seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
5525 
5526 	idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
5527 	seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
5528 
5529 	val = ioread32(&bp->tod->version);
5530 	seq_printf(s, "TOD Version %d.%d.%d\n",
5531 		val >> 24, (val >> 16) & 0xff, val & 0xffff);
5532 
5533 	val = ioread32(&bp->tod->status);
5534 	seq_printf(s, "Status register: 0x%08X\n", val);
5535 
5536 	val = ioread32(&bp->tod->adj_sec);
5537 	idx = (val & ~INT_MAX) ? -1 : 1;
5538 	idx *= (val & INT_MAX);
5539 	seq_printf(s, "Correction seconds: %d\n", idx);
5540 
5541 	val = ioread32(&bp->tod->utc_status);
5542 	seq_printf(s, "UTC status register: 0x%08X\n", val);
5543 	seq_printf(s, "UTC offset: %ld  valid:%d\n",
5544 		val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
5545 	seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
5546 		val & TOD_STATUS_LEAP_VALID ? 1 : 0,
5547 		val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
5548 
5549 	val = ioread32(&bp->tod->leap);
5550 	seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
5551 
5552 	return 0;
5553 }
5554 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
5555 
5556 static struct dentry *ptp_ocp_debugfs_root;
5557 
5558 static void
5559 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
5560 {
5561 	struct dentry *d;
5562 
5563 	d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
5564 	bp->debug_root = d;
5565 	debugfs_create_file("summary", 0444, bp->debug_root,
5566 			    &bp->dev, &ptp_ocp_summary_fops);
5567 	if (bp->tod)
5568 		debugfs_create_file("tod_status", 0444, bp->debug_root,
5569 				    &bp->dev, &ptp_ocp_tod_status_fops);
5570 }
5571 
5572 static void
5573 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
5574 {
5575 	debugfs_remove_recursive(bp->debug_root);
5576 }
5577 
5578 static void
5579 ptp_ocp_debugfs_init(void)
5580 {
5581 	ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
5582 }
5583 
5584 static void
5585 ptp_ocp_debugfs_fini(void)
5586 {
5587 	debugfs_remove_recursive(ptp_ocp_debugfs_root);
5588 }
5589 
5590 static void
5591 ptp_ocp_dev_release(struct device *dev)
5592 {
5593 	struct ptp_ocp *bp = dev_get_drvdata(dev);
5594 
5595 	mutex_lock(&ptp_ocp_lock);
5596 	idr_remove(&ptp_ocp_idr, bp->id);
5597 	mutex_unlock(&ptp_ocp_lock);
5598 }
5599 
5600 static int
5601 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
5602 {
5603 	int i, err;
5604 
5605 	mutex_lock(&ptp_ocp_lock);
5606 	err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
5607 	mutex_unlock(&ptp_ocp_lock);
5608 	if (err < 0) {
5609 		dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
5610 		return err;
5611 	}
5612 	bp->id = err;
5613 
5614 	bp->ptp_info = ptp_ocp_clock_info;
5615 	spin_lock_init(&bp->lock);
5616 
5617 	for (i = 0; i < __PORT_COUNT; i++)
5618 		bp->port[i].uport = NULL;
5619 
5620 	bp->pdev = pdev;
5621 
5622 	device_initialize(&bp->dev);
5623 	dev_set_name(&bp->dev, "ocp%d", bp->id);
5624 	bp->dev.class = &timecard_class;
5625 	bp->dev.parent = &pdev->dev;
5626 	bp->dev.release = ptp_ocp_dev_release;
5627 	dev_set_drvdata(&bp->dev, bp);
5628 
5629 	err = device_add(&bp->dev);
5630 	if (err) {
5631 		dev_err(&bp->dev, "device add failed: %d\n", err);
5632 		goto out;
5633 	}
5634 
5635 	pci_set_drvdata(pdev, bp);
5636 
5637 	return 0;
5638 
5639 out:
5640 	put_device(&bp->dev);
5641 	return err;
5642 }
5643 
5644 static void
5645 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
5646 {
5647 	struct device *dev = &bp->dev;
5648 
5649 	if (sysfs_create_link(&dev->kobj, &child->kobj, link))
5650 		dev_err(dev, "%s symlink failed\n", link);
5651 }
5652 
5653 static void
5654 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
5655 {
5656 	struct device *dev, *child;
5657 
5658 	dev = &bp->pdev->dev;
5659 
5660 	child = device_find_child_by_name(dev, name);
5661 	if (!child) {
5662 		dev_err(dev, "Could not find device %s\n", name);
5663 		return;
5664 	}
5665 
5666 	ptp_ocp_symlink(bp, child, link);
5667 	put_device(child);
5668 }
5669 
5670 static int
5671 ptp_ocp_complete(struct ptp_ocp *bp)
5672 {
5673 	struct pps_device *pps;
5674 	char buf[32];
5675 
5676 	sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
5677 	ptp_ocp_link_child(bp, buf, "ptp");
5678 
5679 	pps = pps_lookup_dev(bp->ptp);
5680 	if (pps)
5681 		ptp_ocp_symlink(bp, &pps->dev, "pps");
5682 
5683 	ptp_ocp_debugfs_add_device(bp);
5684 
5685 	return 0;
5686 }
5687 
5688 static void
5689 ptp_ocp_phc_info(struct ptp_ocp *bp)
5690 {
5691 	struct timespec64 ts;
5692 	u32 version, select;
5693 
5694 	version = ioread32(&bp->reg->version);
5695 	select = ioread32(&bp->reg->select);
5696 	dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
5697 		 version >> 24, (version >> 16) & 0xff, version & 0xffff,
5698 		 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
5699 		 ptp_clock_index(bp->ptp));
5700 
5701 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
5702 		dev_info(&bp->pdev->dev, "Time: %ptSp, %s\n",
5703 			 &ts, bp->sync ? "in-sync" : "UNSYNCED");
5704 }
5705 
5706 static void
5707 ptp_ocp_serial_info(struct device *dev, const char *name, struct uart_8250_port *port, int baud)
5708 {
5709 	if (port)
5710 		dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port->port.line, baud);
5711 }
5712 
5713 static void
5714 ptp_ocp_info(struct ptp_ocp *bp)
5715 {
5716 	static int nmea_baud[] = {
5717 		1200, 2400, 4800, 9600, 19200, 38400,
5718 		57600, 115200, 230400, 460800, 921600,
5719 		1000000, 2000000
5720 	};
5721 	struct device *dev = &bp->pdev->dev;
5722 	u32 reg;
5723 	int i;
5724 
5725 	ptp_ocp_phc_info(bp);
5726 
5727 	for (i = 0; i < __PORT_COUNT; i++) {
5728 		if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].uport) {
5729 			bp->port[PORT_NMEA].baud = -1;
5730 
5731 			reg = ioread32(&bp->nmea_out->uart_baud);
5732 			if (reg < ARRAY_SIZE(nmea_baud))
5733 				bp->port[PORT_NMEA].baud = nmea_baud[reg];
5734 		}
5735 		ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].uport,
5736 				    bp->port[i].baud);
5737 	}
5738 }
5739 
5740 static void
5741 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
5742 {
5743 	struct device *dev = &bp->dev;
5744 
5745 	sysfs_remove_link(&dev->kobj, "ptp");
5746 	sysfs_remove_link(&dev->kobj, "pps");
5747 }
5748 
5749 static void
5750 ptp_ocp_detach(struct ptp_ocp *bp)
5751 {
5752 	int i;
5753 
5754 	ptp_ocp_debugfs_remove_device(bp);
5755 	ptp_ocp_detach_sysfs(bp);
5756 	ptp_ocp_attr_group_del(bp);
5757 	timer_delete_sync(&bp->watchdog);
5758 	/* Disable interrupts on all timestampers */
5759 	if (bp->ts0)
5760 		ptp_ocp_ts_enable(bp->ts0, 0, false);
5761 	if (bp->ts1)
5762 		ptp_ocp_ts_enable(bp->ts1, 0, false);
5763 	if (bp->ts2)
5764 		ptp_ocp_ts_enable(bp->ts2, 0, false);
5765 	if (bp->ts3)
5766 		ptp_ocp_ts_enable(bp->ts3, 0, false);
5767 	if (bp->ts4)
5768 		ptp_ocp_ts_enable(bp->ts4, 0, false);
5769 	if (bp->pps)
5770 		ptp_ocp_ts_enable(bp->pps, ~0, false);
5771 	if (bp->ptp)
5772 		ptp_clock_unregister(bp->ptp);
5773 	kfree(bp->ptp_info.pin_config);
5774 	ptp_ocp_unregister_ext(bp->ts0);
5775 	ptp_ocp_unregister_ext(bp->ts1);
5776 	ptp_ocp_unregister_ext(bp->ts2);
5777 	ptp_ocp_unregister_ext(bp->ts3);
5778 	ptp_ocp_unregister_ext(bp->ts4);
5779 	ptp_ocp_unregister_ext(bp->pps);
5780 	for (i = 0; i < 4; i++)
5781 		ptp_ocp_unregister_ext(bp->signal_out[i]);
5782 	for (i = 0; i < __PORT_COUNT; i++)
5783 		if (bp->port[i].uport)
5784 			serial8250_unregister_port(bp->port[i].uport);
5785 	platform_device_unregister(bp->spi_flash);
5786 	platform_device_unregister(bp->i2c_ctrl);
5787 	if (bp->i2c_clk)
5788 		clk_hw_unregister_fixed_rate(bp->i2c_clk);
5789 	if (bp->n_irqs)
5790 		pci_free_irq_vectors(bp->pdev);
5791 	mutex_destroy(&bp->cpld_lock);
5792 	device_unregister(&bp->dev);
5793 }
5794 
5795 static int
5796 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
5797 			     enum dpll_lock_status *status,
5798 			     enum dpll_lock_status_error *status_error,
5799 			     struct netlink_ext_ack *extack)
5800 {
5801 	struct ptp_ocp *bp = priv;
5802 
5803 	*status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
5804 
5805 	return 0;
5806 }
5807 
5808 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
5809 				  const struct dpll_device *dpll, void *priv,
5810 				  enum dpll_pin_state *state,
5811 				  struct netlink_ext_ack *extack)
5812 {
5813 	struct ptp_ocp *bp = priv;
5814 	int idx;
5815 
5816 	if (bp->pps_select) {
5817 		idx = ioread32(&bp->pps_select->gpio1);
5818 		*state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
5819 						      DPLL_PIN_STATE_SELECTABLE;
5820 		return 0;
5821 	}
5822 	NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
5823 	return -EINVAL;
5824 }
5825 
5826 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
5827 				 enum dpll_mode *mode, struct netlink_ext_ack *extack)
5828 {
5829 	*mode = DPLL_MODE_AUTOMATIC;
5830 	return 0;
5831 }
5832 
5833 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
5834 				      void *pin_priv,
5835 				      const struct dpll_device *dpll,
5836 				      void *priv,
5837 				      enum dpll_pin_direction *direction,
5838 				      struct netlink_ext_ack *extack)
5839 {
5840 	struct ptp_ocp_sma_connector *sma = pin_priv;
5841 
5842 	*direction = sma->mode == SMA_MODE_IN ?
5843 				  DPLL_PIN_DIRECTION_INPUT :
5844 				  DPLL_PIN_DIRECTION_OUTPUT;
5845 	return 0;
5846 }
5847 
5848 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
5849 				      void *pin_priv,
5850 				      const struct dpll_device *dpll,
5851 				      void *dpll_priv,
5852 				      enum dpll_pin_direction direction,
5853 				      struct netlink_ext_ack *extack)
5854 {
5855 	struct ptp_ocp_sma_connector *sma = pin_priv;
5856 	struct ptp_ocp *bp = dpll_priv;
5857 	enum ptp_ocp_sma_mode mode;
5858 	int sma_nr = (sma - bp->sma);
5859 
5860 	if (sma->fixed_dir)
5861 		return -EOPNOTSUPP;
5862 	mode = direction == DPLL_PIN_DIRECTION_INPUT ?
5863 			    SMA_MODE_IN : SMA_MODE_OUT;
5864 	return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
5865 }
5866 
5867 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
5868 				      void *pin_priv,
5869 				      const struct dpll_device *dpll,
5870 				      void *dpll_priv, u64 frequency,
5871 				      struct netlink_ext_ack *extack)
5872 {
5873 	struct ptp_ocp_sma_connector *sma = pin_priv;
5874 	struct ptp_ocp *bp = dpll_priv;
5875 	const struct ocp_selector *tbl;
5876 	int sma_nr = (sma - bp->sma);
5877 	int i;
5878 
5879 	if (sma->fixed_fcn)
5880 		return -EOPNOTSUPP;
5881 
5882 	tbl = bp->sma_op->tbl[sma->mode];
5883 	for (i = 0; tbl[i].name; i++)
5884 		if (tbl[i].frequency == frequency)
5885 			return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
5886 	return -EINVAL;
5887 }
5888 
5889 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
5890 				      void *pin_priv,
5891 				      const struct dpll_device *dpll,
5892 				      void *dpll_priv, u64 *frequency,
5893 				      struct netlink_ext_ack *extack)
5894 {
5895 	struct ptp_ocp_sma_connector *sma = pin_priv;
5896 	struct ptp_ocp *bp = dpll_priv;
5897 	const struct ocp_selector *tbl;
5898 	int sma_nr = (sma - bp->sma);
5899 	u32 val;
5900 	int i;
5901 
5902 	val = bp->sma_op->get(bp, sma_nr + 1);
5903 	tbl = bp->sma_op->tbl[sma->mode];
5904 	for (i = 0; tbl[i].name; i++)
5905 		if (val == tbl[i].value) {
5906 			*frequency = tbl[i].frequency;
5907 			return 0;
5908 		}
5909 
5910 	return -EINVAL;
5911 }
5912 
5913 static const struct dpll_device_ops dpll_ops = {
5914 	.lock_status_get = ptp_ocp_dpll_lock_status_get,
5915 	.mode_get = ptp_ocp_dpll_mode_get,
5916 };
5917 
5918 static const struct dpll_pin_ops dpll_pins_ops = {
5919 	.frequency_get = ptp_ocp_dpll_frequency_get,
5920 	.frequency_set = ptp_ocp_dpll_frequency_set,
5921 	.direction_get = ptp_ocp_dpll_direction_get,
5922 	.direction_set = ptp_ocp_dpll_direction_set,
5923 	.state_on_dpll_get = ptp_ocp_dpll_state_get,
5924 };
5925 
5926 static void
5927 ptp_ocp_sync_work(struct work_struct *work)
5928 {
5929 	struct ptp_ocp *bp;
5930 	bool sync;
5931 
5932 	bp = container_of(work, struct ptp_ocp, sync_work.work);
5933 	sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
5934 
5935 	if (bp->sync != sync)
5936 		dpll_device_change_ntf(bp->dpll);
5937 
5938 	bp->sync = sync;
5939 
5940 	/* Resolve the adapter here rather than once in probe, where it can
5941 	 * race the adapter's own registration, and read the ID as soon as it
5942 	 * turns up.  A claim can fail transiently - the firmware may not
5943 	 * grant the segment straight after power-up - so adva_x1_cpld_read_id()
5944 	 * retries a bounded number of times before giving up.
5945 	 */
5946 	adva_x1_cache_i2c_adap(bp);
5947 	if (bp->has_cpld && !READ_ONCE(bp->cpld_id_tried) &&
5948 	    READ_ONCE(bp->cpld_i2c_adap_nr) >= 0)
5949 		adva_x1_cpld_read_id(bp);
5950 
5951 	queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
5952 }
5953 
5954 static int
5955 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
5956 {
5957 	struct devlink *devlink;
5958 	struct ptp_ocp *bp;
5959 	int err, i;
5960 	u64 clkid;
5961 
5962 	devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
5963 	if (!devlink) {
5964 		dev_err(&pdev->dev, "devlink_alloc failed\n");
5965 		return -ENOMEM;
5966 	}
5967 
5968 	err = pci_enable_device(pdev);
5969 	if (err) {
5970 		dev_err(&pdev->dev, "pci_enable_device\n");
5971 		goto out_free;
5972 	}
5973 
5974 	bp = devlink_priv(devlink);
5975 	err = ptp_ocp_device_init(bp, pdev);
5976 	if (err)
5977 		goto out_disable;
5978 
5979 	/* Before the first error path that calls ptp_ocp_detach(), so
5980 	 * mutex_destroy() runs on an initialised mutex, and before
5981 	 * ptp_ocp_register_resources(), so this sentinel cannot overwrite an
5982 	 * adapter number the i2c notifier stores during registration.
5983 	 */
5984 	mutex_init(&bp->cpld_lock);
5985 	spin_lock_init(&bp->cpld_adap_lock);
5986 	bp->cpld_i2c_adap_nr = -1;
5987 
5988 	INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
5989 
5990 	/* compat mode.
5991 	 * Older FPGA firmware only returns 2 irq's.
5992 	 * allow this - if not all of the IRQ's are returned, skip the
5993 	 * extra devices and just register the clock.
5994 	 */
5995 	err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
5996 	if (err < 0) {
5997 		dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
5998 		goto out;
5999 	}
6000 	bp->n_irqs = err;
6001 	pci_set_master(pdev);
6002 
6003 	err = ptp_ocp_register_resources(bp, id->driver_data);
6004 	if (err)
6005 		goto out;
6006 
6007 	bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
6008 	if (IS_ERR(bp->ptp)) {
6009 		err = PTR_ERR(bp->ptp);
6010 		dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
6011 		bp->ptp = NULL;
6012 		goto out;
6013 	}
6014 
6015 	err = ptp_ocp_complete(bp);
6016 	if (err)
6017 		goto out;
6018 
6019 	ptp_ocp_info(bp);
6020 	devlink_register(devlink);
6021 
6022 	clkid = pci_get_dsn(pdev);
6023 	bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker);
6024 	if (IS_ERR(bp->dpll)) {
6025 		err = PTR_ERR(bp->dpll);
6026 		dev_err(&pdev->dev, "dpll_device_alloc failed\n");
6027 		goto out_devlink;
6028 	}
6029 
6030 	err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
6031 	if (err)
6032 		goto out_dpll_put;
6033 
6034 	for (i = 0; i < OCP_SMA_NUM; i++) {
6035 		bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE,
6036 						   &bp->sma[i].dpll_prop,
6037 						   &bp->sma[i].tracker);
6038 		if (IS_ERR(bp->sma[i].dpll_pin)) {
6039 			err = PTR_ERR(bp->sma[i].dpll_pin);
6040 			goto out_dpll;
6041 		}
6042 
6043 		err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
6044 					&bp->sma[i]);
6045 		if (err) {
6046 			dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6047 			goto out_dpll;
6048 		}
6049 	}
6050 	queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
6051 
6052 	return 0;
6053 out_dpll:
6054 	while (i--) {
6055 		dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
6056 		dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6057 	}
6058 	/* dpll_device_register() takes a second reference and stores bp; only
6059 	 * dpll_device_unregister() drops it.  Without this the device stays
6060 	 * visible with a priv pointer into storage devlink_free() will release.
6061 	 */
6062 	dpll_device_unregister(bp->dpll, &dpll_ops, bp);
6063 out_dpll_put:
6064 	dpll_device_put(bp->dpll, &bp->tracker);
6065 out_devlink:
6066 	/* detach() destroys cpld_lock; no devlink op may still reach it */
6067 	devlink_unregister(devlink);
6068 out:
6069 	ptp_ocp_detach(bp);
6070 out_disable:
6071 	pci_disable_device(pdev);
6072 out_free:
6073 	devlink_free(devlink);
6074 	return err;
6075 }
6076 
6077 static void
6078 ptp_ocp_remove(struct pci_dev *pdev)
6079 {
6080 	struct ptp_ocp *bp = pci_get_drvdata(pdev);
6081 	struct devlink *devlink = priv_to_devlink(bp);
6082 	int i;
6083 
6084 	cancel_delayed_work_sync(&bp->sync_work);
6085 	for (i = 0; i < OCP_SMA_NUM; i++) {
6086 		if (bp->sma[i].dpll_pin) {
6087 			dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
6088 			dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6089 		}
6090 	}
6091 	dpll_device_unregister(bp->dpll, &dpll_ops, bp);
6092 	dpll_device_put(bp->dpll, &bp->tracker);
6093 	devlink_unregister(devlink);
6094 	ptp_ocp_detach(bp);
6095 	pci_disable_device(pdev);
6096 
6097 	devlink_free(devlink);
6098 }
6099 
6100 static struct pci_driver ptp_ocp_driver = {
6101 	.name		= KBUILD_MODNAME,
6102 	.id_table	= ptp_ocp_pcidev_id,
6103 	.probe		= ptp_ocp_probe,
6104 	.remove		= ptp_ocp_remove,
6105 	.shutdown	= ptp_ocp_remove,
6106 };
6107 
6108 static int
6109 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
6110 			  unsigned long action, void *data)
6111 {
6112 	struct device *dev, *child = data;
6113 	struct i2c_adapter *adap;
6114 	struct ptp_ocp *bp;
6115 	bool add;
6116 
6117 	switch (action) {
6118 	case BUS_NOTIFY_ADD_DEVICE:
6119 	case BUS_NOTIFY_DEL_DEVICE:
6120 		add = action == BUS_NOTIFY_ADD_DEVICE;
6121 		break;
6122 	default:
6123 		return 0;
6124 	}
6125 
6126 	if (!i2c_verify_adapter(child))
6127 		return 0;
6128 
6129 	dev = child;
6130 	while ((dev = dev->parent))
6131 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
6132 			goto found;
6133 	return 0;
6134 
6135 found:
6136 	bp = dev_get_drvdata(dev);
6137 	adap = i2c_verify_adapter(child);
6138 	if (add) {
6139 		ptp_ocp_symlink(bp, child, "i2c");
6140 		/* Only the card's own controller: a mux child added on it
6141 		 * reaches ptp_ocp through the same walk.  Numbers are
6142 		 * recycled, so the claim re-checks the parent itself.
6143 		 */
6144 		if (bp->i2c_ctrl && adap->dev.parent == &bp->i2c_ctrl->dev) {
6145 			scoped_guard(spinlock, &bp->cpld_adap_lock)
6146 				bp->cpld_i2c_adap_nr = adap->nr;
6147 		}
6148 	} else {
6149 		/* invalidate before free, but only for the cached adapter */
6150 		scoped_guard(spinlock, &bp->cpld_adap_lock) {
6151 			if (bp->cpld_i2c_adap_nr == adap->nr)
6152 				bp->cpld_i2c_adap_nr = -1;
6153 		}
6154 		sysfs_remove_link(&bp->dev.kobj, "i2c");
6155 	}
6156 	return 0;
6157 }
6158 
6159 static struct notifier_block ptp_ocp_i2c_notifier = {
6160 	.notifier_call = ptp_ocp_i2c_notifier_call,
6161 };
6162 
6163 static int __init
6164 ptp_ocp_init(void)
6165 {
6166 	const char *what;
6167 	int err;
6168 
6169 	ptp_ocp_debugfs_init();
6170 
6171 	what = "timecard class";
6172 	err = class_register(&timecard_class);
6173 	if (err)
6174 		goto out;
6175 
6176 	what = "i2c notifier";
6177 	err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6178 	if (err)
6179 		goto out_notifier;
6180 
6181 	what = "ptp_ocp driver";
6182 	err = pci_register_driver(&ptp_ocp_driver);
6183 	if (err)
6184 		goto out_register;
6185 
6186 	return 0;
6187 
6188 out_register:
6189 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6190 out_notifier:
6191 	class_unregister(&timecard_class);
6192 out:
6193 	ptp_ocp_debugfs_fini();
6194 	pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
6195 	return err;
6196 }
6197 
6198 static void __exit
6199 ptp_ocp_fini(void)
6200 {
6201 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6202 	pci_unregister_driver(&ptp_ocp_driver);
6203 	class_unregister(&timecard_class);
6204 	ptp_ocp_debugfs_fini();
6205 }
6206 
6207 module_init(ptp_ocp_init);
6208 module_exit(ptp_ocp_fini);
6209 
6210 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
6211 MODULE_LICENSE("GPL v2");
6212