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/linux/arch/arm/boot/dts/ti/omap/
H A Domap3xxx-clocks.dtsi3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
H A Dam43xx-clocks.dtsi3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
26 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
[all …]
H A Dam33xx-clocks.dtsi3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
22 clock-mult = <1>;
[all …]
H A Domap54xx-clocks.dtsi3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Domap44xx-clocks.dtsi3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap24xx-clocks.dtsi3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
23 aes1_ick: clock-aes1-ick@3 {
25 #clock-cells = <0>;
26 compatible = "ti,omap3-interface-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
24 clock@a40 {
27 #clock-cells = <2>;
31 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
[all …]
H A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
H A Domap3430es1-clocks.dtsi3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
26 #clock-cells = <0>;
27 compatible = "fixed-factor-clock";
29 clock-mult = <1>;
30 clock-div = <1>;
34 #clock-cells = <0>;
[all …]
H A Ddm816x-clocks.dtsi5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
34 compatible = "ti,dm816-fapll-clock";
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi3 * Keystone 2 Kepler/Hawking SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
H A Dkeystone-k2l-clocks.dtsi3 * Keystone 2 lamarr SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi41 clock-names = "timclk", "apb_pclk";
50 clock-names = "timclk", "apb_pclk";
199 #clock-cells = <0>;
200 compatible = "fixed-clock";
201 clock-frequency = <19200000>;
205 * The 2.4 MHz TIMCLK reference clock is active at
207 * divided by 8. This clock is used by the timers and
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <8>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
47 clock-names = "bus";
53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
54 clock-names = "bus";
60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
61 clock-names = "bus";
[all …]
H A Dexynos5410.dtsi14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 { label
77 compatible = "samsung,exynos5410-clock";
[all …]
H A Dexynos5250.dtsi17 #include <dt-bindings/clock/exynos5250.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
64 clocks = <&clock CLK_ARM_CLK>;
65 clock-names = "cpu";
73 clocks = <&clock CLK_ARM_CLK>;
74 clock-names = "cpu";
87 clock-latency-ns = <140000>;
92 clock-latency-ns = <140000>;
97 clock-latency-ns = <140000>;
102 clock-latency-ns = <140000>;
[all …]
H A Dexynos4.dtsi19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
66 clock_audss: clock-controller@3810000 {
67 compatible = "samsung,exynos4210-audss-clock";
69 #clock-cells = <1>;
70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
71 <&clock CLK_SCLK_AUDIO0>,
72 <&clock CLK_SCLK_AUDIO0>;
73 clock-names = "pll_ref", "pll_in", "sclk_audio",
83 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
26 containing clock control registers
27 - #clock-cells:
[all …]
H A Dmvebu-core-clock.txt3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
14 The following is a list of provided IDs and clock names on Armada 375:
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dgate.txt1 Binding for Texas Instruments gate clock.
3 This binding uses the common clock binding[1]. This clock is
4 quite much similar to the basic gate-clock [2], however,
6 is provided for this clock, the code assumes that a clockdomain
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
12 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
[all …]
/linux/fs/bcachefs/
H A Dclock.c22 void bch2_io_timer_add(struct io_clock *clock, struct io_timer *timer) in bch2_io_timer_add() argument
24 spin_lock(&clock->timer_lock); in bch2_io_timer_add()
26 if (time_after_eq64((u64) atomic64_read(&clock->now), timer->expire)) { in bch2_io_timer_add()
27 spin_unlock(&clock->timer_lock); in bch2_io_timer_add()
32 for (size_t i = 0; i < clock->timers.nr; i++) in bch2_io_timer_add()
33 if (clock->timers.data[i] == timer) in bch2_io_timer_add()
36 BUG_ON(!min_heap_push(&clock->timers, &timer, &callbacks, NULL)); in bch2_io_timer_add()
38 spin_unlock(&clock->timer_lock); in bch2_io_timer_add()
41 void bch2_io_timer_del(struct io_clock *clock, struct io_timer *timer) in bch2_io_timer_del() argument
43 spin_lock(&clock->timer_lock); in bch2_io_timer_del()
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-clks.dtsi9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
[all …]

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