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Searched refs:clksrc (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/clocksource/
H A Dmmio.c12 struct clocksource clksrc; member
17 return container_of(c, struct clocksource_mmio, clksrc); in to_mmio_clksrc()
63 cs->clksrc.name = name; in clocksource_mmio_init()
64 cs->clksrc.rating = rating; in clocksource_mmio_init()
65 cs->clksrc.read = read; in clocksource_mmio_init()
66 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); in clocksource_mmio_init()
67 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in clocksource_mmio_init()
69 return clocksource_register_hz(&cs->clksrc, hz); in clocksource_mmio_init()
H A Dtimer-sun5i.c41 struct clocksource clksrc; member
48 container_of(x, struct sun5i_timer, clksrc)
141 static u64 sun5i_clksrc_read(struct clocksource *clksrc) in sun5i_clksrc_read() argument
143 struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc); in sun5i_clksrc_read()
156 clocksource_unregister(&cs->clksrc); in sun5i_rate_cb()
160 clocksource_register_hz(&cs->clksrc, ndata->new_rate); in sun5i_rate_cb()
183 cs->clksrc.name = pdev->dev.of_node->name; in sun5i_setup_clocksource()
184 cs->clksrc.rating = 340; in sun5i_setup_clocksource()
185 cs->clksrc.read = sun5i_clksrc_read; in sun5i_setup_clocksource()
186 cs->clksrc.mask = CLOCKSOURCE_MASK(32); in sun5i_setup_clocksource()
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H A Dtimer-atmel-pit.c40 struct clocksource clksrc; member
49 static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc) in clksrc_to_pit_data() argument
51 return container_of(clksrc, struct pit_data, clksrc); in clksrc_to_pit_data()
221 data->clksrc.mask = CLOCKSOURCE_MASK(bits); in at91sam926x_pit_dt_init()
222 data->clksrc.name = "pit"; in at91sam926x_pit_dt_init()
223 data->clksrc.rating = 175; in at91sam926x_pit_dt_init()
224 data->clksrc.read = read_pit_clk; in at91sam926x_pit_dt_init()
225 data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in at91sam926x_pit_dt_init()
227 ret = clocksource_register_hz(&data->clksrc, pit_rate); in at91sam926x_pit_dt_init()
239 clocksource_unregister(&data->clksrc); in at91sam926x_pit_dt_init()
H A Dtimer-microchip-pit64b.c85 struct clocksource clksrc; member
90 struct mchp_pit64b_clksrc, clksrc))
366 cs->clksrc.name = MCHP_PIT64B_NAME; in mchp_pit64b_init_clksrc()
367 cs->clksrc.mask = CLOCKSOURCE_MASK(64); in mchp_pit64b_init_clksrc()
368 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in mchp_pit64b_init_clksrc()
369 cs->clksrc.rating = 210; in mchp_pit64b_init_clksrc()
370 cs->clksrc.read = mchp_pit64b_clksrc_read; in mchp_pit64b_init_clksrc()
371 cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; in mchp_pit64b_init_clksrc()
372 cs->clksrc.resume = mchp_pit64b_clksrc_resume; in mchp_pit64b_init_clksrc()
374 ret = clocksource_register_hz(&cs->clksrc, clk_rate); in mchp_pit64b_init_clksrc()
H A Dtimer-atmel-tcb.c113 static struct clocksource clksrc = { variable
124 return tc_get_cycles(&clksrc); in tc_sched_clock_read()
129 return tc_get_cycles32(&clksrc); in tc_sched_clock_read32()
136 return tc_get_cycles(&clksrc); in tc_delay_timer_read()
141 return tc_get_cycles32(&clksrc); in tc_delay_timer_read32()
451 clksrc.name = kbasename(node->parent->full_name); in tcb_clksrc_init()
453 pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, in tcb_clksrc_init()
460 clksrc.read = tc_get_cycles32; in tcb_clksrc_init()
481 ret = clocksource_register_hz(&clksrc, divided_rate); in tcb_clksrc_init()
498 clocksource_unregister(&clksrc); in tcb_clksrc_init()
H A Dtimer-loongson1-pwm.c36 struct clocksource clksrc; member
41 return container_of(c, struct ls1x_clocksource, clksrc); in to_ls1x_clksrc()
207 .clksrc = {
231 return clocksource_register_hz(&ls1x_clocksource.clksrc, in ls1x_pwm_clocksource_init()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c44 u64 clksrc; member
67 u64 clksrc; member
97 u64 clksrc; member
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
146 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); in sja1105_cgu_mii_control_packing()
171 int clksrc; in sja1105_cgu_mii_tx_clk_config() local
177 clksrc = mac_clk_sources[port]; in sja1105_cgu_mii_tx_clk_config()
179 clksrc = phy_clk_sources[port]; in sja1105_cgu_mii_tx_clk_config()
182 mii_tx_clk.clksrc = clksrc; in sja1105_cgu_mii_tx_clk_config()
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H A Dsja1105_static_config.h230 u64 clksrc; member
H A Dsja1105_tas.c270 schedule_entry_points_params->clksrc = SJA1105_TAS_CLKSRC_PTP; in sja1105_init_scheduling()
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
60 clock-names = "clksrc", "extclksrc";
84 clock-names = "clksrc";
H A Dda8xx-cfgchip.txt40 - compatible: shall be "ti,da850-async1-clksrc".
48 - compatible: shall be "ti,da850-async3-clksrc".
78 compatible = "ti,da850-async1-clksrc";
84 compatible = "ti,da850-async3-clksrc";
/linux/arch/m68k/atari/
H A Ddebug.c219 int clksrc, clkmode, div, reg3, reg5; in atari_init_scc_port() local
227 clksrc = clksrc_table[baud]; in atari_init_scc_port()
232 clksrc = 0x28; /* TRxC */ in atari_init_scc_port()
252 SCC_WRITE(11, clksrc); /* main clock source */ in atari_init_scc_port()
/linux/include/linux/
H A Dsm501.h13 int clksrc, unsigned long freq);
16 int clksrc, unsigned long req_freq);
/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c720 static void tegra210_emc_set_clock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_set_clock() argument
722 emc->sequence->set_clock(emc, clksrc); in tegra210_emc_set_clock()
731 u32 clksrc) in tegra210_change_dll_src() argument
737 emc_clk_src = (clksrc & EMC_CLK_EMC_2X_CLK_SRC_MASK) >> in tegra210_change_dll_src()
739 emc_clk_div = (clksrc & EMC_CLK_EMC_2X_CLK_DIVISOR_MASK) >> in tegra210_change_dll_src()
792 u32 clksrc; in tegra210_emc_set_refresh() local
794 clksrc = emc->provider.configs[index].value | in tegra210_emc_set_refresh()
800 tegra210_emc_set_clock(emc, clksrc); in tegra210_emc_set_refresh()
839 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_do_clock_change() argument
846 tegra210_clk_emc_update_setting(clksrc); in tegra210_emc_do_clock_change()
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H A Dtegra210-emc.h939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
994 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc);
1008 u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc);
H A Dtegra210-emc-cc-r21021.c337 static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_r21021_set_clock() argument
431 emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc); in tegra210_emc_r21021_set_clock()
573 value = tegra210_emc_dll_prelock(emc, clksrc); in tegra210_emc_r21021_set_clock()
1394 tegra210_emc_do_clock_change(emc, clksrc); in tegra210_emc_r21021_set_clock()
/linux/sound/soc/codecs/
H A Dcs35l36.c52 int clksrc; member
1001 prev_clksrc = cs35l36->clksrc; in cs35l36_component_set_sysclk()
1005 cs35l36->clksrc = CS35L36_PLLSRC_SCLK; in cs35l36_component_set_sysclk()
1008 cs35l36->clksrc = CS35L36_PLLSRC_LRCLK; in cs35l36_component_set_sysclk()
1011 cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK; in cs35l36_component_set_sysclk()
1014 cs35l36->clksrc = CS35L36_PLLSRC_SELF; in cs35l36_component_set_sysclk()
1017 cs35l36->clksrc = CS35L36_PLLSRC_MCLK; in cs35l36_component_set_sysclk()
1040 cs35l36->clksrc); in cs35l36_component_set_sysclk()
1071 if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) { in cs35l36_component_set_sysclk()
H A Dcs35l41.c816 int extclk_cfg, clksrc; in cs35l41_component_set_sysclk() local
820 clksrc = CS35L41_PLLSRC_SCLK; in cs35l41_component_set_sysclk()
823 clksrc = CS35L41_PLLSRC_LRCLK; in cs35l41_component_set_sysclk()
826 clksrc = CS35L41_PLLSRC_MCLK; in cs35l41_component_set_sysclk()
851 CS35L41_PLL_CLK_SEL_MASK, clksrc); in cs35l41_component_set_sysclk()
H A Dcs35l35.c713 int clksrc; in cs35l35_component_set_sysclk() local
718 clksrc = CS35L35_CLK_SOURCE_MCLK; in cs35l35_component_set_sysclk()
721 clksrc = CS35L35_CLK_SOURCE_SCLK; in cs35l35_component_set_sysclk()
724 clksrc = CS35L35_CLK_SOURCE_PDM; in cs35l35_component_set_sysclk()
751 clksrc << CS35L35_CLK_SOURCE_SHIFT); in cs35l35_component_set_sysclk()
/linux/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_drv.c41 enum shmob_drm_clk_source clksrc) in shmob_drm_setup_clocks() argument
46 switch (clksrc) { in shmob_drm_setup_clocks()
/linux/sound/soc/fsl/
H A Dfsl_esai.c263 struct clk *clksrc = esai_priv->extalclk; in fsl_esai_set_dai_sysclk() local
293 clksrc = esai_priv->fsysclk; in fsl_esai_set_dai_sysclk()
305 if (IS_ERR(clksrc)) { in fsl_esai_set_dai_sysclk()
308 return PTR_ERR(clksrc); in fsl_esai_set_dai_sysclk()
310 clk_rate = clk_get_rate(clksrc); in fsl_esai_set_dai_sysclk()
328 if (ratio == 1 && clksrc == esai_priv->extalclk) { in fsl_esai_set_dai_sysclk()
H A Dfsl_spdif.c486 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc() local
488 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) in spdif_set_rx_clksrc()
493 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); in spdif_set_rx_clksrc()
1068 u8 clksrc; in spdif_get_rxclk_rate() local
1073 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; in spdif_get_rxclk_rate()
1076 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) in spdif_get_rxclk_rate()
/linux/drivers/mfd/
H A Dsm501.c509 int clksrc, in sm501_set_clock() argument
526 switch (clksrc) { in sm501_set_clock()
590 clock = clock & ~(0xFF << clksrc); in sm501_set_clock()
591 clock |= reg<<clksrc; in sm501_set_clock()
640 int clksrc, in sm501_find_clock() argument
647 switch (clksrc) { in sm501_find_clock()
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi139 clock-names = "clksrc", "extclksrc";
407 compatible = "ti,da850-async1-clksrc";
413 compatible = "ti,da850-async3-clksrc";
700 clock-names = "clksrc";
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c124 u8 clksrc; member
600 if (priv->mux_dsi_div_params.clksrc) in rzg2l_cpg_get_vclk_parent_rate()
704 parent = clk_hw_get_parent_by_index(hw, priv->mux_dsi_div_params.clksrc); in rzg2l_cpg_pll5_4_clk_mux_determine_rate()
797 if (priv->mux_dsi_div_params.clksrc) in rzg2l_cpg_get_vclk_rate()
937 priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */ in rzg2l_cpg_sipll5_register()

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