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Searched refs:clksel (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c142 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
147 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
149 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
151 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
156 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
158 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
167 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
216 u32 clksel; in dw_mci_exynos_resume_noirq() local
226 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
228 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
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/linux/drivers/clk/rockchip/
H A Dclk-cpu.c105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
125 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
129 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_pre_muxs()
130 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
141 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; in rockchip_cpuclk_set_post_muxs() local
143 if (!clksel->reg) in rockchip_cpuclk_set_post_muxs()
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/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c488 int clksel, ret; in ttc_timer_probe() local
516 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
517 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
518 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
524 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
525 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
526 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi9 compatible = "ti,clksel";
25 compatible = "ti,clksel";
56 compatible = "ti,clksel";
88 compatible = "ti,clksel";
176 compatible = "ti,clksel";
199 compatible = "ti,clksel";
H A Domap34xx-omap36xx-clocks.dtsi17 compatible = "ti,clksel";
66 compatible = "ti,clksel";
107 compatible = "ti,clksel";
163 compatible = "ti,clksel";
232 compatible = "ti,clksel";
257 compatible = "ti,clksel";
H A Domap3430es1-clocks.dtsi50 compatible = "ti,clksel";
82 compatible = "ti,clksel";
123 compatible = "ti,clksel";
177 compatible = "ti,clksel";
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi138 compatible = "ti,clksel";
154 compatible = "ti,clksel";
170 compatible = "ti,clksel";
186 compatible = "ti,clksel";
H A Domap3xxx-clocks.dtsi83 compatible = "ti,clksel";
122 compatible = "ti,clksel";
262 compatible = "ti,clksel";
434 compatible = "ti,clksel";
477 compatible = "ti,clksel";
611 compatible = "ti,clksel";
676 compatible = "ti,clksel";
721 compatible = "ti,clksel";
748 compatible = "ti,clksel";
929 compatible = "ti,clksel";
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H A Dam35xx-clocks.dtsi66 compatible = "ti,clksel";
102 compatible = "ti,clksel";
H A Ddra7xx-clocks.dtsi290 compatible = "ti,clksel";
381 compatible = "ti,clksel";
431 compatible = "ti,clksel";
481 compatible = "ti,clksel";
543 compatible = "ti,clksel";
580 compatible = "ti,clksel";
671 compatible = "ti,clksel";
899 compatible = "ti,clksel";
980 compatible = "ti,clksel";
1096 compatible = "ti,clksel";
[all …]
H A Domap36xx-clocks.dtsi62 compatible = "ti,clksel";
H A Dam33xx-clocks.dtsi108 compatible = "ti,clksel";
567 compatible = "ti,clksel";
573 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
592 compatible = "ti,clksel";
H A Ddra76x.dtsi89 compatible = "ti,clksel";
H A Dam43xx-clocks.dtsi572 dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
606 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c85 u32 clksel; in imx6q_1588_init() local
118 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
125 clksel); in imx6q_1588_init()
/linux/drivers/clk/
H A Dclk-qoriq.c59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
852 u32 clksel; in mux_set_parent() local
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
866 u32 clksel; in mux_get_parent() local
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
903 pll = hwc->info->clksel[idx].pll; in get_pll_div()
904 div = hwc->info->clksel[idx].div; in get_pll_div()
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c138 u32 clksel; member
143 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
251 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in rcar_lvds_pll_setup_d3_e3()