| /linux/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 74 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
89 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
118 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
134 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
137 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
141 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
147 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
150 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
153 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box_fpu() local
607 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box_fpu()
610 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box_fpu()
611 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box_fpu()
612 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box_fpu()
613 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box_fpu()
614 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box_fpu()
617 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box_fpu()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box_fpu()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/clk/mmp/ |
| H A D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kzalloc_objs(struct clk *, nr_clks); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
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| H A D | clk-pll.c | 168 unit->clk_table[clks[i].id] = clk; in mmp_register_pll_clks()
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| H A D | clk.h | 134 struct clk **clk_table; member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_processpptables.c | 571 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
576 clk_table = kzalloc_flex(*clk_table, entries, in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
581 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
584 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
586 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
590 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
643 clk_table = kzalloc_flex(*clk_table, entries, in get_gfxclk_voltage_dependency_table()
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
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| H A D | process_pptables_v1_0.c | 313 struct phm_clock_array **clk_table, in get_valid_clk() argument
336 *clk_table = table; in get_valid_clk()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
205 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfcl… in dcn32_build_wm_range_table_fpu()
207 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
208 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
246 …params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memcl… in dcn32_build_wm_range_table_fpu()
248 …params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memcl… in dcn32_build_wm_range_table_fpu()
250 …params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memcl… in dcn32_build_wm_range_table_fpu()
252 …params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memcl… in dcn32_build_wm_range_table_fpu()
2480 …int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_l… in dcn32_calculate_wm_and_dlg_fpu()
[all …]
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| /linux/drivers/clk/hisilicon/ |
| H A D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kzalloc_objs(*clk_table, nr_clks); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 608 .clk_table = {
658 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn42_build_watermark_ranges()
661 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn42_build_watermark_ranges()
721 if (i >= clk_mgr_base->bw_params->clk_table.num_entries) { in dcn42_notify_wm_ranges()
847 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn42_get_max_clock_khz()
849 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 : in dcn42_get_max_clock_khz()
852 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; in dcn42_get_max_clock_khz()
854 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : in dcn42_get_max_clock_khz()
857 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn42_get_max_clock_khz()
859 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 : in dcn42_get_max_clock_khz()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 47 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in get_minimum_clocks_for_latency()
68 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
73 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
77 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
116 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
120 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
149 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
153 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
190 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_idle_minimums()
618 …n_clocks.dcn4x.active.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->soc_bb->clk… in clamp_uclk_to_max()
[all …]
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| /linux/drivers/clk/axis/ |
| H A D | clk-artpec6.c | 20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_wrapper_fpu.c | 119 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
121 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()
123 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispc… in dml21_calculate_rq_and_dlg_params()
126 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
128 …in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.… in dml21_calculate_rq_and_dlg_params()
130 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk… in dml21_calculate_rq_and_dlg_params()
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| H A D | dml21_translation_helper.c | 970 …min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_… in dml21_init_min_clocks_for_dc_state()
971 …min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_st… in dml21_init_min_clocks_for_dc_state()
972 …min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_st… in dml21_init_min_clocks_for_dc_state()
973 …min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_sta… in dml21_init_min_clocks_for_dc_state()
974 …min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_… in dml21_init_min_clocks_for_dc_state()
982 …min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_st… in dml21_init_min_clocks_for_dc_state()
985 …min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_st… in dml21_init_min_clocks_for_dc_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2291 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
2375 …dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int hi… in construct_low_pstate_lvl() argument
2381 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; in construct_low_pstate_lvl()
2382 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; in construct_low_pstate_lvl()
2383 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz; in construct_low_pstate_lvl()
2384 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; in construct_low_pstate_lvl()
2394 for (i = clk_table->num_entries; i > 1; i--) in construct_low_pstate_lvl()
2395 clk_table->entries[i] = clk_table->entries[i-1]; in construct_low_pstate_lvl()
2396 clk_table->entries[1] = clk_table->entries[0]; in construct_low_pstate_lvl()
2397 clk_table->num_entries++; in construct_low_pstate_lvl()
[all …]
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| /linux/drivers/acpi/pmic/ |
| H A D | tps68470_pmic.c | 168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2159 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2162 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2163 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2164 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2165 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2166 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2167 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2168 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2169 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2192 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()
[all …]
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| /linux/sound/soc/samsung/ |
| H A D | i2s.c | 123 struct clk *clk_table[3]; member
814 rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC]; in i2s_hw_params()
1262 if (!IS_ERR(priv->clk_table[i])) in i2s_unregister_clocks()
1263 clk_unregister(priv->clk_table[i]); in i2s_unregister_clocks()
1311 priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev, in i2s_register_clock_provider()
1318 priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev, in i2s_register_clock_provider()
1328 priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, in i2s_register_clock_provider()
1335 priv->clk_data.clks = priv->clk_table; in i2s_register_clock_provider()
1545 priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]); in samsung_i2s_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/ |
| H A D | dcn42_soc_and_ip_translator.c | 44 dc_clk_table = &dc_bw_params->clk_table; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()
155 dcn42_convert_dc_clock_table_to_soc_bb_clock_table(&soc_bb->clk_table, &soc_bb->vmin_limit, in dcn42_update_soc_bb_with_values_from_clk_mgr()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk.c | 362 struct clk **clk_table; in rockchip_clk_init_base() local
372 clk_table = kzalloc_objs(struct clk *, nr_clks); in rockchip_clk_init_base()
373 if (!clk_table) in rockchip_clk_init_base()
377 clk_table[i] = default_clk_val; in rockchip_clk_init_base()
380 ctx->clk_data.clks = clk_table; in rockchip_clk_init_base()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 534 …ctive_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table) in dml2_core_utils_get_active_min_uclk_dpm_index() argument
539 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
540 …DML_LOG_VERBOSE("DML::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk… in dml2_core_utils_get_active_min_uclk_dpm_index()
542 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
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| H A D | dml2_core_utils.h | 29 …tive_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table);
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| H A D | dml2_core_dcn4.c | 647 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
648 if (uclk_freq_khz == soc_bb->clk_table.uclk.clk_values_khz[i]) in lookup_uclk_dpm_index_by_freq()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/ |
| H A D | dcn42_soc_bb.h | 73 .clk_table = {
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
81 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
1304 …et_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_t… in dcn401_prepare_bandwidth()
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