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Searched refs:clk_table (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c74 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
89 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
118 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
134 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
137 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
141 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
147 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
150 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
153 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
607 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
610 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
611 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
612 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
613 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
614 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
617 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu() local
278 ASSERT(clk_table->num_entries); in dcn351_update_bw_bounding_box_fpu()
281 for (i = 0; i < clk_table->num_entries; ++i) { in dcn351_update_bw_bounding_box_fpu()
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn351_update_bw_bounding_box_fpu()
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn351_update_bw_bounding_box_fpu()
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn351_update_bw_bounding_box_fpu()
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn351_update_bw_bounding_box_fpu()
288 for (i = 0; i < clk_table->num_entries; i++) { in dcn351_update_bw_bounding_box_fpu()
293 clk_table->entries[i].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()
298 if (clk_table->num_entries == 1) { in dcn351_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu() local
244 ASSERT(clk_table->num_entries); in dcn35_update_bw_bounding_box_fpu()
247 for (i = 0; i < clk_table->num_entries; ++i) { in dcn35_update_bw_bounding_box_fpu()
248 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn35_update_bw_bounding_box_fpu()
249 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn35_update_bw_bounding_box_fpu()
250 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn35_update_bw_bounding_box_fpu()
251 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn35_update_bw_bounding_box_fpu()
254 for (i = 0; i < clk_table->num_entries; i++) { in dcn35_update_bw_bounding_box_fpu()
259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
264 if (clk_table->num_entries == 1) { in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c635 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table; in smu_v14_0_1_get_dpm_freq_by_index() local
637 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
642 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
644 *freq = clk_table->SocClocks[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
647 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
649 *freq = clk_table->VClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
652 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
654 *freq = clk_table->DClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
657 if (dpm_level >= clk_table->Vcn1ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
659 *freq = clk_table->VClocks1[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
[all …]
/linux/drivers/clk/mmp/
H A Dclk.c13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
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H A Dclk-pll.c168 unit->clk_table[clks[i].id] = clk; in mmp_register_pll_clks()
H A Dclk.h134 struct clk **clk_table; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_processpptables.c571 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
576 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
581 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
584 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
586 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
590 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
643 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_gfxclk_voltage_dependency_table()
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
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H A Dprocess_pptables_v1_0.c313 struct phm_clock_array **clk_table, in get_valid_clk() argument
337 *clk_table = table; in get_valid_clk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c98 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
151 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
156 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
372 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
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/linux/drivers/clk/hisilicon/
H A Dclk.c31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c477 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
577 .clk_table = {
664 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
666 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
671 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/clk/axis/
H A Dclk-artpec6.c20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
/linux/drivers/acpi/pmic/
H A Dtps68470_pmic.c168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
/linux/drivers/clk/rockchip/
H A Dclk.c362 struct clk **clk_table; in rockchip_clk_init_base() local
372 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in rockchip_clk_init_base()
373 if (!clk_table) in rockchip_clk_init_base()
377 clk_table[i] = default_clk_val; in rockchip_clk_init_base()
380 ctx->clk_data.clks = clk_table; in rockchip_clk_init_base()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h266 struct clk_limit_table clk_table; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c62 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
63 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
67 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
76 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
1381 …et_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_t… in dcn401_prepare_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c5787 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) { in dc_enable_dcmode_clk_limit()
5788 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM) in dc_enable_dcmode_clk_limit()
5789 maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz; in dc_enable_dcmode_clk_limit()