| /linux/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 74 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
89 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
118 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
134 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
137 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
141 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
147 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
150 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
153 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
607 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
610 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
611 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
612 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
613 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
614 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
617 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu() local
278 ASSERT(clk_table->num_entries); in dcn351_update_bw_bounding_box_fpu()
281 for (i = 0; i < clk_table->num_entries; ++i) { in dcn351_update_bw_bounding_box_fpu()
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn351_update_bw_bounding_box_fpu()
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn351_update_bw_bounding_box_fpu()
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn351_update_bw_bounding_box_fpu()
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn351_update_bw_bounding_box_fpu()
288 for (i = 0; i < clk_table->num_entries; i++) { in dcn351_update_bw_bounding_box_fpu()
293 clk_table->entries[i].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()
298 if (clk_table->num_entries == 1) { in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu() local
244 ASSERT(clk_table->num_entries); in dcn35_update_bw_bounding_box_fpu()
247 for (i = 0; i < clk_table->num_entries; ++i) { in dcn35_update_bw_bounding_box_fpu()
248 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn35_update_bw_bounding_box_fpu()
249 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn35_update_bw_bounding_box_fpu()
250 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn35_update_bw_bounding_box_fpu()
251 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn35_update_bw_bounding_box_fpu()
254 for (i = 0; i < clk_table->num_entries; i++) { in dcn35_update_bw_bounding_box_fpu()
259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
264 if (clk_table->num_entries == 1) { in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 641 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table; in smu_v14_0_1_get_dpm_freq_by_index() local
643 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
648 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
650 *freq = clk_table->SocClocks[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
653 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
655 *freq = clk_table->VClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
658 if (dpm_level >= clk_table->Vcn0ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
660 *freq = clk_table->DClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
663 if (dpm_level >= clk_table->Vcn1ClkLevelsEnabled) in smu_v14_0_1_get_dpm_freq_by_index()
665 *freq = clk_table->VClocks1[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 757 .clk_table = {
887 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges()
890 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
1023 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
1083 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn35_clk_mgr_helper_populate_bw_params()
1084 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn35_clk_mgr_helper_populate_bw_params()
1087 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1088 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1089 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1092 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux/drivers/clk/mmp/ |
| H A D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kzalloc_objs(struct clk *, nr_clks); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_processpptables.c | 571 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
576 clk_table = kzalloc_flex(*clk_table, entries, in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
581 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
584 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
586 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
590 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
643 clk_table = kzalloc_flex(*clk_table, entries, in get_gfxclk_voltage_dependency_table()
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
178 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn401_init_single_clock()
185 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 635 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_level_count() local
639 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
642 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
645 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
648 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
651 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
665 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_freq_by_index() local
667 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
672 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
674 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
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| H A D | smu_v13_0_4_ppt.c | 434 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_4_get_dpm_freq_by_index() local
436 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
451 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
453 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
457 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
459 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
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| H A D | yellow_carp_ppt.c | 769 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_level_count() local
773 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
776 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
779 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
782 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
785 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
799 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_freq_by_index() local
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
806 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
808 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 98 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
151 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
156 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
372 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu15/ |
| H A D | smu_v15_0_0_ppt.c | 719 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v15_0_0_get_dpm_freq_by_index() local
721 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_0_get_dpm_freq_by_index()
726 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
728 *freq = clk_table->SocClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
731 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
733 *freq = clk_table->VClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
736 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
738 *freq = clk_table->DClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
742 if (dpm_level >= clk_table->NumMemPstatesEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
744 *freq = clk_table->MemPstateTable[dpm_level].MemClk; in smu_v15_0_0_get_dpm_freq_by_index()
[all …]
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| /linux/drivers/clk/hisilicon/ |
| H A D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kzalloc_objs(*clk_table, nr_clks); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
198 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn32_init_clocks()
205 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
213 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn32_init_clocks()
223 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn32_init_clocks()
238 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
240 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
244 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) in dcn32_init_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 47 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in get_minimum_clocks_for_latency()
68 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
73 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
77 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()
116 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
120 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
149 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
153 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()
190 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_idle_minimums()
597 …n_clocks.dcn4x.active.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->soc_bb->clk… in clamp_uclk_to_max()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 477 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
577 .clk_table = {
664 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
666 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
671 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 526 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in vangogh_get_dpm_clk_limited() local
528 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
533 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
535 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
538 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
540 *freq = clk_table->VcnClocks[dpm_level].vclk; in vangogh_get_dpm_clk_limited()
543 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
545 *freq = clk_table->VcnClocks[dpm_level].dclk; in vangogh_get_dpm_clk_limited()
549 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
551 *freq = clk_table->DfPstateTable[dpm_level].memclk; in vangogh_get_dpm_clk_limited()
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| /linux/drivers/clk/axis/ |
| H A D | clk-artpec6.c | 20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2122 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2125 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2126 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2127 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2128 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2129 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2130 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2131 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2132 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2155 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()
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| /linux/drivers/acpi/pmic/ |
| H A D | tps68470_pmic.c | 168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
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| /linux/sound/soc/samsung/ |
| H A D | i2s.c | 123 struct clk *clk_table[3]; member
814 rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC]; in i2s_hw_params()
1262 if (!IS_ERR(priv->clk_table[i])) in i2s_unregister_clocks()
1263 clk_unregister(priv->clk_table[i]); in i2s_unregister_clocks()
1311 priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev, in i2s_register_clock_provider()
1318 priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev, in i2s_register_clock_provider()
1328 priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, in i2s_register_clock_provider()
1335 priv->clk_data.clks = priv->clk_table; in i2s_register_clock_provider()
1545 priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]); in samsung_i2s_probe()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 198 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_get_dpm_clk_limited() local
200 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
207 *freq = clk_table->SocClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
213 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
218 *freq = clk_table->DcfClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
223 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
228 *freq = clk_table->VClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
233 *freq = clk_table->DClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk.c | 362 struct clk **clk_table; in rockchip_clk_init_base() local
372 clk_table = kzalloc_objs(struct clk *, nr_clks); in rockchip_clk_init_base()
373 if (!clk_table) in rockchip_clk_init_base()
377 clk_table[i] = default_clk_val; in rockchip_clk_init_base()
380 ctx->clk_data.clks = clk_table; in rockchip_clk_init_base()
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