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Searched refs:clk_table (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c73 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
88 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
117 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
128 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
133 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
136 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
140 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
146 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
149 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
152 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
H A Dclk-exynos-audss.c130 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
152 clk_table = clk_data->hws; in exynos_audss_clk_probe()
183 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
194 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
199 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", in exynos_audss_clk_probe()
203 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
207 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", in exynos_audss_clk_probe()
211 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
215 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
219 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c408 .clk_table = {
522 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn314_build_watermark_ranges()
525 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
635 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
677 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn314_clk_mgr_helper_populate_bw_params()
678 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()
681 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
682 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
683 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
686 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/clk/mmp/
H A Dclk.c13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kzalloc_objs(struct clk *, nr_clks); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
H A Dclk-pll.c168 unit->clk_table[clks[i].id] = clk; in mmp_register_pll_clks()
H A Dclk.h134 struct clk **clk_table; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c776 .clk_table = {
908 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn35_build_watermark_ranges()
911 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
1044 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
1105 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn35_clk_mgr_helper_populate_bw_params()
1106 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[entry_idx]) in dcn35_clk_mgr_helper_populate_bw_params()
1109 bw_params->clk_table.entries[entry_idx].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1110 …bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d1… in dcn35_clk_mgr_helper_populate_bw_params()
1111 bw_params->clk_table.entries[entry_idx].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1114 …bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemCl… in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c799 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v15_0_0_get_dpm_freq_by_index() local
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_0_get_dpm_freq_by_index()
806 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
808 *freq = clk_table->SocClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
811 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
813 *freq = clk_table->VClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
816 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
818 *freq = clk_table->DClocks[dpm_level]; in smu_v15_0_0_get_dpm_freq_by_index()
822 if (dpm_level >= clk_table->NumMemPstatesEnabled) in smu_v15_0_0_get_dpm_freq_by_index()
824 *freq = clk_table->MemPstateTable[dpm_level].MemClk; in smu_v15_0_0_get_dpm_freq_by_index()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c635 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_level_count() local
639 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
642 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
645 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
648 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
651 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
665 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_freq_by_index() local
667 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
672 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
674 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
H A Dsmu_v13_0_4_ppt.c434 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_4_get_dpm_freq_by_index() local
436 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
451 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
453 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
457 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
459 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
H A Dyellow_carp_ppt.c769 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_level_count() local
773 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
776 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
779 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
782 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
785 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
799 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_freq_by_index() local
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
806 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
808 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk.c31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kzalloc_objs(*clk_table, nr_clks); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c129 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
133 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
137 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
141 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
145 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
152 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
156 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
319 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn60_build_update_display_clocks_sequence()
342 (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ in dcn60_build_update_display_clocks_sequence()
343 clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels - 1].dtbclk_mhz; in dcn60_build_update_display_clocks_sequence()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c342 .clk_table = {
451 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn31_build_watermark_ranges()
454 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
591 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
602 for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
603 bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn31_clk_mgr_helper_populate_bw_params()
604 bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
605 bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].Voltage; in dcn31_clk_mgr_helper_populate_bw_params()
608 bw_params->clk_table.entries[entry_idx].wck_ratio = 2; in dcn31_clk_mgr_helper_populate_bw_params()
611 bw_params->clk_table.entries[entry_idx].wck_ratio = 4; in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/clk/cix/
H A Dclk-sky1-audss.c968 struct clk_hw **clk_table; in sky1_audss_clk_probe() local
989 clk_table = priv->clk_data->hws; in sky1_audss_clk_probe()
1043 clk_table[CLK_AUD_CLK4_DIV2] = in sky1_audss_clk_probe()
1049 if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV2])) { in sky1_audss_clk_probe()
1050 ret = PTR_ERR(clk_table[CLK_AUD_CLK4_DIV2]); in sky1_audss_clk_probe()
1055 clk_table[CLK_AUD_CLK4_DIV4] = in sky1_audss_clk_probe()
1061 if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV4])) { in sky1_audss_clk_probe()
1062 ret = PTR_ERR(clk_table[CLK_AUD_CLK4_DIV4]); in sky1_audss_clk_probe()
1068 clk_table[CLK_AUD_CLK5_DIV2] = in sky1_audss_clk_probe()
1074 if (IS_ERR(clk_table[CLK_AUD_CLK5_DIV2])) { in sky1_audss_clk_probe()
[all …]
/linux/drivers/clk/axis/
H A Dclk-artpec6.c20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
/linux/drivers/acpi/pmic/
H A Dtps68470_pmic.c168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2287 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2290 if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2291 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2292 if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2293 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2294 if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2295 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2296 if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2297 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2320 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()
[all …]
/linux/sound/soc/samsung/
H A Di2s.c124 struct clk *clk_table[3];
805 rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC]; in i2s_hw_params()
1253 if (!IS_ERR(priv->clk_table[i])) in i2s_runtime_resume()
1254 clk_unregister(priv->clk_table[i]); in i2s_runtime_resume()
1302 priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev, in i2s_register_clock_provider()
1309 priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev, in i2s_register_clock_provider()
1319 priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, in i2s_register_clock_provider()
1326 priv->clk_data.clks = priv->clk_table; in i2s_register_clock_provider()
1536 priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]); in samsung_i2s_probe()
123 struct clk *clk_table[3]; global() member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c58 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn50_initialize_min_clocks()
59 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn50_initialize_min_clocks()
60 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn50_initialize_min_clocks()
61 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn50_initialize_min_clocks()
63 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn50_initialize_min_clocks()
73 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn50_initialize_min_clocks()
/linux/drivers/clk/rockchip/
H A Dclk.c362 struct clk **clk_table; in rockchip_clk_init_base() local
372 clk_table = kzalloc_objs(struct clk *, nr_clks); in rockchip_clk_init_base()
373 if (!clk_table) in rockchip_clk_init_base()
377 clk_table[i] = default_clk_val; in rockchip_clk_init_base()
380 ctx->clk_data.clks = clk_table; in rockchip_clk_init_base()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.h29 …tive_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table);
H A Ddml2_core_utils.c534 …ctive_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table) in dml2_core_utils_get_active_min_uclk_dpm_index() argument
539 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
540 …DML_LOG_VERBOSE("DML::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk… in dml2_core_utils_get_active_min_uclk_dpm_index()
542 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/
H A Ddcn60_resource.c1903 …for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk… in dcn60_get_power_profile()
1904 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || in dcn60_get_power_profile()
1905 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn60_get_power_profile()
1907 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn60_get_power_profile()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1946 …for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk… in dcn401_get_power_profile()
1947 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || in dcn401_get_power_profile()
1948 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()
1950 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()

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