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Searched refs:clk_regs (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drv740_dpm.c124 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
125 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
126 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
127 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
128 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
190 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; in rv740_populate_mclk_value()
191 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv740_populate_mclk_value()
192 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; in rv740_populate_mclk_value()
193 u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv740_populate_mclk_value()
194 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv740_populate_mclk_value()
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H A Drv730_dpm.c43 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; in rv730_populate_sclk_value()
44 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; in rv730_populate_sclk_value()
45 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; in rv730_populate_sclk_value()
46 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; in rv730_populate_sclk_value()
47 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; in rv730_populate_sclk_value()
121 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; in rv730_populate_mclk_value()
122 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; in rv730_populate_mclk_value()
123 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; in rv730_populate_mclk_value()
124 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; in rv730_populate_mclk_value()
125 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; in rv730_populate_mclk_value()
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H A Drv770_dpm.c394 pi->clk_regs.rv770.mpll_ad_func_cntl; in rv770_populate_mclk_value()
396 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv770_populate_mclk_value()
398 pi->clk_regs.rv770.mpll_dq_func_cntl; in rv770_populate_mclk_value()
400 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv770_populate_mclk_value()
402 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv770_populate_mclk_value()
403 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; in rv770_populate_mclk_value()
492 pi->clk_regs.rv770.cg_spll_func_cntl; in rv770_populate_sclk_value()
494 pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv770_populate_sclk_value()
496 pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv770_populate_sclk_value()
498 pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv770_populate_sclk_value()
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H A Dcypress_dpm.c480 pi->clk_regs.rv770.mpll_ad_func_cntl; in cypress_populate_mclk_value()
482 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in cypress_populate_mclk_value()
484 pi->clk_regs.rv770.mpll_dq_func_cntl; in cypress_populate_mclk_value()
486 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in cypress_populate_mclk_value()
488 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in cypress_populate_mclk_value()
490 pi->clk_regs.rv770.dll_cntl; in cypress_populate_mclk_value()
491 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; in cypress_populate_mclk_value()
492 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; in cypress_populate_mclk_value()
1247 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); in cypress_populate_smc_initial_state()
1249 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); in cypress_populate_smc_initial_state()
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H A Drv770_dpm.h96 union r7xx_clock_registers clk_regs; member
/linux/drivers/clk/pxa/
H A Dclk-pxa27x.c56 static void __iomem *clk_regs; variable
105 unsigned long ccsr = readl(clk_regs + CCSR); in pxa27x_is_ppll_disabled()
207 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_cpll_get_rate()
241 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa27x_cpll_set_rate()
252 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_rate()
253 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_lcd_base_get_rate()
274 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_parent()
303 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_core_get_parent()
340 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_run_get_rate()
363 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_rate()
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H A Dclk-pxa3xx.c125 static void __iomem *clk_regs; variable
162 u32 accr = readl(clk_regs + ACCR); in pxa3xx_clk_update_accr()
167 writel(accr, clk_regs + ACCR); in pxa3xx_clk_update_accr()
171 while ((readl(clk_regs + ACSR) & mask) != (accr & mask)) in pxa3xx_clk_update_accr()
180 ac97_div = readl(clk_regs + AC97_DIV); in clk_pxa3xx_ac97_get_rate()
197 unsigned long acsr = readl(clk_regs + ACSR); in clk_pxa3xx_smemc_get_rate()
208 unsigned long acsr = readl(clk_regs + ACSR); in pxa3xx_is_ring_osc_forced()
288 unsigned long acsr = readl(clk_regs + ACSR); in clk_pxa3xx_system_bus_get_rate()
335 unsigned long acsr = readl(clk_regs + ACSR); in clk_pxa3xx_run_get_rate()
351 unsigned long acsr = readl(clk_regs + ACSR); in clk_pxa3xx_cpll_get_rate()
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H A Dclk-pxa25x.c44 static void __iomem *clk_regs; variable
103 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_memory_get_rate()
207 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_run_get_rate()
218 unsigned long clkcfg, cccr = readl(clk_regs + CCCR); in clk_pxa25x_cpll_get_rate()
250 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa25x_cpll_set_rate()
329 clk_regs = regs; in pxa25x_clocks_init()
332 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs); in pxa25x_clocks_init()
H A Dclk-pxa.c100 int nb_clks, void __iomem *clk_regs) in clk_pxa_cken_init() argument
114 pxa_clk->gate.reg = clk_regs + clks[i].cken_reg; in clk_pxa_cken_init()
H A Dclk-pxa.h152 int nb_clks, void __iomem *clk_regs);
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c74 void __iomem *clk_regs; member
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
170 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
260 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
268 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
501 tegra->clk_regs = base; in tegra124_clk_register_emc()
/linux/drivers/clk/samsung/
H A Dclk-exynosautov920.c1001 .clk_regs = top_clk_regs,
1129 .clk_regs = cpucl0_clk_regs,
1231 .clk_regs = cpucl1_clk_regs,
1333 .clk_regs = cpucl2_clk_regs,
1482 .clk_regs = peric0_clk_regs,
1622 .clk_regs = peric1_clk_regs,
1676 .clk_regs = misc_clk_regs,
1712 .clk_regs = hsi0_clk_regs,
1753 .clk_regs = hsi1_clk_regs,
1821 .clk_regs = hsi2_clk_regs,
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H A Dclk-artpec8.c373 .clk_regs = cmu_cmu_clk_regs,
409 .clk_regs = cmu_bus_clk_regs,
445 .clk_regs = cmu_core_clk_regs,
553 .clk_regs = cmu_cpucl_clk_regs,
783 .clk_regs = cmu_fsys_clk_regs,
833 .clk_regs = cmu_imem_clk_regs,
987 .clk_regs = cmu_peri_clk_regs,
H A Dclk-exynos-arm64.c76 const unsigned long *reg_offs = cmu->clk_regs; in exynos_arm64_init_clocks()
145 data->clk_save = samsung_clk_alloc_reg_dump(cmu->clk_regs, in exynos_arm64_cmu_prepare_pm()
H A Dclk-fsd.c313 .clk_regs = cmu_clk_regs,
678 .clk_regs = peric_clk_regs,
977 .clk_regs = fsys0_clk_regs,
1149 .clk_regs = fsys1_clk_regs,
1426 .clk_regs = imem_clk_regs,
1551 .clk_regs = mfc_clk_regs,
1755 .clk_regs = cam_csi_clk_regs,
H A Dclk.c380 if (cmu->clk_regs) in samsung_cmu_register_one()
382 cmu->clk_regs, cmu->nr_clk_regs, in samsung_cmu_register_one()
H A Dclk-exynos990.c1172 .clk_regs = top_clk_regs,
1351 .clk_regs = hsi0_clk_regs,
1886 .clk_regs = peric0_clk_regs,
2495 .clk_regs = peric1_clk_regs,
2663 .clk_regs = peris_clk_regs,