Searched refs:clk_pol (Results 1 – 11 of 11) sorted by relevance
45 unsigned int clk_pol:1; member
443 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT; in omap3isp_configure_bridge()2037 buscfg->bus.parallel.clk_pol = in isp_parse_of_parallel_endpoint()
27 int clk_pol; member
462 u8 clk_pol; member
518 u8 serial, u8 clk_pol, u8 clk_gated) in lgs8gxx_set_mpeg_mode() argument530 t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL; in lgs8gxx_set_mpeg_mode()
968 stv0367ter_set_clk_pol(state, state->config->clk_pol); in stv0367ter_init()2277 switch (state->config->clk_pol) { in stv0367cab_init()
299 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags & in ipu_crtc_mode_set_nofb()
39 unsigned clk_pol:1; /* true = rising edge */ member
368 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,375 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
617 if (sig->clk_pol) in ipu_di_init_sync_panel()
929 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,936 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,