Searched refs:clk_period_ps (Results 1 – 3 of 3) sorted by relevance
1040 u32 clk_period_ps) in create_timings_aligned() argument1045 if (clk_period_ps == 0) in create_timings_aligned()1052 val = dmc->timings->tRFC / clk_period_ps; in create_timings_aligned()1053 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; in create_timings_aligned()1058 val = dmc->timings->tRRD / clk_period_ps; in create_timings_aligned()1059 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; in create_timings_aligned()1064 val = dmc->timings->tRPab / clk_period_ps; in create_timings_aligned()1065 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; in create_timings_aligned()1070 val = dmc->timings->tRCD / clk_period_ps; in create_timings_aligned()1071 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; in create_timings_aligned()[all …]
168 u64 clk_period_ps; in aspeed_sdhci_phase_to_tap() local185 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); in aspeed_sdhci_phase_to_tap()186 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); in aspeed_sdhci_phase_to_tap()
618 u32 clk_period_ps = 1600; /* 625Mhz for now */ in sparx5_port_fwd_urg() local640 return urg / clk_period_ps - 1; in sparx5_port_fwd_urg()