| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 99 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_exit_optimized_pwr_state() argument
117 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; in clk_mgr_exit_optimized_pwr_state()
125 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state() argument
139 &clk_mgr->psr_allow_active_cache, false, false, NULL); in clk_mgr_optimize_pwr_state()
141 &clk_mgr->psr_allow_active_cache, false, false, NULL); in clk_mgr_optimize_pwr_state()
150 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create()
158 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); in dc_clk_mgr_create() local
160 if (clk_mgr == NULL) { in dc_clk_mgr_create()
164 dce_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
165 return &clk_mgr->base; in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 85 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn31_smu_wait_for_response() argument
103 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param() argument
109 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
127 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
147 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version() argument
150 clk_mgr, in dcn31_smu_get_smu_version()
156 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk() argument
160 if (!clk_mgr->smu_present) in dcn31_smu_set_dispclk()
165 clk_mgr, in dcn31_smu_set_dispclk()
172 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk() argument
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| H A D | dcn31_clk_mgr.c | 58 clk_mgr->base.base.ctx->logger
73 #define TO_CLK_MGR_DCN31(clk_mgr)\ argument
74 container_of(clk_mgr, struct clk_mgr_dcn31, base)
117 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disab… in dcn31_disable_otg_wa()
137 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, in dcn31_update_clocks()
142 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_update_clocks() local
160 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn31_update_clocks()
165 dcn31_smu_set_dtbclk(clk_mgr, false); in dcn31_update_clocks()
177 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
185 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); in dcn31_update_clocks()
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| H A D | dcn31_smu.h | 254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| H A D | dcn31_clk_mgr.h | 44 void dcn31_init_clocks(struct clk_mgr *clk_mgr);
45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
50 struct clk_mgr_dcn31 *clk_mgr,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 100 static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn316_smu_wait_for_response() argument
119 struct clk_mgr_internal *clk_mgr, in dcn316_smu_send_msg_with_param() argument
124 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
142 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
152 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_smu_version() argument
155 clk_mgr, in dcn316_smu_get_smu_version()
161 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn316_smu_set_dispclk() argument
165 if (!clk_mgr->smu_present) in dcn316_smu_set_dispclk()
170 clk_mgr, in dcn316_smu_set_dispclk()
177 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn316_smu_set_hard_min_dcfclk() argument
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| H A D | dcn316_smu.h | 122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 101 static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn314_smu_wait_for_response() argument
119 static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn314_smu_send_msg_with_param() argument
125 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
143 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
166 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn314_smu_get_smu_version() argument
169 clk_mgr, in dcn314_smu_get_smu_version()
175 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn314_smu_set_dispclk() argument
179 if (!clk_mgr->smu_present) in dcn314_smu_set_dispclk()
184 clk_mgr, in dcn314_smu_set_dispclk()
191 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn314_smu_set_dprefclk() argument
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| H A D | dcn314_clk_mgr.c | 79 clk_mgr->base.base.ctx->logger
107 #define TO_CLK_MGR_DCN314(clk_mgr)\ argument
108 container_of(clk_mgr, struct clk_mgr_dcn314, base)
151 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn314_disable_otg_wa()
177 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) in dcn314_is_spll_ssc_enabled()
179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_is_spll_ssc_enabled() local
187 void dcn314_init_clocks(struct clk_mgr *clk_mgr) in dcn314_init_clocks() argument
189 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); in dcn314_init_clocks()
190 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn314_init_clocks()
192 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn314_init_clocks()
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| H A D | dcn314_smu.h | 93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
96 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
97 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 43 (clk_mgr->regs->reg)
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
61 clk_mgr->base.ctx
75 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) in dcn201_init_clocks() argument
77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
78 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
79 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
80 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
81 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 80 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn301_smu_wait_for_response() argument
98 static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param() argument
104 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
122 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
133 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version() argument
135 int smu_version = dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_get_smu_version()
145 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk() argument
153 clk_mgr, in dcn301_smu_set_dispclk()
160 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk() argument
164 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
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| H A D | dcn301_smu.h | 150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
154 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 52 clk_mgr->base.base.ctx->logger
125 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
128 (clk_mgr->regs->reg)
153 #define TO_CLK_MGR_DCN35(clk_mgr)\ argument
154 container_of(clk_mgr, struct clk_mgr_dcn35, base)
189 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_disable_otg_wa()
256 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, in dcn35_update_clocks_update_dtb_dto() argument
260 struct dccg *dccg = clk_mgr->dccg; in dcn35_update_clocks_update_dtb_dto()
264 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dtb_dto()
288 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn35_update_clocks_update_dtb_dto()
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| H A D | dcn35_smu.h | 196 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
197 int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
198 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
199 int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
200 int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
201 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
202 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
203 void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
204 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
205 void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| H A D | dcn35_clk_mgr.h | 51 void dcn35_init_clocks(struct clk_mgr *clk_mgr);
52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
57 struct clk_mgr_dcn35 *clk_mgr,
64 struct clk_mgr_dcn35 *clk_mgr,
68 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/ |
| H A D | dcn60_clk_mgr.c | 91 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
94 (clk_mgr->regs->reg)
119 #define TO_DCN60_CLK_MGR(clk_mgr)\ argument
120 container_of(clk_mgr, struct dcn60_clk_mgr, base)
122 static bool dcn60_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk) in dcn60_is_ppclk_dpm_enabled() argument
129 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
133 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
137 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
141 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
145 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.h | 114 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
115 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
116 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
117 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
120 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
121 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
122 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
123 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
33 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
39 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
42 struct clk_mgr_internal *clk_mgr,
48 void dcn2_get_clock(struct clk_mgr *clk_mgr,
53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.h | 39 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
40 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
41 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
42 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
43 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
44 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
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| H A D | dcn32_clk_mgr.h | 28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
31 struct clk_mgr_internal *clk_mgr,
35 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
38 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30m_clk_mgr_smu_msg.c | 53 static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_wait_for_response() argument
76 static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_send_msg_with_param() argument
81 dcn30m_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30m_smu_send_msg_with_param()
92 result = dcn30m_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30m_smu_send_msg_with_param()
108 uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set) in dcn30m_smu_set_smart_mux_switch() argument
114 dcn30m_smu_send_msg_with_param(clk_mgr, in dcn30m_smu_set_smart_mux_switch()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.h | 32 struct clk_mgr_internal *clk_mgr);
35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
36 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
37 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 58 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn50_initialize_min_clocks()
59 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn50_initialize_min_clocks()
60 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn50_initialize_min_clocks()
61 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn50_initialize_min_clocks()
63 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn50_initialize_min_clocks()
70 if (dc->clk_mgr->funcs->get_dispclk_from_dentist) in dcn50_initialize_min_clocks()
71 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); in dcn50_initialize_min_clocks()
73 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn50_initialize_min_clocks()
77 dc->clk_mgr->funcs->update_clocks( in dcn50_initialize_min_clocks()
78 dc->clk_mgr, in dcn50_initialize_min_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 152 if (state->clk_mgr && in dcn60_build_audio_output()
157 state->clk_mgr->funcs->get_dp_ref_clk_frequency( in dcn60_build_audio_output()
158 state->clk_mgr); in dcn60_build_audio_output()
363 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn60_setup_audio_dto()
417 dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn60_setup_audio_dto()
552 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { in dcn60_init_hw()
553 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn60_init_hw()
556 dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present && in dcn60_init_hw()
557 dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr); in dcn60_init_hw()
646 if (dc->clk_mgr && dc->clk_mgr->funcs) in dcn60_init_hw()
[all …]
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