| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 98 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_exit_optimized_pwr_state()
116 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; in clk_mgr_exit_optimized_pwr_state()
124 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state()
138 &clk_mgr->psr_allow_active_cache, false, false, NULL); in clk_mgr_optimize_pwr_state()
140 &clk_mgr->psr_allow_active_cache, false, false, NULL); in clk_mgr_optimize_pwr_state()
149 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create()
157 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); in dc_clk_mgr_create()
97 clk_mgr_exit_optimized_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr) clk_mgr_exit_optimized_pwr_state() argument
123 clk_mgr_optimize_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr) clk_mgr_optimize_pwr_state() argument
156 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
166 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
176 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
200 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
214 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
242 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
269 struct clk_mgr_vgh *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
281 struct clk_mgr_dcn31 *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
293 struct clk_mgr_dcn315 *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
305 struct clk_mgr_dcn316 *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
317 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
328 struct clk_mgr_dcn314 *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
341 struct clk_mgr_dcn35 *clk_mgr = kzalloc_obj(*clk_mgr); dc_clk_mgr_create() local
357 struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg); dc_clk_mgr_create() local
368 struct clk_mgr_dcn42 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); dc_clk_mgr_create() local
390 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dc_destroy_clk_mgr() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 85 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn31_smu_wait_for_response() argument
103 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param() argument
109 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
127 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
147 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version() argument
150 clk_mgr, in dcn31_smu_get_smu_version()
156 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk() argument
160 if (!clk_mgr->smu_present) in dcn31_smu_set_dispclk()
165 clk_mgr, in dcn31_smu_set_dispclk()
172 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk() argument
[all …]
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| H A D | dcn31_smu.h | 254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
[all …]
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| H A D | dcn31_clk_mgr.h | 44 void dcn31_init_clocks(struct clk_mgr *clk_mgr);
45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
50 struct clk_mgr_dcn31 *clk_mgr,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 100 static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn316_smu_wait_for_response() argument
119 struct clk_mgr_internal *clk_mgr, in dcn316_smu_send_msg_with_param() argument
124 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
142 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
152 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_smu_version() argument
155 clk_mgr, in dcn316_smu_get_smu_version()
161 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn316_smu_set_dispclk() argument
165 if (!clk_mgr->smu_present) in dcn316_smu_set_dispclk()
170 clk_mgr, in dcn316_smu_set_dispclk()
177 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn316_smu_set_hard_min_dcfclk() argument
[all …]
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| H A D | dcn316_smu.h | 122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 101 static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn314_smu_wait_for_response() argument
119 static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn314_smu_send_msg_with_param() argument
125 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
143 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
166 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn314_smu_get_smu_version() argument
169 clk_mgr, in dcn314_smu_get_smu_version()
175 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn314_smu_set_dispclk() argument
179 if (!clk_mgr->smu_present) in dcn314_smu_set_dispclk()
184 clk_mgr, in dcn314_smu_set_dispclk()
191 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn314_smu_set_dprefclk() argument
[all …]
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| H A D | dcn314_smu.h | 93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
96 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
97 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 (clk_mgr->regs->reg)
104 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn20_update_clocks_update_dpp_dto() argument
109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr in dcn20_update_clocks_update_dpp_dto()
127 dcn20_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context) dcn20_update_clocks_update_dentist() argument
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn2_update_clocks() local
343 dcn2_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower) dcn2_update_clocks_fpga() argument
403 dcn2_init_clocks(struct clk_mgr * clk_mgr) dcn2_init_clocks() argument
413 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn2_enable_pme_wa() local
427 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn2_read_clocks_from_hw_dentist() local
449 dcn2_get_clock(struct clk_mgr * clk_mgr,struct dc_state * context,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg) dcn2_get_clock() argument
495 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn2_notify_link_rate_change() local
530 dcn20_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg) dcn20_clk_mgr_construct() argument
[all...] |
| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
33 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
39 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
42 struct clk_mgr_internal *clk_mgr,
48 void dcn2_get_clock(struct clk_mgr *clk_mgr,
53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 48 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
51 (clk_mgr->regs->reg)
114 static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock) in dcn42_get_clock_freq_from_clkip()
116 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn42_get_clock_freq_from_clkip() local
157 void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, in dcn42_update_clocks_update_dtb_dto() argument
161 (void)clk_mgr; in dcn42_update_clocks_update_dtb_dto()
167 void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn42_update_clocks_update_dpp_dto() argument
174 clk_mgr->dccg->ref_dppclk = clk_mgr in dcn42_update_clocks_update_dpp_dto()
216 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_update_clocks() local
367 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_enable_pme_wa() local
394 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_dump_clk_registers_internal() local
419 dcn42_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn42 * clk_mgr) dcn42_dump_clk_registers() argument
501 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_is_spll_ssc_enabled() local
513 init_clk_states(struct clk_mgr * clk_mgr) init_clk_states() argument
527 dcn42_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn42_smu_dpm_clks * smu_dpm_clks) dcn42_get_dpm_table_from_smu() argument
584 struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); dcn42_init_clocks() local
619 dcn42_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr) dcn42_read_ss_info_from_lut() argument
695 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_notify_wm_ranges() local
756 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_set_low_power_state() local
771 dcn42_init_clocks_fpga(struct clk_mgr * clk_mgr) dcn42_init_clocks_fpga() argument
777 dcn42_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower) dcn42_update_clocks_fpga() argument
841 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_get_max_clock_khz() local
871 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_get_dispclk_from_dentist() local
886 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); dcn42_is_smu_present() local
1035 dcn42_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn42 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg) dcn42_clk_mgr_construct() argument
1100 struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); dcn42_clk_mgr_destroy() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 43 (clk_mgr->regs->reg)
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
61 clk_mgr->base.ctx
75 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) in dcn201_init_clocks() argument
77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
78 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
79 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
80 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
81 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 34 static void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument
36 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
39 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in rv1_determine_dppclk_threshold() argument
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
44 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
74 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
86 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp() argument
92 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clock in ramp_up_dispclk_with_dpp()
191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); rv1_update_clocks() local
293 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); rv1_enable_pme_wa() local
316 rv1_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu) rv1_clk_mgr_construct() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 80 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn301_smu_wait_for_response() argument
98 static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param() argument
104 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
122 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
133 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version() argument
135 int smu_version = dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_get_smu_version()
145 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk() argument
153 clk_mgr, in dcn301_smu_set_dispclk()
160 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk() argument
164 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
[all …]
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| H A D | dcn301_smu.h | 150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
154 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr_smu_msg.h | 33 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
34 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);
35 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
36 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
37 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
38 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
39 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
40 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
41 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
42 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_
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| H A D | dcn30m_clk_mgr_smu_msg.c | 53 static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_wait_for_response() argument
76 static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn30m_smu_send_msg_with_param() argument
81 dcn30m_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30m_smu_send_msg_with_param()
92 result = dcn30m_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30m_smu_send_msg_with_param()
108 uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set) in dcn30m_smu_set_smart_mux_switch() argument
114 dcn30m_smu_send_msg_with_param(clk_mgr, in dcn30m_smu_set_smart_mux_switch()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.h | 196 int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
197 int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
198 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
199 int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
200 int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
201 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
202 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
203 void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
204 void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
205 void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| H A D | dcn35_clk_mgr.h | 51 void dcn35_init_clocks(struct clk_mgr *clk_mgr);
52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
57 struct clk_mgr_dcn35 *clk_mgr,
64 struct clk_mgr_dcn35 *clk_mgr,
68 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.h | 114 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
115 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
116 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
117 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
120 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
121 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
122 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
123 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 57 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
104 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) in dce112_set_clock()
107 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_clock()
108 struct dc *dc = clk_mgr->base.ctx->dc; in dce112_set_clock()
117 clk_mgr->base.dentist_vco_freq_khz / 62); in dce112_set_clock()
127 if (clk_mgr->dfs_bypass_disp_clk != actual_clock) in dce112_set_dispclk()
132 clk_mgr->dfs_bypass_disp_clk = actual_clock; in dce112_set_dispclk()
137 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dce112_set_dispclk()
140 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dispclk()
149 if (!((clk_mgr in dce112_set_dispclk()
124 dce112_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_clk_khz) dce112_set_dispclk() argument
165 dce112_set_dprefclk(struct clk_mgr_internal * clk_mgr) dce112_set_dprefclk() argument
225 dce112_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr) dce112_clk_mgr_construct() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| H A D | dce120_clk_mgr.c | 72 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce121_clock_patch_xgmi_ss_info()
116 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce12_update_clocks()
118 dce_clk_mgr_construct(ctx, clk_mgr); in dce12_update_clocks()
120 clk_mgr->base.dprefclk_khz = 600000; in dce12_update_clocks()
121 clk_mgr->base.funcs = &dce120_funcs;
124 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
126 dce120_clk_mgr_construct(ctx, clk_mgr);
127 clk_mgr->base.dprefclk_khz = 625000;
134 dce121_clock_patch_xgmi_ss_info(clk_mgr); in dce120_clk_mgr_construct()
128 dce120_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr) dce120_clk_mgr_construct() argument
140 dce121_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr) dce121_clk_mgr_construct() argument
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.h | 39 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
40 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
41 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
42 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
43 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
44 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.h | 34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
45 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
48 struct clk_mgr *clk_mgr_base,
52 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
186 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) in dcn32_build_wm_range_table_fpu() argument
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
194 uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
198 (uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
204 clk_mgr in dcn32_build_wm_range_table_fpu()
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