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Searched refs:clk_id (Results 1 – 25 of 185) sorted by relevance

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/linux/drivers/clk/zynqmp/
H A Dpll.c21 u32 clk_id; member
52 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode() local
57 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); in zynqmp_pll_get_mode()
75 u32 clk_id = clk->clk_id; in zynqmp_pll_set_mode() local
85 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); in zynqmp_pll_set_mode()
137 u32 clk_id = clk->clk_id; in zynqmp_pll_recalc_rate() local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
158 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); in zynqmp_pll_recalc_rate()
181 u32 clk_id = clk->clk_id; in zynqmp_pll_set_rate() local
197 ret = zynqmp_pm_clock_setdivider(clk_id, m); in zynqmp_pll_set_rate()
[all …]
H A Dclk-gate-zynqmp.c23 u32 clk_id; member
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable() local
41 ret = zynqmp_pm_clock_enable(clk_id); in zynqmp_clk_gate_enable()
45 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_enable()
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable() local
61 ret = zynqmp_pm_clock_disable(clk_id); in zynqmp_clk_gate_disable()
65 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_disable()
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled() local
81 ret = zynqmp_pm_clock_getstate(clk_id, &state); in zynqmp_clk_gate_is_enabled()
107 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, in zynqmp_clk_register_gate() argument
[all …]
H A Dclkc.c79 u32 clk_id; member
122 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
146 static inline int zynqmp_is_valid_clock(u32 clk_id) in zynqmp_is_valid_clock() argument
148 if (clk_id >= clock_max_idx) in zynqmp_is_valid_clock()
151 return clock[clk_id].valid; in zynqmp_is_valid_clock()
161 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
165 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_name()
167 strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
181 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) in zynqmp_get_clock_type() argument
185 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_type()
[all …]
H A Ddivider.c44 u32 clk_id; member
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate() local
89 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
126 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_determine_rate() local
134 ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); in zynqmp_clk_divider_determine_rate()
177 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate() local
194 ret = zynqmp_pm_clock_setdivider(clk_id, div); in zynqmp_clk_divider_set_rate()
222 static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) in zynqmp_clk_get_max_divisor() argument
229 qdata.arg1 = clk_id; in zynqmp_clk_get_max_divisor()
276 u32 clk_id, in zynqmp_clk_register_divider() argument
[all …]
H A Dclk-mux-zynqmp.c32 u32 clk_id; member
47 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_get_parent() local
51 ret = zynqmp_pm_clock_getparent(clk_id, &val); in zynqmp_clk_mux_get_parent()
77 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_set_parent() local
80 ret = zynqmp_pm_clock_setparent(clk_id, index); in zynqmp_clk_mux_set_parent()
131 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, in zynqmp_clk_register_mux() argument
157 mux->clk_id = clk_id; in zynqmp_clk_register_mux()
H A Dclk-zynqmp.h70 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
75 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
81 u32 clk_id,
86 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
92 u32 clk_id,
/linux/drivers/clk/keystone/
H A Dsci-clk.c54 u32 clk_id; member
79 clk->clk_id, enable_ssc, in sci_clk_prepare()
96 clk->clk_id); in sci_clk_unprepare()
100 clk->dev_id, clk->clk_id, ret); in sci_clk_unprepare()
117 clk->clk_id, &req_state, in sci_clk_is_prepared()
122 clk->dev_id, clk->clk_id, ret); in sci_clk_is_prepared()
145 clk->clk_id, &freq); in sci_clk_recalc_rate()
149 clk->dev_id, clk->clk_id, ret); in sci_clk_recalc_rate()
180 clk->clk_id, in sci_clk_determine_rate()
188 clk->dev_id, clk->clk_id, ret); in sci_clk_determine_rate()
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/linux/tools/testing/selftests/vDSO/
H A Dvdso_test_abi.c36 typedef long (*vdso_clock_gettime_t)(clockid_t clk_id, struct timespec *ts);
37 typedef long (*vdso_clock_gettime64_t)(clockid_t clk_id, struct vdso_timespec64 *ts);
38 typedef long (*vdso_clock_getres_t)(clockid_t clk_id, struct timespec *ts);
80 static void vdso_test_clock_gettime64(clockid_t clk_id) in vdso_test_clock_gettime64() argument
89 vdso_clock_name[clk_id]); in vdso_test_clock_gettime64()
94 long ret = VDSO_CALL(vdso_clock_gettime64, 2, clk_id, &ts); in vdso_test_clock_gettime64()
100 vdso_clock_name[clk_id]); in vdso_test_clock_gettime64()
103 vdso_clock_name[clk_id]); in vdso_test_clock_gettime64()
107 static void vdso_test_clock_gettime(clockid_t clk_id) in vdso_test_clock_gettime() argument
116 vdso_clock_name[clk_id]); in vdso_test_clock_gettime()
[all …]
/linux/drivers/firmware/arm_scmi/
H A Dclock.c148 __le32 clk_id; member
168 u32 clk_id, enum clk_state state,
172 u32 clk_id, enum scmi_clock_oem_config oem_type,
183 scmi_clock_domain_lookup(struct clock_info *ci, u32 clk_id) in scmi_clock_domain_lookup() argument
185 if (clk_id >= ci->num_clocks) in scmi_clock_domain_lookup()
188 return ci->clk + clk_id; in scmi_clock_domain_lookup()
229 u32 clk_id; member
239 msg->id = cpu_to_le32(p->clk_id); in iter_clk_possible_parents_prepare_message()
290 static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph, u32 clk_id, in scmi_clock_possible_parents() argument
300 .clk_id = clk_id, in scmi_clock_possible_parents()
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/linux/tools/testing/selftests/timens/
H A Dtimens.h64 static inline int _settime(clockid_t clk_id, time_t offset) in _settime() argument
69 if (clk_id == CLOCK_MONOTONIC_COARSE || clk_id == CLOCK_MONOTONIC_RAW) in _settime()
70 clk_id = CLOCK_MONOTONIC; in _settime()
72 len = snprintf(buf, sizeof(buf), "%d %ld 0", clk_id, offset); in _settime()
86 static inline int _gettime(clockid_t clk_id, struct timespec *res, bool raw_syscall) in _gettime() argument
91 if (clock_gettime(clk_id, res)) { in _gettime()
92 pr_perror("clock_gettime(%d)", (int)clk_id); in _gettime()
98 err = syscall(SYS_clock_gettime, clk_id, res); in _gettime()
100 pr_perror("syscall(SYS_clock_gettime(%d))", (int)clk_id); in _gettime()
/linux/drivers/pmdomain/mediatek/
H A Dmtk-scpsys.c81 enum clk_id { enum
129 enum clk_id clk_id[MAX_CLKS]; member
494 for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { in init_scp()
495 struct clk *c = clk[data->clk_id[j]]; in init_scp()
562 .clk_id = {CLK_NONE},
570 .clk_id = {CLK_MM},
580 .clk_id = {CLK_MFG},
589 .clk_id = {CLK_MM},
598 .clk_id = {CLK_MM},
606 .clk_id = {CLK_NONE},
[all …]
/linux/drivers/firmware/samsung/
H A Dexynos-acpm-dvfs.c36 static void acpm_dvfs_init_set_rate_cmd(u32 cmd[4], unsigned int clk_id, in acpm_dvfs_init_set_rate_cmd() argument
39 cmd[0] = FIELD_PREP(ACPM_DVFS_ID, clk_id); in acpm_dvfs_init_set_rate_cmd()
46 unsigned int acpm_chan_id, unsigned int clk_id, in acpm_dvfs_set_rate() argument
52 acpm_dvfs_init_set_rate_cmd(cmd, clk_id, rate); in acpm_dvfs_set_rate()
58 static void acpm_dvfs_init_get_rate_cmd(u32 cmd[4], unsigned int clk_id) in acpm_dvfs_init_get_rate_cmd() argument
60 cmd[0] = FIELD_PREP(ACPM_DVFS_ID, clk_id); in acpm_dvfs_init_get_rate_cmd()
66 unsigned int acpm_chan_id, unsigned int clk_id) in acpm_dvfs_get_rate() argument
72 acpm_dvfs_init_get_rate_cmd(cmd, clk_id); in acpm_dvfs_get_rate()
/linux/sound/soc/ti/
H A Domap-dmic.c279 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_fclk() argument
298 if (dmic->sysclk == clk_id) { in omap_dmic_select_fclk()
309 switch (clk_id) { in omap_dmic_select_fclk()
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
353 dmic->sysclk = clk_id; in omap_dmic_select_fclk()
363 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_outclk() argument
368 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) { in omap_dmic_select_outclk()
370 clk_id); in omap_dmic_select_outclk()
390 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, in omap_dmic_set_dai_sysclk() argument
396 return omap_dmic_select_fclk(dmic, clk_id, freq); in omap_dmic_set_dai_sysclk()
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/linux/drivers/clk/tegra/
H A Dclk-tegra-audio.c35 int clk_id; member
41 .clk_id = tegra_clk_ ## _name,\
66 int clk_id; member
77 .clk_id = tegra_clk_ ## _name ## _2x,\
181 dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks); in tegra_audio_clk_init()
207 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
231 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
H A Dclk.c262 for (; dup_list->clk_id < clk_max; dup_list++) { in tegra_init_dup_clks()
263 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
274 for (; tbl->clk_id < clk_max; tbl++) { in tegra_init_from_table()
275 clk = clks[tbl->clk_id]; in tegra_init_from_table()
278 __func__, PTR_ERR(clk), tbl->clk_id); in tegra_init_from_table()
373 struct clk ** __init tegra_lookup_dt_id(int clk_id, in tegra_lookup_dt_id() argument
376 if (tegra_clk[clk_id].present) in tegra_lookup_dt_id()
377 return &clks[tegra_clk[clk_id].dt_id]; in tegra_lookup_dt_id()
/linux/sound/soc/codecs/
H A Dadav80x.c538 int clk_id, int source, in adav80x_set_sysclk() argument
545 switch (clk_id) { in adav80x_set_sysclk()
558 if (adav80x->clk_src != clk_id) { in adav80x_set_sysclk()
561 adav80x->clk_src = clk_id; in adav80x_set_sysclk()
562 if (clk_id == ADAV80X_CLK_XTAL) in adav80x_set_sysclk()
563 clk_id = ADAV80X_CLK_XIN; in adav80x_set_sysclk()
565 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | in adav80x_set_sysclk()
566 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | in adav80x_set_sysclk()
567 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); in adav80x_set_sysclk()
568 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); in adav80x_set_sysclk()
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H A Dmc13783.c241 int clk_id, unsigned int freq, int dir, in mc13783_set_sysclk() argument
259 if (clk_id == MC13783_CLK_CLIB) in mc13783_set_sysclk()
270 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_dac() argument
272 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC); in mc13783_set_sysclk_dac()
276 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_codec() argument
278 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC); in mc13783_set_sysclk_codec()
282 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_sync() argument
286 ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC); in mc13783_set_sysclk_sync()
290 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC); in mc13783_set_sysclk_sync()
/linux/drivers/firmware/
H A Dti_sci.c952 u32 dev_id, u32 clk_id, in ti_sci_set_clock_state() argument
980 if (clk_id < 255) { in ti_sci_set_clock_state()
981 req->clk_id = clk_id; in ti_sci_set_clock_state()
983 req->clk_id = 255; in ti_sci_set_clock_state()
984 req->clk_id_32 = clk_id; in ti_sci_set_clock_state()
1017 u32 dev_id, u32 clk_id, in ti_sci_cmd_get_clock_state() argument
1048 if (clk_id < 255) { in ti_sci_cmd_get_clock_state()
1049 req->clk_id = clk_id; in ti_sci_cmd_get_clock_state()
1051 req->clk_id = 255; in ti_sci_cmd_get_clock_state()
1052 req->clk_id_32 = clk_id; in ti_sci_cmd_get_clock_state()
[all …]
H A Dti_sci.h306 u8 clk_id; member
332 u8 clk_id; member
375 u8 clk_id; member
397 u8 clk_id; member
435 u8 clk_id; member
486 u8 clk_id; member
545 u8 clk_id; member
566 u8 clk_id; member
/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.c107 static int q6prm_request_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_unvote_lpass_core_hw()
131 req->clock_id.clock_id = clk_id; in q6prm_request_lpass_clock()
139 static int q6prm_release_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_request_lpass_clock()
163 rel->clock_id.clock_id = clk_id; in q6prm_release_lpass_clock()
168 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_release_lpass_clock()
172 return q6prm_request_lpass_clock(dev, clk_id, clk_attr, clk_root, freq); in q6prm_release_lpass_clock()
174 return q6prm_release_lpass_clock(dev, clk_id, clk_attr, clk_root, freq); in q6prm_release_lpass_clock()
112 q6prm_request_lpass_clock(struct device * dev,int clk_id,int clk_attr,int clk_root,unsigned int freq) q6prm_request_lpass_clock() argument
149 q6prm_release_lpass_clock(struct device * dev,int clk_id,int clk_attr,int clk_root,unsigned int freq) q6prm_release_lpass_clock() argument
183 q6prm_set_lpass_clock(struct device * dev,int clk_id,int clk_attr,int clk_root,unsigned int freq) q6prm_set_lpass_clock() argument
H A Dq6dsp-lpass-clocks.h7 int clk_id; member
14 .clk_id = id, \
22 int (*lpass_set_clk)(struct device *dev, int clk_id, int attr,
/linux/tools/perf/util/
H A Dclockid.c55 static int get_clockid_res(clockid_t clk_id, u64 *res_ns) in get_clockid_res() argument
60 if (!clock_getres(clk_id, &res)) in get_clockid_res()
110 const char *clockid_name(clockid_t clk_id) in clockid_name() argument
115 if (cm->clockid == clk_id) in clockid_name()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c501 uint8_t clk_id, in smu_v11_0_atom_get_smu_clockinfo() argument
509 input.clk_id = clk_id; in smu_v11_0_atom_get_smu_clockinfo()
798 int clk_id; in smu_v11_0_get_max_sustainable_clock() local
804 clk_id = smu_cmn_to_asic_specific_index(smu, in smu_v11_0_get_max_sustainable_clock()
807 if (clk_id < 0) in smu_v11_0_get_max_sustainable_clock()
811 clk_id << 16, clock); in smu_v11_0_get_max_sustainable_clock()
822 clk_id << 16, clock); in smu_v11_0_get_max_sustainable_clock()
1718 int ret = 0, clk_id = 0; in smu_v11_0_get_dpm_ultimate_freq() local
1749 clk_id = smu_cmn_to_asic_specific_index(smu, in smu_v11_0_get_dpm_ultimate_freq()
1752 if (clk_id < 0) { in smu_v11_0_get_dpm_ultimate_freq()
[all …]
/linux/sound/soc/intel/boards/
H A Dsof_rt5682.c264 int pll_id, pll_source, pll_in, pll_out, clk_id, ret; in sof_rt5682_hw_params()
329 clk_id = RT5645_SCLK_S_MCLK; in sof_rt5682_hw_params()
332 clk_id = RT5682_SCLK_S_MCLK; in sof_rt5682_hw_params()
335 clk_id = RT5682S_SCLK_S_MCLK; in sof_rt5682_hw_params()
346 clk_id = RT5645_SCLK_S_PLL1; in sof_rt5682_hw_params()
350 clk_id = RT5682_SCLK_S_PLL1; in sof_rt5682_hw_params()
364 clk_id = RT5682S_SCLK_S_PLL1; in sof_rt5682_hw_params()
368 clk_id = RT5682S_SCLK_S_PLL2; in sof_rt5682_hw_params()
385 ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, in sof_rt5682_hw_params()
260 int pll_id, pll_source, pll_in, pll_out, clk_id, ret; sof_rt5682_hw_params() local
/linux/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c162 u8 clk_id; member
171 .clk_id = CLK_SRC_ ##_id, \
197 u8 clk_id; member
205 .clk_id = BASE_ ##_id ##_CLK, \
259 u8 clk_id; member
270 .clk_id = CLK_SRC_ ##_id, \
535 const char *name = clk_src_names[clk->clk_id]; in lpc18xx_cgu_register_div()
555 const char *name = clk_base_names[clk->clk_id]; in lpc18xx_register_base_clk()
582 const char *name = clk_src_names[clk->clk_id]; in lpc18xx_cgu_register_pll()

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