/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_phase.c | 35 parent_rate = clk_hw_get_rate(parent); in ccu_phase_get_phase() 45 grandparent_rate = clk_hw_get_rate(grandparent); in ccu_phase_get_phase() 71 parent_rate = clk_hw_get_rate(parent); in ccu_phase_set_phase() 81 grandparent_rate = clk_hw_get_rate(grandparent); in ccu_phase_set_phase()
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H A D | ccu_mux.c | 97 best_parent_rate = clk_hw_get_rate(best_parent); in ccu_mux_helper_determine_rate() 124 clk_hw_get_rate(parent)); in ccu_mux_helper_determine_rate()
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/linux/drivers/clk/ti/ |
H A D | clkt_dpll.c | 76 fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n; in _dpll_test_fint() 254 return clk_hw_get_rate(dd->clk_bypass); in omap2_get_dpll_rate() 262 dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult; in omap2_get_dpll_rate() 305 ref_rate = clk_hw_get_rate(dd->clk_ref); in omap2_dpll_round_rate()
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H A D | dpll3xxx.c | 98 fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel() 251 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_dco() 277 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_sddiv() 318 ref_rate = clk_hw_get_rate(dd->clk_ref); in omap3_noncore_dpll_ssc_program() 546 if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) { in omap3_noncore_dpll_enable() 598 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap3_noncore_dpll_determine_rate()
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H A D | dpll44xx.c | 94 fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); in omap4_dpll_lpmode_recalc() 214 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap4_dpll_regm4xen_determine_rate()
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/linux/drivers/clk/at91/ |
H A D | clk-utmi.c | 55 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_prepare() 202 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_sama7g5_prepare() 236 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_sama7g5_is_prepared()
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H A D | clk-programmable.c | 67 parent_rate = clk_hw_get_rate(parent); in clk_programmable_determine_rate() 187 prog->pms.parent_rate = clk_hw_get_rate(parent_hw); in clk_programmable_save_context()
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/linux/drivers/clk/tegra/ |
H A D | clk-tegra210-emc.c | 79 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in tegra210_clk_emc_recalc_rate() 97 return clk_hw_get_rate(hw); in tegra210_clk_emc_round_rate() 151 if (config->parent_rate != clk_hw_get_rate(old)) { in tegra210_clk_emc_set_rate() 342 config->parent_rate = clk_hw_get_rate(parent); in tegra210_clk_emc_attach()
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H A D | clk-divider.c | 120 unsigned long parent_rate = clk_hw_get_rate(parent); in clk_divider_restore_context() 121 unsigned long rate = clk_hw_get_rate(hw); in clk_divider_restore_context()
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H A D | clk-tegra124-emc.c | 103 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in emc_recalc_rate() 159 req->rate = clk_hw_get_rate(hw); in emc_determine_rate() 331 if (clk_hw_get_rate(hw) == rate) in emc_set_rate()
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H A D | clk-sdmmc-mux.c | 209 unsigned long parent_rate = clk_hw_get_rate(parent); in clk_sdmmc_mux_restore_context() 210 unsigned long rate = clk_hw_get_rate(hw); in clk_sdmmc_mux_restore_context()
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H A D | clk-device.c | 102 rate = clk_hw_get_rate(clk_dev->hw); in tegra_clock_sync_pd_state()
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/linux/drivers/clk/mmp/ |
H A D | clk-mix.c | 121 parent_rate = clk_hw_get_rate(parent); in _filter_clk_table() 226 parent_rate = clk_hw_get_rate(parent); in mmp_clk_mix_determine_rate() 241 parent_rate = clk_hw_get_rate(parent); in mmp_clk_mix_determine_rate() 392 parent_rate = clk_hw_get_rate(parent); in mmp_clk_set_rate() 407 parent_rate = clk_hw_get_rate(parent); in mmp_clk_set_rate()
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H A D | clk-gate.c | 43 rate = clk_hw_get_rate(hw); in mmp_clk_gate_enable()
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/linux/drivers/clk/qcom/ |
H A D | clk-regmap-mux-div.c | 98 unsigned long parent_rate = clk_hw_get_rate(parent); in mux_div_determine_rate() 135 unsigned long parent_rate = clk_hw_get_rate(parent); in __mux_div_set_rate_and_parent() 214 unsigned long parent_rate = clk_hw_get_rate(p); in mux_div_recalc_rate()
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H A D | clk-rcg2.c | 254 rate = clk_hw_get_rate(p); in _freq_tbl_determine_rate() 291 parent_rate = clk_hw_get_rate(p); in __clk_rcg2_select_conf() 362 rate = clk_hw_get_rate(p); in _freq_tbl_fm_determine_rate() 768 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); in clk_edp_pixel_determine_rate() 1049 if (req->rate == clk_hw_get_rate(xo)) { in clk_gfx3d_determine_rate() 1060 p0_rate = clk_hw_get_rate(p0); in clk_gfx3d_determine_rate() 1070 if (clk_hw_get_rate(p2) == parent_req.rate) in clk_gfx3d_determine_rate() 1444 prate = clk_hw_get_rate(p); in clk_rcg2_dfs_populate_freq()
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/linux/drivers/clk/imx/ |
H A D | clk-lpcg-scu.c | 86 lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); in clk_lpcg_scu_enable() 103 lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); in clk_lpcg_scu_disable()
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/linux/drivers/clk/rockchip/ |
H A D | clk-mmc-phase.c | 48 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_get_phase() 77 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_set_phase()
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/linux/drivers/clk/samsung/ |
H A D | clk-exynos4.c | 1051 finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]); in exynos4_clk_register_finpll() 1298 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init() 1305 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000) in exynos4_clk_init() 1312 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init() 1387 clk_hw_get_rate(hws[CLK_SCLK_APLL]), in exynos4_clk_init() 1388 clk_hw_get_rate(hws[CLK_SCLK_MPLL]), in exynos4_clk_init() 1389 clk_hw_get_rate(hws[CLK_SCLK_EPLL]), in exynos4_clk_init() 1390 clk_hw_get_rate(hws[CLK_SCLK_VPLL]), in exynos4_clk_init() 1391 clk_hw_get_rate(hws[CLK_DIV_CORE2])); in exynos4_clk_init()
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H A D | clk-s3c64xx.c | 464 clk_hw_get_rate(hws[MOUT_APLL]), in s3c64xx_clk_init() 465 clk_hw_get_rate(hws[MOUT_MPLL]), in s3c64xx_clk_init() 466 clk_hw_get_rate(hws[MOUT_EPLL]), in s3c64xx_clk_init() 467 clk_hw_get_rate(hws[ARMCLK])); in s3c64xx_clk_init()
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H A D | clk-cpu.c | 202 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change() 329 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos5433_cpuclk_pre_rate_change() 454 divp_rate = clk_hw_get_rate(clk_divp); in exynos850_alt_parent_set_max_rate() 484 unsigned long alt_prate = clk_hw_get_rate(alt_parent); in exynos850_cpuclk_pre_rate_change()
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H A D | clk-s5pv210.c | 794 clk_hw_get_rate(hws[MOUT_APLL]), in __s5pv210_clk_init() 795 clk_hw_get_rate(hws[MOUT_MPLL]), in __s5pv210_clk_init() 796 clk_hw_get_rate(hws[MOUT_EPLL]), in __s5pv210_clk_init() 797 clk_hw_get_rate(hws[MOUT_VPLL])); in __s5pv210_clk_init()
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H A D | clk-exynos5250.c | 813 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init() 818 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ) in exynos5250_clk_init() 864 clk_hw_get_rate(hws[CLK_DIV_ARM2])); in exynos5250_clk_init()
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/linux/drivers/clk/ |
H A D | clk-lan966x.c | 167 if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) { in lan966x_gck_determine_rate() 169 req->best_parent_rate = clk_hw_get_rate(parent); in lan966x_gck_determine_rate()
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/linux/drivers/clk/bcm/ |
H A D | clk-kona.c | 1007 return clk_hw_get_rate(hw); in kona_peri_clk_round_rate() 1044 parent_rate = clk_hw_get_rate(current_parent); in kona_peri_clk_determine_rate() 1059 parent_rate = clk_hw_get_rate(parent); in kona_peri_clk_determine_rate() 1134 if (rate == clk_hw_get_rate(hw)) in kona_peri_clk_set_rate()
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