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Searched refs:clk_core (Results 1 – 14 of 14) sorted by relevance

/linux/include/trace/events/
H A Dclk.h13 struct clk_core;
17 TP_PROTO(struct clk_core *core),
34 TP_PROTO(struct clk_core *core),
41 TP_PROTO(struct clk_core *core),
48 TP_PROTO(struct clk_core *core),
55 TP_PROTO(struct clk_core *core),
62 TP_PROTO(struct clk_core *core),
69 TP_PROTO(struct clk_core *core),
76 TP_PROTO(struct clk_core *core),
83 TP_PROTO(struct clk_core *cor
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/linux/drivers/clk/
H A Dclk.c60 struct clk_core *core;
66 struct clk_core { struct
74 struct clk_core *parent; argument
81 struct clk_core *new_parent; argument
82 struct clk_core *new_child; argument
110 struct clk_core *core; argument
121 static int clk_pm_runtime_get(struct clk_core *core) in clk_pm_runtime_get()
129 static void clk_pm_runtime_put(struct clk_core *core) in clk_pm_runtime_put()
155 struct clk_core *core, *failed; in clk_pm_runtime_get_all()
200 struct clk_core *core; in clk_pm_runtime_put_all()
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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi29 clocks = <&clk_core CLK_MIPS_PLL>;
139 <&clk_core CLK_I2S>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
159 <&clk_core CLK_AUDIO_DAC>;
161 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
176 <&clk_core CLK_SPDIF>;
178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
230 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
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/linux/drivers/cpufreq/
H A Dpxa2xx-cpufreq.c46 struct clk *clk_core; member
181 return (unsigned int) clk_get_rate(data->clk_core) / 1000; in pxa_cpufreq_get()
207 clk_set_rate(data->clk_core, new_freq_cpu * 1000); in pxa_set_target()
302 pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core"); in pxa_cpu_init()
303 if (IS_ERR(pxa_cpufreq_data.clk_core)) in pxa_cpu_init()
304 return PTR_ERR(pxa_cpufreq_data.clk_core); in pxa_cpu_init()
/linux/Documentation/driver-api/
H A Dclk.rst38 is defined in struct clk_foo and pointed to within struct clk_core. This
45 Below is the common struct clk_core definition from
48 struct clk_core {
53 struct clk_core *parent;
55 struct clk_core **parents;
65 Platforms and devices utilizing the common struct clk_core use the struct
66 clk_ops pointer in struct clk_core to perform the hardware-specific parts of
106 The strength of the common struct clk_core comes from its .ops and .hw pointers
122 framework code and struct clk_core.
/linux/drivers/mmc/host/
H A Dsdhci-pxav2.c261 struct clk *clk, *clk_core; in sdhci_pxav2_probe() local
277 clk_core = devm_clk_get_optional_enabled(dev, "core"); in sdhci_pxav2_probe()
278 if (IS_ERR(clk_core)) in sdhci_pxav2_probe()
279 return dev_err_probe(dev, PTR_ERR(clk_core), in sdhci_pxav2_probe()
H A Dsdhci-of-k1.c64 struct clk *clk_core; member
213 sdhst->clk_core = devm_clk_get_enabled(dev, "core"); in spacemit_sdhci_get_clocks()
214 if (IS_ERR(sdhst->clk_core)) in spacemit_sdhci_get_clocks()
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c513 clk_set_rate(gpu->clk_core, in etnaviv_gpu_update_clock()
1656 ret = clk_prepare_enable(gpu->clk_core); in etnaviv_gpu_clk_enable()
1667 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_enable()
1679 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_disable()
1940 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); in etnaviv_gpu_platform_probe()
1941 DBG("clk_core: %p", gpu->clk_core); in etnaviv_gpu_platform_probe()
1942 if (IS_ERR(gpu->clk_core)) in etnaviv_gpu_platform_probe()
1943 return PTR_ERR(gpu->clk_core); in etnaviv_gpu_platform_probe()
1944 gpu->base_rate_core = clk_get_rate(gpu->clk_core); in etnaviv_gpu_platform_probe()
H A Detnaviv_gpu.h160 struct clk *clk_core; member
/linux/Documentation/devicetree/bindings/mips/img/
H A Dpistachio.txt30 clocks = <&clk_core CLK_MIPS>;
/linux/Documentation/devicetree/bindings/sound/
H A Dimg,spdif-out.txt39 <&clk_core CLK_SPDIF>;
H A Dimg,parallel-out.txt39 <&clk_core CLK_AUDIO_DAC>;
H A Dimg,i2s-out.txt45 <&clk_core CLK_I2S>;
/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-core.c157 struct clk *clk_core; member
1027 clk_rate = clk_get_rate(dev->clk_core); in allegro_encoder_buffer_init()
3952 dev->clk_core = devm_clk_get(&pdev->dev, "core_clk"); in allegro_probe()
3953 if (IS_ERR(dev->clk_core)) in allegro_probe()
3954 return PTR_ERR(dev->clk_core); in allegro_probe()
4012 unsigned int clk_core; in allegro_runtime_resume() local
4020 err = regmap_read(settings, VCU_CORE_CLK, &clk_core); in allegro_runtime_resume()
4023 err = clk_set_rate(dev->clk_core, MHZ_TO_HZ(clk_core)); in allegro_runtime_resume()
4026 err = clk_prepare_enable(dev->clk_core); in allegro_runtime_resume()
4045 clk_disable_unprepare(dev->clk_core); in allegro_runtime_resume()
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