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Searched refs:clk1 (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/clk/spear/
H A Dspear3xx_clock.c390 struct clk *clk, *clk1, *ras_apb_clk; in spear3xx_clk_init() local
414 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
416 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear3xx_clk_init()
420 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
422 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear3xx_clk_init()
436 &_lock, &clk1); in spear3xx_clk_init()
438 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); in spear3xx_clk_init()
454 &_lock, &clk1); in spear3xx_clk_init()
456 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); in spear3xx_clk_init()
506 &_lock, &clk1); in spear3xx_clk_init()
[all …]
H A Dspear6xx_clock.c116 struct clk *clk, *clk1; in spear6xx_clk_init() local
136 &_lock, &clk1, NULL); in spear6xx_clk_init()
138 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear6xx_clk_init()
142 &_lock, &clk1, NULL); in spear6xx_clk_init()
144 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear6xx_clk_init()
162 &_lock, &clk1); in spear6xx_clk_init()
164 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); in spear6xx_clk_init()
182 &_lock, &clk1); in spear6xx_clk_init()
184 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); in spear6xx_clk_init()
198 &_lock, &clk1); in spear6xx_clk_init()
[all …]
H A Dspear1310_clock.c384 struct clk *clk, *clk1; in spear1310_clk_init() local
417 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear1310_clk_init()
419 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear1310_clk_init()
428 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear1310_clk_init()
430 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear1310_clk_init()
439 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear1310_clk_init()
441 clk_register_clkdev(clk1, "pll3_clk", NULL); in spear1310_clk_init()
445 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); in spear1310_clk_init()
447 clk_register_clkdev(clk1, "pll4_clk", NULL); in spear1310_clk_init()
552 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
[all …]
/linux/drivers/clk/ti/
H A Dclk-33xx.c274 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local
294 clk1 = clk_get_sys(NULL, "sys_clkin_ck"); in am33xx_dt_clk_init()
296 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
299 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
307 clk1 = clk_get_sys(NULL, "wdt1_fck"); in am33xx_dt_clk_init()
309 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
H A Dadpll.c267 struct clk *clk1, in ti_adpll_init_mux() argument
279 parents[1] = __clk_get_name(clk1); in ti_adpll_init_mux()
576 struct clk *clk1) in ti_adpll_init_clkout() argument
607 parent_names[1] = __clk_get_name(clk1); in ti_adpll_init_clkout()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgf100.c279 u32 clk0, clk1 = 0; in calc_clk() local
292 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
294 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
295 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
299 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
318 info->freq = clk1; in calc_clk()
H A Dgk104.c293 u32 clk0, clk1 = 0; in calc_clk() local
306 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
308 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
309 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
313 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
332 info->freq = clk1; in calc_clk()
H A Dmcp77.c184 u32 clk0 = src, clk1 = src; in calc_P() local
187 clk1 = clk0 << (*div ? 1 : 0); in calc_P()
193 if (target - clk0 <= clk1 - target) in calc_P()
196 return clk1; in calc_P()
H A Dnv50.c347 u32 clk0 = src, clk1 = src; in calc_div() local
350 clk1 = clk0 << (*div ? 1 : 0); in calc_div()
356 if (target - clk0 <= clk1 - target) in calc_div()
359 return clk1; in calc_div()
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dusb.txt12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
H A Ducc.txt25 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
29 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit-fabric.dtsi11 fabric_clk1: fabric-clk1 {
H A Dmpfs-tysom-m-fabric.dtsi13 fabric_clk1: fabric-clk1 {
H A Dmpfs-polarberry-fabric.dtsi11 fabric_clk1: fabric-clk1 {
H A Dmpfs-m100pfs-fabric.dtsi11 fabric_clk1: fabric-clk1 {
H A Dmpfs-beaglev-fire-fabric.dtsi10 fabric_clk1: fabric-clk1 {
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Duqe_serial.txt8 should be "clk1"-"clk28" for external clock source.
/linux/drivers/clk/zynq/
H A Dclkc.c175 enum zynq_clk clk1, const char *clk_name0, in zynq_clk_register_periph_clk() argument
204 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
219 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
/linux/drivers/clk/renesas/
H A Drzv2h-cpg.c680 unsigned int clk1, clk2; in rzv2h_cpg_pll_clk_recalc_rate() local
686 clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset)); in rzv2h_cpg_pll_clk_recalc_rate()
689 rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) + in rzv2h_cpg_pll_clk_recalc_rate()
690 (s16)FIELD_GET(CPG_PLL_CLK1_KDIV, clk1), in rzv2h_cpg_pll_clk_recalc_rate()
693 return DIV_ROUND_CLOSEST_ULL(rate, FIELD_GET(CPG_PLL_CLK1_PDIV, clk1)); in rzv2h_cpg_pll_clk_recalc_rate()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562-pinctrl.dtsi23 camm0_clk1_out: camm0-clk1-out {
37 camm1_clk1_out: camm1-clk1-out {
125 clk1 {
127 clk1_32k_out: clk1-32k-out {
834 pdmm0_clk1: pdmm0-clk1 {
876 pdmm1_clk1: pdmm1-clk1 {
/linux/drivers/clk/
H A Dclk_test.c3106 struct clk_dummy_context clk1; member
3196 clk_assigned_rates_register_clk(test, &ctx->clk1, np, in clk_assigned_rates_test_init()
3204 data->hws[1] = &ctx->clk1.hw; in clk_assigned_rates_test_init()
3234 KUNIT_EXPECT_EQ(test, ctx->clk1.rate, ASSIGNED_RATES_1_RATE); in clk_assigned_rates_assigns_multiple()
3477 KUNIT_EXPECT_EQ(test, ctx->clk1.sscs.modfreq_hz, ASSIGNED_SSCS_1_MODFREQ); in KUNIT_ARRAY_PARAM_DESC()
3478 KUNIT_EXPECT_EQ(test, ctx->clk1.sscs.spread_bp, ASSIGNED_SSCS_1_SPREAD); in KUNIT_ARRAY_PARAM_DESC()
3479 KUNIT_EXPECT_EQ(test, ctx->clk1.sscs.method, ASSIGNED_SSCS_1_METHOD); in KUNIT_ARRAY_PARAM_DESC()
/linux/drivers/clk/qcom/
H A Dclk-rpmh.c374 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
391 DEFINE_CLK_RPMH_VRM(clk1, _a1_e0, "C1A_E0", 1);
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi38 clk1-out-pw4 {
612 clk1-req-pee2 {
H A Dtegra30-apalis.dtsi62 clk1-out-pw4 {
145 clk1-req-pee2 {
H A Dtegra30-apalis-v1.1.dtsi63 clk1-out-pw4 {
146 clk1-req-pee2 {

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