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Searched refs:chid (Results 1 – 25 of 42) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchid.c25 nvkm_chid_put(struct nvkm_chid *chid, int id, spinlock_t *data_lock) in nvkm_chid_put() argument
28 spin_lock_irq(&chid->lock); in nvkm_chid_put()
30 chid->data[id] = NULL; in nvkm_chid_put()
32 clear_bit(id, chid->used); in nvkm_chid_put()
33 spin_unlock_irq(&chid->lock); in nvkm_chid_put()
38 nvkm_chid_get(struct nvkm_chid *chid, void *data) in nvkm_chid_get() argument
42 spin_lock_irq(&chid->lock); in nvkm_chid_get()
43 cid = find_first_zero_bit(chid->used, chid->nr); in nvkm_chid_get()
44 if (cid < chid->nr) { in nvkm_chid_get()
45 set_bit(cid, chid->used); in nvkm_chid_get()
[all …]
H A Drunl.c185 struct nvkm_chid *chid = runl->chid; in nvkm_runl_chan_get_inst() local
190 spin_lock_irqsave(&chid->lock, flags); in nvkm_runl_chan_get_inst()
191 for_each_set_bit(id, chid->used, chid->nr) { in nvkm_runl_chan_get_inst()
192 chan = chid->data[id]; in nvkm_runl_chan_get_inst()
197 spin_unlock(&chid->lock); in nvkm_runl_chan_get_inst()
202 spin_unlock_irqrestore(&chid->lock, flags); in nvkm_runl_chan_get_inst()
209 struct nvkm_chid *chid = runl->chid; in nvkm_runl_chan_get_chid() local
213 spin_lock_irqsave(&chid->lock, flags); in nvkm_runl_chan_get_chid()
214 if (!WARN_ON(id >= chid->nr)) { in nvkm_runl_chan_get_chid()
215 chan = chid->data[id]; in nvkm_runl_chan_get_chid()
[all …]
H A Dbase.c181 case NV_DEVICE_HOST_CHANNELS: *data = fifo->chid ? fifo->chid->nr : 0; return 0; in nvkm_fifo_info()
225 if (!fifo->chid) { in nvkm_fifo_info()
228 *data = runl->chid->nr; in nvkm_fifo_info()
309 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, fifo->chid->nr * in nvkm_fifo_oneinit()
350 nvkm_chid_unref(&fifo->chid); in nvkm_fifo_dtor()
H A Dga100.c198 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask; in ga100_runq_intr_1() local
202 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); in ga100_runq_intr_1()
203 chan = nvkm_runl_chan_get_chid(runl, chid, &flags); in ga100_runq_intr_1()
237 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask; in ga100_runq_intr_0() local
242 chan = nvkm_runl_chan_get_chid(runl, chid, &flags); in ga100_runq_intr_0()
H A Drunl.h70 struct nvkm_chid *chid; member
117 struct nvkm_chan *nvkm_runl_chan_get_chid(struct nvkm_runl *, int chid, unsigned long *irqflags);
/linux/drivers/dma/
H A Dcv1800b-dmamux.c34 #define DMAMUX_CH_REGPOS(chid) \ argument
35 ((chid) / DMAMUX_NR_CH_PER_REGISTER)
36 #define DMAMUX_CH_REGOFF(chid) \ argument
37 ((chid) % DMAMUX_NR_CH_PER_REGISTER)
38 #define DMAMUX_CH_REG(chid) \ argument
39 ((DMAMUX_CH_REGPOS(chid) * sizeof(u32)) + \
41 #define DMAMUX_CH_SET(chid, val) \ argument
42 (((val) << (DMAMUX_CH_REGOFF(chid) * DMAMUX_BIT_PER_CH)) | \
44 #define DMAMUX_CH_MASK(chid) \ argument
45 DMAMUX_CH_SET(chid, DMAMUX_CH_MASk)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/core/
H A Dramht.c27 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_hash() argument
36 hash ^= chid << (ramht->bits - 4); in nvkm_ramht_hash()
41 nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) in nvkm_ramht_search() argument
45 co = ho = nvkm_ramht_hash(ramht, chid, handle); in nvkm_ramht_search()
47 if (ramht->data[co].chid == chid) { in nvkm_ramht_search()
61 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_update() argument
68 data->chid = chid; in nvkm_ramht_update()
75 data->chid = -1; in nvkm_ramht_update()
108 int chid, int addr, u32 handle, u32 context) in nvkm_ramht_insert() argument
112 if (nvkm_ramht_search(ramht, chid, handle)) in nvkm_ramht_insert()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgp102.c38 int ctrl = chan->chid.ctrl; in gp102_disp_dmac_init()
39 int user = chan->chid.user; in gp102_disp_dmac_init()
148 gp102_disp_intr_error(struct nvkm_disp *disp, int chid) in gp102_disp_intr_error() argument
152 u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12)); in gp102_disp_intr_error()
153 u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12)); in gp102_disp_intr_error()
154 u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12)); in gp102_disp_intr_error()
157 chid, (mthd & 0x0000ffc), data, mthd, unkn); in gp102_disp_intr_error()
159 if (chid < ARRAY_SIZE(disp->chan)) { in gp102_disp_intr_error()
162 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); in gp102_disp_intr_error()
169 nvkm_wr32(device, 0x61009c, (1 << chid)); in gp102_disp_intr_error()
[all …]
H A Dgf119.c507 const u32 mask = 0x00000001 << chan->chid.user; in gf119_disp_chan_intr()
522 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_fini()
523 int user = chan->chid.user; in gf119_disp_pioc_fini()
541 int ctrl = chan->chid.ctrl; in gf119_disp_pioc_init()
542 int user = chan->chid.user; in gf119_disp_pioc_init()
570 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle, in gf119_disp_dmac_bind()
571 chan->chid.user << 27 | 0x00000001); in gf119_disp_dmac_bind()
579 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_fini()
580 int user = chan->chid.user; in gf119_disp_dmac_fini()
601 int ctrl = chan->chid.ctrl; in gf119_disp_dmac_init()
[all …]
H A Dnv50.c502 mthd->name, chan->chid.user); in nv50_disp_chan_mthd()
538 nv50_disp_chan_uevent_send(struct nvkm_disp *disp, int chid) in nv50_disp_chan_uevent_send() argument
540 nvkm_event_ntfy(&disp->uevent, chid, NVKM_DISP_EVENT_CHAN_AWAKEN); in nv50_disp_chan_uevent_send()
553 return 0x640000 + (chan->chid.user * 0x1000); in nv50_disp_chan_user()
560 const u32 mask = 0x00010001 << chan->chid.user; in nv50_disp_chan_intr()
561 const u32 data = en ? 0x00010000 << chan->chid.user : 0x00000000; in nv50_disp_chan_intr()
571 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_fini()
572 int user = chan->chid.user; in nv50_disp_pioc_fini()
590 int ctrl = chan->chid.ctrl; in nv50_disp_pioc_init()
591 int user = chan->chid.user; in nv50_disp_pioc_init()
[all …]
/linux/drivers/dma/qcom/
H A Dgpi.c93 #define GPII_n_CH_CMD(opcode, chid) \ argument
95 FIELD_PREP(GPII_n_CH_CMD_CHID, chid))
142 #define GPII_n_EV_CMD(opcode, chid) \ argument
144 FIELD_PREP(GPII_n_EV_CMD_CHID, chid))
248 u8 chid; member
259 u8 chid; member
269 u8 chid; member
483 u32 chid; member
674 u32 chid = MAX_CHANNELS_PER_GPII; in gpi_send_cmd() local
682 chid = gchan->chid; in gpi_send_cmd()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c402 int chid; member
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel() local
553 if (chid < ARRAY_SIZE(gr->chan)) in nv10_gr_channel()
554 chan = gr->chan[chid]; in nv10_gr_channel()
812 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) in nv10_gr_load_dma_vtxbuf() argument
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); in nv10_gr_load_dma_vtxbuf()
883 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) in nv10_gr_load_context() argument
901 nv10_gr_load_dma_vtxbuf(chan, chid, inst); in nv10_gr_load_context()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
937 int chid; in nv10_gr_context_switch() local
[all …]
H A Dnv04.c362 int chid; member
1077 int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24; in nv04_gr_channel() local
1078 if (chid < ARRAY_SIZE(gr->chan)) in nv04_gr_channel()
1079 chan = gr->chan[chid]; in nv04_gr_channel()
1085 nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) in nv04_gr_load_context() argument
1094 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv04_gr_load_context()
1119 int chid; in nv04_gr_context_switch() local
1129 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; in nv04_gr_context_switch()
1130 next = gr->chan[chid]; in nv04_gr_context_switch()
1132 nv04_gr_load_context(next, chid); in nv04_gr_context_switch()
[all …]
H A Dnv50.c396 int chid, u64 inst, const char *name) in nv50_gr_trap_handler() argument
436 chid, inst, name, subc, class, mthd, in nv50_gr_trap_handler()
461 "40084c %08x\n", chid, inst, name, in nv50_gr_trap_handler()
638 int chid = -1; in nv50_gr_intr() local
643 chid = chan->id; in nv50_gr_intr()
655 if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name)) in nv50_gr_intr()
668 stat, msg, chid, (u64)inst << 12, name, in nv50_gr_intr()
H A Dnv2a.c32 chan->chid = fifoch->id; in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
H A Dnv25.c32 chan->chid = fifoch->id; in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
H A Dnv35.c32 chan->chid = fifoch->id; in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
H A Dnv34.c32 chan->chid = fifoch->id; in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
H A Dnv20.h28 int chid; member
/linux/drivers/bus/mhi/
H A Dcommon.h126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
152 #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ argument
/linux/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dramht.h9 int chid; member
26 int chid, int addr, u32 handle, u32 context);
29 nvkm_ramht_search(struct nvkm_ramht *, int chid, u32 handle);
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-hidma1 What: /sys/devices/platform/hidma-*/chid
2 /sys/devices/platform/QCOM8061:*/chid
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dfifo.c76 bool priv, int chid, u64 inst_addr, u64 userd_addr, u64 mthdbuf_addr, in r535_chan_alloc() argument
82 const int userd_p = chid / CHID_PER_USERD; in r535_chan_alloc()
83 const int userd_i = chid % CHID_PER_USERD; in r535_chan_alloc()
345 r535_fifo_rc_chid(struct nvkm_fifo *fifo, int chid) in r535_fifo_rc_chid() argument
350 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); in r535_fifo_rc_chid()
352 nvkm_error(&fifo->engine.subdev, "rc: chid %d not found!\n", chid); in r535_fifo_rc_chid()
370 msg->nv2080EngineType, msg->chid, msg->exceptType, msg->scope, in r535_fifo_rc_triggered()
373 r535_fifo_rc_chid(gsp->subdev.device->fifo, msg->chid); in r535_fifo_rc_triggered()
472 (ret = nvkm_chid_new(&nvkm_chan_event, subdev, chids, first, count, &fifo->chid))) in r535_fifo_runl_ctor()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A Dbase.c30 nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) in nvkm_sw_mthd() argument
38 if (chan->fifo->id == chid) { in nvkm_sw_mthd()
/linux/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dsw.h13 bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data);

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