1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "cgx.h"
21 #include "rvu.h"
22 #include "lmac_common.h"
23
24 #define DRV_NAME "Marvell-CGX-RPM"
25
26 #define CGX_RX_STAT_GLOBAL_INDEX 9
27
28 static LIST_HEAD(cgx_list);
29
30 /* Convert firmware speed encoding to user format(Mbps) */
31 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
32 [CGX_LINK_NONE] = 0,
33 [CGX_LINK_10M] = 10,
34 [CGX_LINK_100M] = 100,
35 [CGX_LINK_1G] = 1000,
36 [CGX_LINK_2HG] = 2500,
37 [CGX_LINK_5G] = 5000,
38 [CGX_LINK_10G] = 10000,
39 [CGX_LINK_20G] = 20000,
40 [CGX_LINK_25G] = 25000,
41 [CGX_LINK_40G] = 40000,
42 [CGX_LINK_50G] = 50000,
43 [CGX_LINK_80G] = 80000,
44 [CGX_LINK_100G] = 100000,
45 };
46
47 /* Convert firmware lmac type encoding to string */
48 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
49 [LMAC_MODE_SGMII] = "SGMII",
50 [LMAC_MODE_XAUI] = "XAUI",
51 [LMAC_MODE_RXAUI] = "RXAUI",
52 [LMAC_MODE_10G_R] = "10G_R",
53 [LMAC_MODE_40G_R] = "40G_R",
54 [LMAC_MODE_QSGMII] = "QSGMII",
55 [LMAC_MODE_25G_R] = "25G_R",
56 [LMAC_MODE_50G_R] = "50G_R",
57 [LMAC_MODE_100G_R] = "100G_R",
58 [LMAC_MODE_USXGMII] = "USXGMII",
59 [LMAC_MODE_USGMII] = "USGMII",
60 };
61
62 /* CGX PHY management internal APIs */
63 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
64
65 /* Supported devices */
66 static const struct pci_device_id cgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
69 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) },
70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
71 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) },
72 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
73 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) },
74 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
75 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) },
76 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
77 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) },
78 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
79 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) },
80 { 0, } /* end of table */
81 };
82
83 MODULE_DEVICE_TABLE(pci, cgx_id_table);
84
is_dev_rpm(void * cgxd)85 static bool is_dev_rpm(void *cgxd)
86 {
87 struct cgx *cgx = cgxd;
88
89 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) ||
90 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM);
91 }
92
is_lmac_valid(struct cgx * cgx,int lmac_id)93 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
94 {
95 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac)
96 return false;
97 return test_bit(lmac_id, &cgx->lmac_bmap);
98 }
99
100 /* Helper function to get sequential index
101 * given the enabled LMAC of a CGX
102 */
get_sequence_id_of_lmac(struct cgx * cgx,int lmac_id)103 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
104 {
105 int tmp, id = 0;
106
107 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
108 if (tmp == lmac_id)
109 break;
110 id++;
111 }
112
113 return id;
114 }
115
get_mac_ops(void * cgxd)116 struct mac_ops *get_mac_ops(void *cgxd)
117 {
118 if (!cgxd)
119 return cgxd;
120
121 return ((struct cgx *)cgxd)->mac_ops;
122 }
123
cgx_get_fifo_len(void * cgxd)124 u32 cgx_get_fifo_len(void *cgxd)
125 {
126 return ((struct cgx *)cgxd)->fifo_len;
127 }
128
cgx_write(struct cgx * cgx,u64 lmac,u64 offset,u64 val)129 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
130 {
131 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
132 offset);
133 }
134
cgx_read(struct cgx * cgx,u64 lmac,u64 offset)135 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
136 {
137 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
138 offset);
139 }
140
lmac_pdata(u8 lmac_id,struct cgx * cgx)141 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
142 {
143 if (!cgx || lmac_id >= cgx->max_lmac_per_mac)
144 return NULL;
145
146 return cgx->lmac_idmap[lmac_id];
147 }
148
cgx_get_cgxcnt_max(void)149 int cgx_get_cgxcnt_max(void)
150 {
151 struct cgx *cgx_dev;
152 int idmax = -ENODEV;
153
154 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
155 if (cgx_dev->cgx_id > idmax)
156 idmax = cgx_dev->cgx_id;
157
158 if (idmax < 0)
159 return 0;
160
161 return idmax + 1;
162 }
163
cgx_get_lmac_cnt(void * cgxd)164 int cgx_get_lmac_cnt(void *cgxd)
165 {
166 struct cgx *cgx = cgxd;
167
168 if (!cgx)
169 return -ENODEV;
170
171 return cgx->lmac_count;
172 }
173
cgx_get_pdata(int cgx_id)174 void *cgx_get_pdata(int cgx_id)
175 {
176 struct cgx *cgx_dev;
177
178 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
179 if (cgx_dev->cgx_id == cgx_id)
180 return cgx_dev;
181 }
182 return NULL;
183 }
184
cgx_lmac_write(int cgx_id,int lmac_id,u64 offset,u64 val)185 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
186 {
187 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
188
189 /* Software must not access disabled LMAC registers */
190 if (!is_lmac_valid(cgx_dev, lmac_id))
191 return;
192 cgx_write(cgx_dev, lmac_id, offset, val);
193 }
194
cgx_lmac_read(int cgx_id,int lmac_id,u64 offset)195 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
196 {
197 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
198
199 /* Software must not access disabled LMAC registers */
200 if (!is_lmac_valid(cgx_dev, lmac_id))
201 return 0;
202
203 return cgx_read(cgx_dev, lmac_id, offset);
204 }
205
cgx_get_cgxid(void * cgxd)206 int cgx_get_cgxid(void *cgxd)
207 {
208 struct cgx *cgx = cgxd;
209
210 if (!cgx)
211 return -EINVAL;
212
213 return cgx->cgx_id;
214 }
215
cgx_lmac_get_p2x(int cgx_id,int lmac_id)216 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
217 {
218 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
219 u64 cfg;
220
221 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
222
223 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
224 }
225
cgx_get_nix_resetbit(struct cgx * cgx)226 static u8 cgx_get_nix_resetbit(struct cgx *cgx)
227 {
228 int first_lmac;
229 u8 p2x;
230
231 /* non 98XX silicons supports only NIX0 block */
232 if (cgx->pdev->subsystem_device != PCI_SUBSYS_DEVID_98XX)
233 return CGX_NIX0_RESET;
234
235 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
236 p2x = cgx_lmac_get_p2x(cgx->cgx_id, first_lmac);
237
238 if (p2x == CMR_P2X_SEL_NIX1)
239 return CGX_NIX1_RESET;
240 else
241 return CGX_NIX0_RESET;
242 }
243
244 /* Ensure the required lock for event queue(where asynchronous events are
245 * posted) is acquired before calling this API. Else an asynchronous event(with
246 * latest link status) can reach the destination before this function returns
247 * and could make the link status appear wrong.
248 */
cgx_get_link_info(void * cgxd,int lmac_id,struct cgx_link_user_info * linfo)249 int cgx_get_link_info(void *cgxd, int lmac_id,
250 struct cgx_link_user_info *linfo)
251 {
252 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
253
254 if (!lmac)
255 return -ENODEV;
256
257 *linfo = lmac->link_info;
258 return 0;
259 }
260
cgx_lmac_addr_set(u8 cgx_id,u8 lmac_id,u8 * mac_addr)261 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
262 {
263 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
264 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
265 struct mac_ops *mac_ops;
266 int index, id;
267 u64 cfg;
268
269 if (!lmac)
270 return -ENODEV;
271
272 /* access mac_ops to know csr_offset */
273 mac_ops = cgx_dev->mac_ops;
274
275 /* copy 6bytes from macaddr */
276 /* memcpy(&cfg, mac_addr, 6); */
277
278 cfg = ether_addr_to_u64(mac_addr);
279
280 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
281
282 index = id * lmac->mac_to_index_bmap.max;
283
284 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
285 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
286
287 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
288 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
289 CGX_DMAC_MCAST_MODE);
290 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
291
292 return 0;
293 }
294
cgx_read_dmac_ctrl(void * cgxd,int lmac_id)295 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
296 {
297 struct mac_ops *mac_ops;
298 struct cgx *cgx = cgxd;
299
300 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
301 return 0;
302
303 cgx = cgxd;
304 /* Get mac_ops to know csr offset */
305 mac_ops = cgx->mac_ops;
306
307 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
308 }
309
cgx_read_dmac_entry(void * cgxd,int index)310 u64 cgx_read_dmac_entry(void *cgxd, int index)
311 {
312 struct mac_ops *mac_ops;
313 struct cgx *cgx;
314
315 if (!cgxd)
316 return 0;
317
318 cgx = cgxd;
319 mac_ops = cgx->mac_ops;
320 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
321 }
322
cgx_lmac_addr_add(u8 cgx_id,u8 lmac_id,u8 * mac_addr)323 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
324 {
325 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
326 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
327 struct mac_ops *mac_ops;
328 int index, idx;
329 u64 cfg = 0;
330 int id;
331
332 if (!lmac)
333 return -ENODEV;
334
335 mac_ops = cgx_dev->mac_ops;
336 /* Get available index where entry is to be installed */
337 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
338 if (idx < 0)
339 return idx;
340
341 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
342
343 index = id * lmac->mac_to_index_bmap.max + idx;
344
345 cfg = ether_addr_to_u64(mac_addr);
346 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
347 cfg |= ((u64)lmac_id << 49);
348 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
349
350 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
351 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
352
353 if (is_multicast_ether_addr(mac_addr)) {
354 cfg &= ~GENMASK_ULL(2, 1);
355 cfg |= CGX_DMAC_MCAST_MODE_CAM;
356 lmac->mcast_filters_count++;
357 } else if (!lmac->mcast_filters_count) {
358 cfg |= CGX_DMAC_MCAST_MODE;
359 }
360
361 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
362
363 return idx;
364 }
365
cgx_lmac_addr_reset(u8 cgx_id,u8 lmac_id)366 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
367 {
368 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
369 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
370 struct mac_ops *mac_ops;
371 u8 index = 0, id;
372 u64 cfg;
373
374 if (!lmac)
375 return -ENODEV;
376
377 mac_ops = cgx_dev->mac_ops;
378 /* Restore index 0 to its default init value as done during
379 * cgx_lmac_init
380 */
381 set_bit(0, lmac->mac_to_index_bmap.bmap);
382
383 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
384
385 index = id * lmac->mac_to_index_bmap.max + index;
386 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
387
388 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
389 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
390 cfg &= ~CGX_DMAC_CAM_ACCEPT;
391 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
392 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
393
394 return 0;
395 }
396
397 /* Allows caller to change macaddress associated with index
398 * in dmac filter table including index 0 reserved for
399 * interface mac address
400 */
cgx_lmac_addr_update(u8 cgx_id,u8 lmac_id,u8 * mac_addr,u8 index)401 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
402 {
403 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
404 struct mac_ops *mac_ops;
405 struct lmac *lmac;
406 u64 cfg;
407 int id;
408
409 lmac = lmac_pdata(lmac_id, cgx_dev);
410 if (!lmac)
411 return -ENODEV;
412
413 mac_ops = cgx_dev->mac_ops;
414 /* Validate the index */
415 if (index >= lmac->mac_to_index_bmap.max)
416 return -EINVAL;
417
418 /* ensure index is already set */
419 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
420 return -EINVAL;
421
422 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
423
424 index = id * lmac->mac_to_index_bmap.max + index;
425
426 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
427 cfg &= ~CGX_RX_DMAC_ADR_MASK;
428 cfg |= ether_addr_to_u64(mac_addr);
429
430 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
431 return 0;
432 }
433
cgx_lmac_addr_del(u8 cgx_id,u8 lmac_id,u8 index)434 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
435 {
436 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
437 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
438 struct mac_ops *mac_ops;
439 u8 mac[ETH_ALEN];
440 u64 cfg;
441 int id;
442
443 if (!lmac)
444 return -ENODEV;
445
446 mac_ops = cgx_dev->mac_ops;
447 /* Validate the index */
448 if (index >= lmac->mac_to_index_bmap.max)
449 return -EINVAL;
450
451 /* Skip deletion for reserved index i.e. index 0 */
452 if (index == 0)
453 return 0;
454
455 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
456
457 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
458
459 index = id * lmac->mac_to_index_bmap.max + index;
460
461 /* Read MAC address to check whether it is ucast or mcast */
462 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
463
464 u64_to_ether_addr(cfg, mac);
465 if (is_multicast_ether_addr(mac))
466 lmac->mcast_filters_count--;
467
468 if (!lmac->mcast_filters_count) {
469 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
470 cfg &= ~GENMASK_ULL(2, 1);
471 cfg |= CGX_DMAC_MCAST_MODE;
472 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
473 }
474
475 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
476
477 return 0;
478 }
479
cgx_lmac_addr_max_entries_get(u8 cgx_id,u8 lmac_id)480 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
481 {
482 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
483 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
484
485 if (lmac)
486 return lmac->mac_to_index_bmap.max;
487
488 return 0;
489 }
490
cgx_lmac_addr_get(u8 cgx_id,u8 lmac_id)491 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
492 {
493 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
494 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
495 struct mac_ops *mac_ops;
496 int index;
497 u64 cfg;
498 int id;
499
500 mac_ops = cgx_dev->mac_ops;
501
502 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
503
504 index = id * lmac->mac_to_index_bmap.max;
505
506 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
507 return cfg & CGX_RX_DMAC_ADR_MASK;
508 }
509
cgx_set_pkind(void * cgxd,u8 lmac_id,int pkind)510 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
511 {
512 struct cgx *cgx = cgxd;
513
514 if (!is_lmac_valid(cgx, lmac_id))
515 return -ENODEV;
516
517 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F));
518 return 0;
519 }
520
cgx_get_lmac_type(void * cgxd,int lmac_id)521 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
522 {
523 struct cgx *cgx = cgxd;
524 u64 cfg;
525
526 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
527 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
528 }
529
cgx_get_lmac_fifo_len(void * cgxd,int lmac_id)530 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
531 {
532 struct cgx *cgx = cgxd;
533 u8 num_lmacs;
534 u32 fifo_len;
535
536 fifo_len = cgx->fifo_len;
537 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
538
539 switch (num_lmacs) {
540 case 1:
541 return fifo_len;
542 case 2:
543 return fifo_len / 2;
544 case 3:
545 /* LMAC0 gets half of the FIFO, reset 1/4th */
546 if (lmac_id == 0)
547 return fifo_len / 2;
548 return fifo_len / 4;
549 case 4:
550 default:
551 return fifo_len / 4;
552 }
553 return 0;
554 }
555
556 /* Configure CGX LMAC in internal loopback mode */
cgx_lmac_internal_loopback(void * cgxd,int lmac_id,bool enable)557 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
558 {
559 struct cgx *cgx = cgxd;
560 struct lmac *lmac;
561 u64 cfg;
562
563 if (!is_lmac_valid(cgx, lmac_id))
564 return -ENODEV;
565
566 lmac = lmac_pdata(lmac_id, cgx);
567 if (lmac->lmac_type == LMAC_MODE_SGMII ||
568 lmac->lmac_type == LMAC_MODE_QSGMII) {
569 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
570 if (enable)
571 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
572 else
573 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
574 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
575 } else {
576 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
577 if (enable)
578 cfg |= CGXX_SPUX_CONTROL1_LBK;
579 else
580 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
581 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
582 }
583 return 0;
584 }
585
cgx_lmac_promisc_config(int cgx_id,int lmac_id,bool enable)586 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
587 {
588 struct cgx *cgx = cgx_get_pdata(cgx_id);
589 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
590 struct mac_ops *mac_ops;
591 u16 max_dmac;
592 int index, i;
593 u64 cfg = 0;
594 int id;
595
596 if (!cgx || !lmac)
597 return;
598
599 max_dmac = lmac->mac_to_index_bmap.max;
600 id = get_sequence_id_of_lmac(cgx, lmac_id);
601
602 mac_ops = cgx->mac_ops;
603 if (enable) {
604 /* Enable promiscuous mode on LMAC */
605 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
606 cfg &= ~CGX_DMAC_CAM_ACCEPT;
607 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
608 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
609
610 for (i = 0; i < max_dmac; i++) {
611 index = id * max_dmac + i;
612 cfg = cgx_read(cgx, 0,
613 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
614 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
615 cgx_write(cgx, 0,
616 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
617 }
618 } else {
619 /* Disable promiscuous mode */
620 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
621 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
622 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
623 for (i = 0; i < max_dmac; i++) {
624 index = id * max_dmac + i;
625 cfg = cgx_read(cgx, 0,
626 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
627 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
628 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
629 cgx_write(cgx, 0,
630 (CGXX_CMRX_RX_DMAC_CAM0 +
631 index * 0x8),
632 cfg);
633 }
634 }
635 }
636 }
637
cgx_lmac_get_pause_frm_status(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)638 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
639 u8 *tx_pause, u8 *rx_pause)
640 {
641 struct cgx *cgx = cgxd;
642 u64 cfg;
643
644 if (is_dev_rpm(cgx))
645 return 0;
646
647 if (!is_lmac_valid(cgx, lmac_id))
648 return -ENODEV;
649
650 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
651 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
652
653 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
654 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
655 return 0;
656 }
657
658 /* Enable or disable forwarding received pause frames to Tx block */
cgx_lmac_enadis_rx_pause_fwding(void * cgxd,int lmac_id,bool enable)659 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
660 {
661 struct cgx *cgx = cgxd;
662 u8 rx_pause, tx_pause;
663 bool is_pfc_enabled;
664 struct lmac *lmac;
665 u64 cfg;
666
667 if (!cgx)
668 return;
669
670 lmac = lmac_pdata(lmac_id, cgx);
671 if (!lmac)
672 return;
673
674 /* Pause frames are not enabled just return */
675 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
676 return;
677
678 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause);
679 is_pfc_enabled = rx_pause ? false : true;
680
681 if (enable) {
682 if (!is_pfc_enabled) {
683 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
684 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
685 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
686
687 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
688 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
689 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
690 } else {
691 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
692 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN;
693 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
694 }
695 } else {
696
697 if (!is_pfc_enabled) {
698 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
699 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
700 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
701
702 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
703 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
704 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
705 } else {
706 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
707 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN;
708 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
709 }
710 }
711 }
712
cgx_get_rx_stats(void * cgxd,int lmac_id,int idx,u64 * rx_stat)713 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
714 {
715 struct cgx *cgx = cgxd;
716
717 if (!is_lmac_valid(cgx, lmac_id))
718 return -ENODEV;
719
720 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
721 if (idx >= CGX_RX_STAT_GLOBAL_INDEX)
722 lmac_id = 0;
723
724 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
725 return 0;
726 }
727
cgx_get_tx_stats(void * cgxd,int lmac_id,int idx,u64 * tx_stat)728 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
729 {
730 struct cgx *cgx = cgxd;
731
732 if (!is_lmac_valid(cgx, lmac_id))
733 return -ENODEV;
734 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
735 return 0;
736 }
737
cgx_features_get(void * cgxd)738 u64 cgx_features_get(void *cgxd)
739 {
740 return ((struct cgx *)cgxd)->hw_features;
741 }
742
cgx_stats_reset(void * cgxd,int lmac_id)743 int cgx_stats_reset(void *cgxd, int lmac_id)
744 {
745 struct cgx *cgx = cgxd;
746 int stat_id;
747
748 if (!is_lmac_valid(cgx, lmac_id))
749 return -ENODEV;
750
751 for (stat_id = 0 ; stat_id < CGX_RX_STATS_COUNT; stat_id++) {
752 if (stat_id >= CGX_RX_STAT_GLOBAL_INDEX)
753 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
754 cgx_write(cgx, 0,
755 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
756 else
757 cgx_write(cgx, lmac_id,
758 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
759 }
760
761 for (stat_id = 0 ; stat_id < CGX_TX_STATS_COUNT; stat_id++)
762 cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0);
763
764 return 0;
765 }
766
cgx_set_fec_stats_count(struct cgx_link_user_info * linfo)767 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
768 {
769 if (!linfo->fec)
770 return 0;
771
772 switch (linfo->lmac_type_id) {
773 case LMAC_MODE_SGMII:
774 case LMAC_MODE_XAUI:
775 case LMAC_MODE_RXAUI:
776 case LMAC_MODE_QSGMII:
777 return 0;
778 case LMAC_MODE_10G_R:
779 case LMAC_MODE_25G_R:
780 case LMAC_MODE_100G_R:
781 case LMAC_MODE_USXGMII:
782 return 1;
783 case LMAC_MODE_40G_R:
784 return 4;
785 case LMAC_MODE_50G_R:
786 if (linfo->fec == OTX2_FEC_BASER)
787 return 2;
788 else
789 return 1;
790 default:
791 return 0;
792 }
793 }
794
cgx_get_fec_stats(void * cgxd,int lmac_id,struct cgx_fec_stats_rsp * rsp)795 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
796 {
797 int stats, fec_stats_count = 0;
798 int corr_reg, uncorr_reg;
799 struct cgx *cgx = cgxd;
800
801 if (!is_lmac_valid(cgx, lmac_id))
802 return -ENODEV;
803
804 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
805 return 0;
806
807 fec_stats_count =
808 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
809 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
810 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
811 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
812 } else {
813 corr_reg = CGXX_SPUX_RSFEC_CORR;
814 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
815 }
816 for (stats = 0; stats < fec_stats_count; stats++) {
817 rsp->fec_corr_blks +=
818 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
819 rsp->fec_uncorr_blks +=
820 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
821 }
822 return 0;
823 }
824
cgx_lmac_rx_tx_enable(void * cgxd,int lmac_id,bool enable)825 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
826 {
827 struct cgx *cgx = cgxd;
828 u64 cfg;
829
830 if (!is_lmac_valid(cgx, lmac_id))
831 return -ENODEV;
832
833 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
834 if (enable)
835 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
836 else
837 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
838 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
839 return 0;
840 }
841
cgx_lmac_tx_enable(void * cgxd,int lmac_id,bool enable)842 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
843 {
844 struct cgx *cgx = cgxd;
845 u64 cfg, last;
846
847 if (!is_lmac_valid(cgx, lmac_id))
848 return -ENODEV;
849
850 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
851 last = cfg;
852 if (enable)
853 cfg |= DATA_PKT_TX_EN;
854 else
855 cfg &= ~DATA_PKT_TX_EN;
856
857 if (cfg != last)
858 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
859 return !!(last & DATA_PKT_TX_EN);
860 }
861
cgx_lmac_enadis_pause_frm(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause)862 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
863 u8 tx_pause, u8 rx_pause)
864 {
865 struct cgx *cgx = cgxd;
866 u64 cfg;
867
868 if (is_dev_rpm(cgx))
869 return 0;
870
871 if (!is_lmac_valid(cgx, lmac_id))
872 return -ENODEV;
873
874 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
875 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
876 cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0;
877 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
878
879 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
880 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
881 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
882 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
883
884 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
885 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
886 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
887 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
888
889 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
890 if (tx_pause) {
891 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
892 } else {
893 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
894 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
895 }
896 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
897 return 0;
898 }
899
cgx_lmac_pause_frm_config(void * cgxd,int lmac_id,bool enable)900 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
901 {
902 struct cgx *cgx = cgxd;
903 u64 cfg;
904
905 if (!is_lmac_valid(cgx, lmac_id))
906 return;
907
908 if (enable) {
909 /* Set pause time and interval */
910 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
911 DEFAULT_PAUSE_TIME);
912 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
913 cfg &= ~0xFFFFULL;
914 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
915 cfg | (DEFAULT_PAUSE_TIME / 2));
916
917 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
918 DEFAULT_PAUSE_TIME);
919
920 cfg = cgx_read(cgx, lmac_id,
921 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
922 cfg &= ~0xFFFFULL;
923 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
924 cfg | (DEFAULT_PAUSE_TIME / 2));
925 }
926
927 /* ALL pause frames received are completely ignored */
928 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
929 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
930 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
931
932 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
933 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
934 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
935
936 /* Disable pause frames transmission */
937 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
938 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
939 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
940
941 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
942 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
943 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
944 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
945
946 /* Disable all PFC classes by default */
947 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
948 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
949 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
950 }
951
verify_lmac_fc_cfg(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,int pfvf_idx)952 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
953 int pfvf_idx)
954 {
955 struct cgx *cgx = cgxd;
956 struct lmac *lmac;
957
958 lmac = lmac_pdata(lmac_id, cgx);
959 if (!lmac)
960 return -ENODEV;
961
962 if (!rx_pause)
963 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
964 else
965 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
966
967 if (!tx_pause)
968 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
969 else
970 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
971
972 /* check if other pfvfs are using flow control */
973 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) {
974 dev_warn(&cgx->pdev->dev,
975 "Receive Flow control disable not permitted as its used by other PFVFs\n");
976 return -EPERM;
977 }
978
979 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) {
980 dev_warn(&cgx->pdev->dev,
981 "Transmit Flow control disable not permitted as its used by other PFVFs\n");
982 return -EPERM;
983 }
984
985 return 0;
986 }
987
cgx_lmac_pfc_config(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,u16 pfc_en)988 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,
989 u8 rx_pause, u16 pfc_en)
990 {
991 struct cgx *cgx = cgxd;
992 u64 cfg;
993
994 if (!is_lmac_valid(cgx, lmac_id))
995 return -ENODEV;
996
997 /* Return as no traffic classes are requested */
998 if (tx_pause && !pfc_en)
999 return 0;
1000
1001 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1002 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg);
1003
1004 if (rx_pause) {
1005 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |
1006 CGXX_SMUX_CBFC_CTL_BCK_EN |
1007 CGXX_SMUX_CBFC_CTL_DRP_EN);
1008 } else {
1009 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |
1010 CGXX_SMUX_CBFC_CTL_BCK_EN |
1011 CGXX_SMUX_CBFC_CTL_DRP_EN);
1012 }
1013
1014 if (tx_pause) {
1015 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;
1016 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);
1017 } else {
1018 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;
1019 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
1020 }
1021
1022 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
1023
1024 /* Write source MAC address which will be filled into PFC packet */
1025 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);
1026 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
1027
1028 return 0;
1029 }
1030
cgx_lmac_get_pfc_frm_cfg(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)1031 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
1032 u8 *rx_pause)
1033 {
1034 struct cgx *cgx = cgxd;
1035 u64 cfg;
1036
1037 if (!is_lmac_valid(cgx, lmac_id))
1038 return -ENODEV;
1039
1040 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1041
1042 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN);
1043 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN);
1044
1045 return 0;
1046 }
1047
cgx_lmac_ptp_config(void * cgxd,int lmac_id,bool enable)1048 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
1049 {
1050 struct cgx *cgx = cgxd;
1051 u64 cfg;
1052
1053 if (!cgx)
1054 return;
1055
1056 if (enable) {
1057 /* Enable inbound PTP timestamping */
1058 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1059 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1060 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1061
1062 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1063 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1064 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1065 } else {
1066 /* Disable inbound PTP stamping */
1067 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1068 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1069 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1070
1071 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1072 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1073 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1074 }
1075 }
1076
1077 /* CGX Firmware interface low level support */
cgx_fwi_cmd_send(u64 req,u64 * resp,struct lmac * lmac)1078 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
1079 {
1080 struct cgx *cgx = lmac->cgx;
1081 struct device *dev;
1082 int err = 0;
1083 u64 cmd;
1084
1085 /* Ensure no other command is in progress */
1086 err = mutex_lock_interruptible(&lmac->cmd_lock);
1087 if (err)
1088 return err;
1089
1090 /* Ensure command register is free */
1091 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
1092 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
1093 err = -EBUSY;
1094 goto unlock;
1095 }
1096
1097 /* Update ownership in command request */
1098 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
1099
1100 /* Mark this lmac as pending, before we start */
1101 lmac->cmd_pend = true;
1102
1103 /* Start command in hardware */
1104 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
1105
1106 /* Ensure command is completed without errors */
1107 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
1108 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
1109 dev = &cgx->pdev->dev;
1110 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n",
1111 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req));
1112 err = LMAC_AF_ERR_CMD_TIMEOUT;
1113 goto unlock;
1114 }
1115
1116 /* we have a valid command response */
1117 smp_rmb(); /* Ensure the latest updates are visible */
1118 *resp = lmac->resp;
1119
1120 unlock:
1121 mutex_unlock(&lmac->cmd_lock);
1122
1123 return err;
1124 }
1125
cgx_fwi_cmd_generic(u64 req,u64 * resp,struct cgx * cgx,int lmac_id)1126 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
1127 {
1128 struct lmac *lmac;
1129 int err;
1130
1131 lmac = lmac_pdata(lmac_id, cgx);
1132 if (!lmac)
1133 return -ENODEV;
1134
1135 err = cgx_fwi_cmd_send(req, resp, lmac);
1136
1137 /* Check for valid response */
1138 if (!err) {
1139 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
1140 return -EIO;
1141 else
1142 return 0;
1143 }
1144
1145 return err;
1146 }
1147
cgx_link_usertable_index_map(int speed)1148 static int cgx_link_usertable_index_map(int speed)
1149 {
1150 switch (speed) {
1151 case SPEED_10:
1152 return CGX_LINK_10M;
1153 case SPEED_100:
1154 return CGX_LINK_100M;
1155 case SPEED_1000:
1156 return CGX_LINK_1G;
1157 case SPEED_2500:
1158 return CGX_LINK_2HG;
1159 case SPEED_5000:
1160 return CGX_LINK_5G;
1161 case SPEED_10000:
1162 return CGX_LINK_10G;
1163 case SPEED_20000:
1164 return CGX_LINK_20G;
1165 case SPEED_25000:
1166 return CGX_LINK_25G;
1167 case SPEED_40000:
1168 return CGX_LINK_40G;
1169 case SPEED_50000:
1170 return CGX_LINK_50G;
1171 case 80000:
1172 return CGX_LINK_80G;
1173 case SPEED_100000:
1174 return CGX_LINK_100G;
1175 case SPEED_UNKNOWN:
1176 return CGX_LINK_NONE;
1177 }
1178 return CGX_LINK_NONE;
1179 }
1180
set_mod_args(struct cgx_set_link_mode_args * args,u32 speed,u8 duplex,u8 autoneg,u64 mode)1181 static void set_mod_args(struct cgx_set_link_mode_args *args,
1182 u32 speed, u8 duplex, u8 autoneg, u64 mode)
1183 {
1184 int mode_baseidx;
1185 u8 cgx_mode;
1186
1187 if (args->multimode) {
1188 args->mode |= mode;
1189 return;
1190 }
1191
1192 /* Derive mode_base_idx and mode fields based
1193 * on cgx_mode value
1194 */
1195 cgx_mode = find_first_bit((unsigned long *)&mode,
1196 CGX_MODE_MAX);
1197 args->mode = mode;
1198 mode_baseidx = cgx_mode - 41;
1199 if (mode_baseidx > 0) {
1200 args->mode_baseidx = 1;
1201 args->mode = BIT_ULL(mode_baseidx);
1202 }
1203 }
1204
otx2_map_ethtool_link_modes(u64 bitmask,struct cgx_set_link_mode_args * args)1205 static void otx2_map_ethtool_link_modes(u64 bitmask,
1206 struct cgx_set_link_mode_args *args)
1207 {
1208 switch (bitmask) {
1209 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1210 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
1211 break;
1212 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1213 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
1214 break;
1215 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1216 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
1217 break;
1218 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1219 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
1220 break;
1221 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1222 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1223 break;
1224 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1225 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1226 break;
1227 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1228 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1229 break;
1230 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1231 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1232 break;
1233 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1234 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1235 break;
1236 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1237 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1238 break;
1239 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1240 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1241 break;
1242 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1243 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1244 break;
1245 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1246 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1247 break;
1248 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1249 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1250 break;
1251 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1252 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1253 break;
1254 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1255 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1256 break;
1257 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1258 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1259 break;
1260 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1261 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1262 break;
1263 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1264 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1265 break;
1266 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1267 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1268 break;
1269 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1270 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1271 break;
1272 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1273 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1274 break;
1275 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1276 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1277 break;
1278 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1279 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1280 break;
1281 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1282 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1283 break;
1284 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1285 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1286 break;
1287 default:
1288 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1289 break;
1290 }
1291 }
1292
link_status_user_format(u64 lstat,struct cgx_link_user_info * linfo,struct cgx * cgx,u8 lmac_id)1293 static inline void link_status_user_format(u64 lstat,
1294 struct cgx_link_user_info *linfo,
1295 struct cgx *cgx, u8 lmac_id)
1296 {
1297 unsigned int speed;
1298
1299 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1300 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1301 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1302 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1303 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat);
1304
1305 speed = FIELD_GET(RESP_LINKSTAT_SPEED, lstat);
1306 linfo->speed = speed < ARRAY_SIZE(cgx_speed_mbps) ?
1307 cgx_speed_mbps[speed] : 0;
1308
1309 if (linfo->lmac_type_id >= LMAC_MODE_MAX) {
1310 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d",
1311 linfo->lmac_type_id, cgx->cgx_id, lmac_id);
1312 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type));
1313 return;
1314 }
1315
1316 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id],
1317 sizeof(linfo->lmac_type));
1318 }
1319
1320 /* Hardware event handlers */
cgx_link_change_handler(u64 lstat,struct lmac * lmac)1321 static inline void cgx_link_change_handler(u64 lstat,
1322 struct lmac *lmac)
1323 {
1324 struct cgx_link_user_info *linfo;
1325 struct cgx *cgx = lmac->cgx;
1326 struct cgx_link_event event;
1327 struct device *dev;
1328 int err_type;
1329
1330 dev = &cgx->pdev->dev;
1331
1332 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1333 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1334
1335 event.cgx_id = cgx->cgx_id;
1336 event.lmac_id = lmac->lmac_id;
1337
1338 /* update the local copy of link status */
1339 lmac->link_info = event.link_uinfo;
1340 linfo = &lmac->link_info;
1341
1342 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1343 return;
1344
1345 /* Ensure callback doesn't get unregistered until we finish it */
1346 spin_lock(&lmac->event_cb_lock);
1347
1348 if (!lmac->event_cb.notify_link_chg) {
1349 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1350 cgx->cgx_id, lmac->lmac_id);
1351 if (err_type != CGX_ERR_NONE) {
1352 dev_err(dev, "cgx port %d:%d Link error %d\n",
1353 cgx->cgx_id, lmac->lmac_id, err_type);
1354 }
1355 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1356 cgx->cgx_id, lmac->lmac_id,
1357 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1358 goto err;
1359 }
1360
1361 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1362 dev_err(dev, "event notification failure\n");
1363 err:
1364 spin_unlock(&lmac->event_cb_lock);
1365 }
1366
cgx_cmdresp_is_linkevent(u64 event)1367 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1368 {
1369 u8 id;
1370
1371 id = FIELD_GET(EVTREG_ID, event);
1372 if (id == CGX_CMD_LINK_BRING_UP ||
1373 id == CGX_CMD_LINK_BRING_DOWN ||
1374 id == CGX_CMD_MODE_CHANGE)
1375 return true;
1376 else
1377 return false;
1378 }
1379
cgx_event_is_linkevent(u64 event)1380 static inline bool cgx_event_is_linkevent(u64 event)
1381 {
1382 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1383 return true;
1384 else
1385 return false;
1386 }
1387
cgx_fwi_event_handler(int irq,void * data)1388 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1389 {
1390 u64 event, offset, clear_bit;
1391 struct lmac *lmac = data;
1392 struct cgx *cgx;
1393
1394 cgx = lmac->cgx;
1395
1396 /* Clear SW_INT for RPM and CMR_INT for CGX */
1397 offset = cgx->mac_ops->int_register;
1398 clear_bit = cgx->mac_ops->int_ena_bit;
1399
1400 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1401
1402 if (!FIELD_GET(EVTREG_ACK, event))
1403 return IRQ_NONE;
1404
1405 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1406 case CGX_EVT_CMD_RESP:
1407 /* Copy the response. Since only one command is active at a
1408 * time, there is no way a response can get overwritten
1409 */
1410 lmac->resp = event;
1411 /* Ensure response is updated before thread context starts */
1412 smp_wmb();
1413
1414 /* There wont be separate events for link change initiated from
1415 * software; Hence report the command responses as events
1416 */
1417 if (cgx_cmdresp_is_linkevent(event))
1418 cgx_link_change_handler(event, lmac);
1419
1420 /* Release thread waiting for completion */
1421 lmac->cmd_pend = false;
1422 wake_up(&lmac->wq_cmd_cmplt);
1423 break;
1424 case CGX_EVT_ASYNC:
1425 if (cgx_event_is_linkevent(event))
1426 cgx_link_change_handler(event, lmac);
1427 break;
1428 }
1429
1430 /* Any new event or command response will be posted by firmware
1431 * only after the current status is acked.
1432 * Ack the interrupt register as well.
1433 */
1434 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1435 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1436
1437 return IRQ_HANDLED;
1438 }
1439
1440 /* APIs for PHY management using CGX firmware interface */
1441
1442 /* callback registration for hardware events like link change */
cgx_lmac_evh_register(struct cgx_event_cb * cb,void * cgxd,int lmac_id)1443 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1444 {
1445 struct cgx *cgx = cgxd;
1446 struct lmac *lmac;
1447
1448 lmac = lmac_pdata(lmac_id, cgx);
1449 if (!lmac)
1450 return -ENODEV;
1451
1452 lmac->event_cb = *cb;
1453
1454 return 0;
1455 }
1456
cgx_lmac_evh_unregister(void * cgxd,int lmac_id)1457 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1458 {
1459 struct lmac *lmac;
1460 unsigned long flags;
1461 struct cgx *cgx = cgxd;
1462
1463 lmac = lmac_pdata(lmac_id, cgx);
1464 if (!lmac)
1465 return -ENODEV;
1466
1467 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1468 lmac->event_cb.notify_link_chg = NULL;
1469 lmac->event_cb.data = NULL;
1470 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1471
1472 return 0;
1473 }
1474
cgx_get_fwdata_base(u64 * base)1475 int cgx_get_fwdata_base(u64 *base)
1476 {
1477 u64 req = 0, resp;
1478 struct cgx *cgx;
1479 int first_lmac;
1480 int err;
1481
1482 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1483 if (!cgx)
1484 return -ENXIO;
1485
1486 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1487 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1488 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1489 if (!err)
1490 *base = FIELD_GET(RESP_FWD_BASE, resp);
1491
1492 return err;
1493 }
1494
cgx_set_link_mode(void * cgxd,struct cgx_set_link_mode_args args,struct cgx_lmac_fwdata_s * linkmodes,int cgx_id,int lmac_id)1495 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1496 struct cgx_lmac_fwdata_s *linkmodes,
1497 int cgx_id, int lmac_id)
1498 {
1499 struct cgx *cgx = cgxd;
1500 u64 req = 0, resp;
1501 u8 bit;
1502
1503 if (!cgx)
1504 return -ENODEV;
1505
1506 for_each_set_bit(bit, args.advertising,
1507 __ETHTOOL_LINK_MODE_MASK_NBITS)
1508 otx2_map_ethtool_link_modes(bit, &args);
1509
1510 if (args.multimode) {
1511 if (linkmodes->advertised_link_modes_own != CGX_CMD_OWN_NS)
1512 return -EBUSY;
1513
1514 linkmodes->advertised_link_modes = args.mode;
1515 /* Update ownership */
1516 linkmodes->advertised_link_modes_own = CGX_CMD_OWN_FIRMWARE;
1517 args.mode = GENMASK_ULL(41, 0);
1518 }
1519
1520 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1521 req = FIELD_SET(CMDMODECHANGE_SPEED,
1522 cgx_link_usertable_index_map(args.speed), req);
1523 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1524 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1525 req = FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req);
1526 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1527
1528 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1529 }
cgx_set_fec(u64 fec,int cgx_id,int lmac_id)1530 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1531 {
1532 u64 req = 0, resp;
1533 struct cgx *cgx;
1534 int err = 0;
1535
1536 cgx = cgx_get_pdata(cgx_id);
1537 if (!cgx)
1538 return -ENXIO;
1539
1540 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1541 req = FIELD_SET(CMDSETFEC, fec, req);
1542 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1543 if (err)
1544 return err;
1545
1546 cgx->lmac_idmap[lmac_id]->link_info.fec =
1547 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1548 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1549 }
1550
cgx_get_phy_fec_stats(void * cgxd,int lmac_id)1551 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1552 {
1553 struct cgx *cgx = cgxd;
1554 u64 req = 0, resp;
1555
1556 if (!cgx)
1557 return -ENODEV;
1558
1559 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1560 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1561 }
1562
cgx_fwi_link_change(struct cgx * cgx,int lmac_id,bool enable)1563 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1564 {
1565 u64 req = 0;
1566 u64 resp;
1567
1568 if (enable) {
1569 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1570 /* On CN10K firmware offloads link bring up/down operations to ECP
1571 * On Octeontx2 link operations are handled by firmware itself
1572 * which can cause mbox errors so configure maximum time firmware
1573 * poll for Link as 1000 ms
1574 */
1575 if (!is_dev_rpm(cgx))
1576 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req);
1577
1578 } else {
1579 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1580 }
1581 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1582 }
1583
cgx_fwi_read_version(u64 * resp,struct cgx * cgx)1584 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1585 {
1586 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1587 u64 req = 0;
1588
1589 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1590 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1591 }
1592
cgx_lmac_verify_fwi_version(struct cgx * cgx)1593 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1594 {
1595 struct device *dev = &cgx->pdev->dev;
1596 int major_ver, minor_ver;
1597 u64 resp;
1598 int err;
1599
1600 if (!cgx->lmac_count)
1601 return 0;
1602
1603 err = cgx_fwi_read_version(&resp, cgx);
1604 if (err)
1605 return err;
1606
1607 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1608 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1609 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1610 major_ver, minor_ver);
1611 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1612 return -EIO;
1613 else
1614 return 0;
1615 }
1616
cgx_lmac_linkup_work(struct work_struct * work)1617 static void cgx_lmac_linkup_work(struct work_struct *work)
1618 {
1619 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1620 struct device *dev = &cgx->pdev->dev;
1621 int i, err;
1622
1623 /* Do Link up for all the enabled lmacs */
1624 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1625 err = cgx_fwi_link_change(cgx, i, true);
1626 if (err)
1627 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1628 cgx->cgx_id, i);
1629 }
1630 }
1631
cgx_lmac_linkup_start(void * cgxd)1632 int cgx_lmac_linkup_start(void *cgxd)
1633 {
1634 struct cgx *cgx = cgxd;
1635
1636 if (!cgx)
1637 return -ENODEV;
1638
1639 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1640
1641 return 0;
1642 }
1643
cgx_lmac_reset(void * cgxd,int lmac_id,u8 pf_req_flr)1644 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr)
1645 {
1646 struct cgx *cgx = cgxd;
1647 u64 cfg;
1648
1649 if (!is_lmac_valid(cgx, lmac_id))
1650 return -ENODEV;
1651
1652 /* Resetting PFC related CSRs */
1653 cfg = 0xff;
1654 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg);
1655
1656 if (pf_req_flr)
1657 cgx_lmac_internal_loopback(cgxd, lmac_id, false);
1658 return 0;
1659 }
1660
cgx_configure_interrupt(struct cgx * cgx,struct lmac * lmac,int cnt,bool req_free)1661 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1662 int cnt, bool req_free)
1663 {
1664 struct mac_ops *mac_ops = cgx->mac_ops;
1665 u64 offset, ena_bit;
1666 unsigned int irq;
1667 int err;
1668
1669 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1670 cnt * mac_ops->irq_offset);
1671 offset = mac_ops->int_set_reg;
1672 ena_bit = mac_ops->int_ena_bit;
1673
1674 if (req_free) {
1675 free_irq(irq, lmac);
1676 return 0;
1677 }
1678
1679 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1680 if (err)
1681 return err;
1682
1683 /* Enable interrupt */
1684 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1685 return 0;
1686 }
1687
cgx_get_nr_lmacs(void * cgxd)1688 int cgx_get_nr_lmacs(void *cgxd)
1689 {
1690 struct cgx *cgx = cgxd;
1691
1692 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1693 }
1694
cgx_get_lmacid(void * cgxd,u8 lmac_index)1695 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1696 {
1697 struct cgx *cgx = cgxd;
1698
1699 return cgx->lmac_idmap[lmac_index]->lmac_id;
1700 }
1701
cgx_get_lmac_bmap(void * cgxd)1702 unsigned long cgx_get_lmac_bmap(void *cgxd)
1703 {
1704 struct cgx *cgx = cgxd;
1705
1706 return cgx->lmac_bmap;
1707 }
1708
cgx_lmac_init(struct cgx * cgx)1709 static int cgx_lmac_init(struct cgx *cgx)
1710 {
1711 u8 max_dmac_filters;
1712 struct lmac *lmac;
1713 int err, filter;
1714 unsigned int i;
1715 u64 lmac_list;
1716
1717 /* lmac_list specifies which lmacs are enabled
1718 * when bit n is set to 1, LMAC[n] is enabled
1719 */
1720 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1721 if (is_dev_rpm2(cgx))
1722 lmac_list =
1723 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL;
1724 else
1725 lmac_list =
1726 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1727 }
1728
1729 if (cgx->lmac_count > cgx->max_lmac_per_mac)
1730 cgx->lmac_count = cgx->max_lmac_per_mac;
1731
1732 for (i = 0; i < cgx->lmac_count; i++) {
1733 lmac = kzalloc_obj(struct lmac);
1734 if (!lmac)
1735 return -ENOMEM;
1736 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1737 if (!lmac->name) {
1738 err = -ENOMEM;
1739 goto err_lmac_free;
1740 }
1741 sprintf(lmac->name, "cgx_fwi_%u_%u", cgx->cgx_id, i);
1742 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1743 lmac->lmac_id = __ffs64(lmac_list);
1744 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1745 } else {
1746 lmac->lmac_id = i;
1747 }
1748
1749 lmac->cgx = cgx;
1750 lmac->mac_to_index_bmap.max =
1751 cgx->mac_ops->dmac_filter_count /
1752 cgx->lmac_count;
1753
1754 max_dmac_filters = lmac->mac_to_index_bmap.max;
1755
1756 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1757 if (err)
1758 goto err_name_free;
1759
1760 /* Reserve first entry for default MAC address */
1761 set_bit(0, lmac->mac_to_index_bmap.bmap);
1762
1763 lmac->rx_fc_pfvf_bmap.max = 128;
1764 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap);
1765 if (err)
1766 goto err_dmac_bmap_free;
1767
1768 lmac->tx_fc_pfvf_bmap.max = 128;
1769 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap);
1770 if (err)
1771 goto err_rx_fc_bmap_free;
1772
1773 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1774 mutex_init(&lmac->cmd_lock);
1775 spin_lock_init(&lmac->event_cb_lock);
1776 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1777 if (err)
1778 goto err_bitmap_free;
1779
1780 /* Add reference */
1781 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1782 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1783 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1784 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id);
1785
1786 /* Disable stale DMAC filters for sane state */
1787 for (filter = 0; filter < max_dmac_filters; filter++)
1788 cgx_lmac_addr_del(cgx->cgx_id, lmac->lmac_id, filter);
1789
1790 /* As cgx_lmac_addr_del does not clear entry for index 0
1791 * so it needs to be done explicitly
1792 */
1793 cgx_lmac_addr_reset(cgx->cgx_id, lmac->lmac_id);
1794 }
1795
1796 /* Start X2P reset on given MAC block */
1797 cgx->mac_ops->mac_x2p_reset(cgx, true);
1798 return cgx_lmac_verify_fwi_version(cgx);
1799
1800 err_bitmap_free:
1801 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1802 err_rx_fc_bmap_free:
1803 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1804 err_dmac_bmap_free:
1805 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1806 err_name_free:
1807 kfree(lmac->name);
1808 err_lmac_free:
1809 kfree(lmac);
1810 return err;
1811 }
1812
cgx_lmac_exit(struct cgx * cgx)1813 static int cgx_lmac_exit(struct cgx *cgx)
1814 {
1815 struct lmac *lmac;
1816 int i;
1817
1818 if (cgx->cgx_cmd_workq) {
1819 destroy_workqueue(cgx->cgx_cmd_workq);
1820 cgx->cgx_cmd_workq = NULL;
1821 }
1822
1823 /* Free all lmac related resources */
1824 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1825 lmac = cgx->lmac_idmap[i];
1826 if (!lmac)
1827 continue;
1828 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1829 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1830 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1831 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1832 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1833 kfree(lmac->name);
1834 kfree(lmac);
1835 }
1836
1837 return 0;
1838 }
1839
cgx_populate_features(struct cgx * cgx)1840 static void cgx_populate_features(struct cgx *cgx)
1841 {
1842 u64 cfg;
1843
1844 cfg = cgx_read(cgx, 0, CGX_CONST);
1845 cgx->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1846 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg);
1847
1848 if (is_dev_rpm(cgx))
1849 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1850 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1851 else
1852 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1853 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1854 }
1855
cgx_get_rxid_mapoffset(struct cgx * cgx)1856 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx)
1857 {
1858 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM ||
1859 is_dev_rpm2(cgx))
1860 return 0x80;
1861 else
1862 return 0x60;
1863 }
1864
cgx_x2p_reset(void * cgxd,bool enable)1865 static void cgx_x2p_reset(void *cgxd, bool enable)
1866 {
1867 struct cgx *cgx = cgxd;
1868 int lmac_id;
1869 u64 cfg;
1870
1871 if (enable) {
1872 for_each_set_bit(lmac_id, &cgx->lmac_bmap, cgx->max_lmac_per_mac)
1873 cgx->mac_ops->mac_enadis_rx(cgx, lmac_id, false);
1874
1875 usleep_range(1000, 2000);
1876
1877 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1878 cfg |= cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP;
1879 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1880 } else {
1881 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1882 cfg &= ~(cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP);
1883 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1884 }
1885 }
1886
cgx_enadis_rx(void * cgxd,int lmac_id,bool enable)1887 static int cgx_enadis_rx(void *cgxd, int lmac_id, bool enable)
1888 {
1889 struct cgx *cgx = cgxd;
1890 u64 cfg;
1891
1892 if (!is_lmac_valid(cgx, lmac_id))
1893 return -ENODEV;
1894
1895 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
1896 if (enable)
1897 cfg |= DATA_PKT_RX_EN;
1898 else
1899 cfg &= ~DATA_PKT_RX_EN;
1900 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
1901 return 0;
1902 }
1903
1904 static struct mac_ops cgx_mac_ops = {
1905 .name = "cgx",
1906 .csr_offset = 0,
1907 .lmac_offset = 18,
1908 .int_register = CGXX_CMRX_INT,
1909 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1910 .irq_offset = 9,
1911 .int_ena_bit = FW_CGX_INT,
1912 .lmac_fwi = CGX_LMAC_FWI,
1913 .non_contiguous_serdes_lane = false,
1914 .rx_stats_cnt = 9,
1915 .tx_stats_cnt = 18,
1916 .dmac_filter_count = 32,
1917 .get_nr_lmacs = cgx_get_nr_lmacs,
1918 .get_lmac_type = cgx_get_lmac_type,
1919 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1920 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1921 .mac_get_rx_stats = cgx_get_rx_stats,
1922 .mac_get_tx_stats = cgx_get_tx_stats,
1923 .get_fec_stats = cgx_get_fec_stats,
1924 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1925 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1926 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1927 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1928 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1929 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1930 .mac_tx_enable = cgx_lmac_tx_enable,
1931 .pfc_config = cgx_lmac_pfc_config,
1932 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg,
1933 .mac_reset = cgx_lmac_reset,
1934 .mac_stats_reset = cgx_stats_reset,
1935 .mac_x2p_reset = cgx_x2p_reset,
1936 .mac_enadis_rx = cgx_enadis_rx,
1937 };
1938
cgx_probe(struct pci_dev * pdev,const struct pci_device_id * id)1939 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1940 {
1941 struct device *dev = &pdev->dev;
1942 struct cgx *cgx;
1943 int err, nvec;
1944
1945 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1946 if (!cgx)
1947 return -ENOMEM;
1948 cgx->pdev = pdev;
1949
1950 pci_set_drvdata(pdev, cgx);
1951
1952 /* Use mac_ops to get MAC specific features */
1953 if (is_dev_rpm(cgx))
1954 cgx->mac_ops = rpm_get_mac_ops(cgx);
1955 else
1956 cgx->mac_ops = &cgx_mac_ops;
1957
1958 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx);
1959
1960 err = pci_enable_device(pdev);
1961 if (err) {
1962 dev_err(dev, "Failed to enable PCI device\n");
1963 pci_set_drvdata(pdev, NULL);
1964 return err;
1965 }
1966
1967 err = pci_request_regions(pdev, DRV_NAME);
1968 if (err) {
1969 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1970 goto err_disable_device;
1971 }
1972
1973 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
1974 if (err) {
1975 dev_err(dev, "DMA mask config failed, abort\n");
1976 goto err_release_regions;
1977 }
1978
1979 /* MAP configuration registers */
1980 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1981 if (!cgx->reg_base) {
1982 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1983 err = -ENOMEM;
1984 goto err_release_regions;
1985 }
1986
1987 if (!is_cn20k(pdev) &&
1988 !is_cgx_mapped_to_nix(pdev->subsystem_device, cgx->cgx_id)) {
1989 dev_notice(dev, "CGX %d not mapped to NIX, skipping probe\n",
1990 cgx->cgx_id);
1991 err = -ENODEV;
1992 goto err_release_regions;
1993 }
1994
1995 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1996 if (!cgx->lmac_count) {
1997 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id);
1998 err = -EOPNOTSUPP;
1999 goto err_release_regions;
2000 }
2001
2002 nvec = pci_msix_vec_count(cgx->pdev);
2003 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
2004 if (err < 0) {
2005 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
2006 nvec, err);
2007 goto err_release_regions;
2008 }
2009
2010 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
2011 & CGX_ID_MASK;
2012
2013 /* init wq for processing linkup requests */
2014 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
2015 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", WQ_PERCPU, 0);
2016 if (!cgx->cgx_cmd_workq) {
2017 dev_err(dev, "alloc workqueue failed for cgx cmd");
2018 err = -ENOMEM;
2019 goto err_free_irq_vectors;
2020 }
2021
2022 list_add(&cgx->cgx_list, &cgx_list);
2023
2024
2025 cgx_populate_features(cgx);
2026
2027 mutex_init(&cgx->lock);
2028
2029 err = cgx_lmac_init(cgx);
2030 if (err)
2031 goto err_release_lmac;
2032
2033 return 0;
2034
2035 err_release_lmac:
2036 cgx_lmac_exit(cgx);
2037 list_del(&cgx->cgx_list);
2038 err_free_irq_vectors:
2039 pci_free_irq_vectors(pdev);
2040 err_release_regions:
2041 pci_release_regions(pdev);
2042 err_disable_device:
2043 pci_disable_device(pdev);
2044 pci_set_drvdata(pdev, NULL);
2045 return err;
2046 }
2047
cgx_remove(struct pci_dev * pdev)2048 static void cgx_remove(struct pci_dev *pdev)
2049 {
2050 struct cgx *cgx = pci_get_drvdata(pdev);
2051
2052 if (cgx) {
2053 cgx_lmac_exit(cgx);
2054 list_del(&cgx->cgx_list);
2055 }
2056 pci_free_irq_vectors(pdev);
2057 pci_release_regions(pdev);
2058 pci_disable_device(pdev);
2059 pci_set_drvdata(pdev, NULL);
2060 }
2061
2062 struct pci_driver cgx_driver = {
2063 .name = DRV_NAME,
2064 .id_table = cgx_id_table,
2065 .probe = cgx_probe,
2066 .remove = cgx_remove,
2067 };
2068