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Searched refs:cgu (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/clk/ingenic/
H A Dcgu.c30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
106 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
187 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, in ingenic_pll_check_stable() argument
[all …]
H A DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
9 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
10 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
H A Djz4780-cgu.c103 static struct ingenic_cgu *cgu; variable
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
186 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_enable()
187 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_enable()
196 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_disable()
197 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_disable()
[all …]
H A Dx1000-cgu.c62 static struct ingenic_cgu *cgu; variable
70 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
122 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
124 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
127 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
129 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
135 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
136 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_enable()
145 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_disable()
146 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_disable()
[all …]
H A Dx1830-cgu.c55 static struct ingenic_cgu *cgu; variable
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
453 cgu = ingenic_cgu_new(x1830_cgu_clocks, in x1830_cgu_init()
455 if (!cgu) { in x1830_cgu_init()
460 retval = ingenic_cgu_register_clocks(cgu); in x1830_cgu_init()
[all …]
H A Djz4770-cgu.c49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
448 cgu = ingenic_cgu_new(jz4770_cgu_clocks, in jz4770_cgu_init()
450 if (!cgu) { in jz4770_cgu_init()
455 retval = ingenic_cgu_register_clocks(cgu); in jz4770_cgu_init()
[all …]
H A Djz4740-cgu.c48 static struct ingenic_cgu *cgu; variable
258 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
260 if (!cgu) { in jz4740_cgu_init()
265 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
269 ingenic_cgu_register_syscore_ops(cgu); in jz4740_cgu_init()
H A Djz4725b-cgu.c33 static struct ingenic_cgu *cgu; variable
260 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init()
262 if (!cgu) { in jz4725b_cgu_init()
267 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init()
271 ingenic_cgu_register_syscore_ops(cgu); in jz4725b_cgu_init()
H A Djz4755-cgu.c30 static struct ingenic_cgu *cgu; variable
329 cgu = ingenic_cgu_new(jz4755_cgu_clocks, in jz4755_cgu_init()
331 if (!cgu) { in jz4755_cgu_init()
336 retval = ingenic_cgu_register_clocks(cgu); in jz4755_cgu_init()
340 ingenic_cgu_register_syscore_ops(cgu); in jz4755_cgu_init()
H A Djz4760-cgu.c425 struct ingenic_cgu *cgu; in jz4760_cgu_init() local
428 cgu = ingenic_cgu_new(jz4760_cgu_clocks, in jz4760_cgu_init()
430 if (!cgu) { in jz4760_cgu_init()
435 retval = ingenic_cgu_register_clocks(cgu); in jz4760_cgu_init()
439 ingenic_cgu_register_syscore_ops(cgu); in jz4760_cgu_init()
H A Dpm.c39 void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) in ingenic_cgu_register_syscore_ops() argument
42 ingenic_cgu_base = cgu->base; in ingenic_cgu_register_syscore_ops()
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-ccu.txt47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
[all …]
H A Djz4780.dtsi2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
H A Djz4770.dtsi2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
54 compatible = "ingenic,jz4770-cgu", "simple-mfd";
69 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
257 clocks = <&cgu JZ4770_CLK_AIC>;
[all …]
H A Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
70 clocks = <&cgu X1000_CLK_OTGPHY>;
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
[all …]
H A Djz4725b.dtsi2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
[all …]
H A Dx1830.dtsi3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
55 compatible = "ingenic,x1830-cgu", "simple-mfd";
70 clocks = <&cgu X1830_CLK_OTGPHY>;
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
[all …]
H A Dgcw0.dts440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
455 <&cgu JZ4770_CLK_LPCLK_MUX>,
456 <&cgu JZ4770_CLK_MMC0_MUX>,
457 <&cgu JZ4770_CLK_MMC1_MUX>;
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
[all …]
H A Dci20.dts164 &cgu {
169 assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
170 <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
171 <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
173 <&cgu JZ4780_CLK_MPLL>,
174 <&cgu JZ4780_CLK_SSIPLL>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
H A Drs90.dts171 clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
296 &cgu {
298 assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
299 assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
308 assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
[all …]
/linux/arch/mips/generic/
H A Dboard-ingenic.c72 void __iomem *cgu; in ingenic_force_12M_ext() local
94 cgu = ioremap(INGENIC_CGU_BASE, 0x4); in ingenic_force_12M_ext()
95 if (!cgu) in ingenic_force_12M_ext()
98 cpccr = ioread32(cgu); in ingenic_force_12M_ext()
103 iowrite32(cpccr, cgu); in ingenic_force_12M_ext()
105 iounmap(cgu); in ingenic_force_12M_ext()
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c1741 ice_dpll_deinit_direct_pins(bool cgu, struct ice_dpll_pin *pins, int count, in ice_dpll_deinit_direct_pins() argument
1746 if (cgu) { in ice_dpll_deinit_direct_pins()
1772 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, in ice_dpll_init_direct_pins() argument
1782 if (cgu) { in ice_dpll_init_direct_pins()
1888 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu) in ice_dpll_deinit_pins() argument
1899 if (cgu) { in ice_dpll_deinit_pins()
1906 if (cgu) { in ice_dpll_deinit_pins()
1927 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) in ice_dpll_init_pins() argument
1932 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
1938 if (cgu) { in ice_dpll_init_pins()
[all …]
/linux/drivers/clk/x86/
H A DMakefile4 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o

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