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Searched refs:cgs_write_ind_register (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h134 …cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~C…
170 #define cgs_write_ind_register(dev, space, index, value) \ macro
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c761 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); in vega10_program_didt_config_registers()
767 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); in vega10_program_didt_config_registers()
773 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); in vega10_program_didt_config_registers()
844 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); in vega10_didt_set_mask()
851 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); in vega10_didt_set_mask()
858 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); in vega10_didt_set_mask()
865 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); in vega10_didt_set_mask()
872 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); in vega10_didt_set_mask()
H A Dsmu7_hwmgr.c463 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_display_gap()
487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_program_voting_clients()
504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_clear_voting_clients()
1175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_sclk_vce_handshake()
1192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_disable_handshake_uvd()
1235 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); in smu7_enable_sclk_mclk_dpm()
1236 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); in smu7_enable_sclk_mclk_dpm()
1237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); in smu7_enable_sclk_mclk_dpm()
1239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); in smu7_enable_sclk_mclk_dpm()
1240 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); in smu7_enable_sclk_mclk_dpm()
[all …]
H A Dsmu_helper.h167 cgs_write_ind_register(device, port, ix##reg, \
172 cgs_write_ind_register(device, port, ix##reg, \
H A Dsmu7_powertune.c934 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data); in smu7_program_pt_config_registers()
938 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); in smu7_program_pt_config_registers()
942 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); in smu7_program_pt_config_registers()
H A Dsmu8_hwmgr.c957 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_program_voting_clients()
964 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_clear_voting_clients()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
169 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_non_protection_mode()
1769 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1812 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); in fiji_populate_clock_stretcher_data_table()
1951 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_init_smc_table()
2384 cgs_write_ind_register(hwmgr->device, in fiji_update_uvd_smc_table()
2420 cgs_write_ind_register(hwmgr->device, in fiji_update_vce_smc_table()
2585 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in fiji_update_dpm_settings()
2600 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in fiji_update_dpm_settings()
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H A Dpolaris10_smumgr.c216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in polaris10_start_smu_in_protection_mode()
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); in polaris10_start_smu_in_protection_mode()
264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in polaris10_start_smu_in_non_protection_mode()
1706 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); in polaris10_populate_clock_stretcher_data_table()
1749 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + in polaris10_populate_vr_config()
1758 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + in polaris10_populate_vr_config()
1948 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in polaris10_init_smc_table()
2300 cgs_write_ind_register(hwmgr->device, in polaris10_update_uvd_smc_table()
2336 cgs_write_ind_register(hwmgr->device, in polaris10_update_vce_smc_table()
2623 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in polaris10_update_dpm_settings()
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H A Dvegam_smumgr.c116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode()
141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); in vegam_start_smu_in_protection_mode()
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_non_protection_mode()
349 cgs_write_ind_register(hwmgr->device, in vegam_update_uvd_smc_table()
385 cgs_write_ind_register(hwmgr->device, in vegam_update_vce_smc_table()
1542 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); in vegam_populate_clock_stretcher_data_table()
1703 cgs_write_ind_register(hwmgr->device, in vegam_populate_vr_config()
1717 cgs_write_ind_register(hwmgr->device, in vegam_populate_vr_config()
1956 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in vegam_init_smc_table()
H A Dtonga_smumgr.c110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_non_protection_mode()
1698 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
1740 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
2264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_init_smc_table()
2695 cgs_write_ind_register(hwmgr->device, in tonga_update_uvd_smc_table()
2730 cgs_write_ind_register(hwmgr->device, in tonga_update_vce_smc_table()
3184 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in tonga_update_dpm_settings()
3199 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in tonga_update_dpm_settings()
[all …]
H A Dci_smumgr.c1974 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in ci_init_smc_table()
2797 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2812 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2832 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2847 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
H A Dsmu7_smumgr.c334 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_request_smu_load_fw()
H A Diceland_smumgr.c213 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in iceland_smu_upload_firmware_image()
1962 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in iceland_init_smc_table()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h85 cgs_write_ind_register(ctx->cgs_device, addr_space, index, value); in dm_write_index_reg()