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Searched refs:cgs_read_ind_register (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h155 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
159 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
168 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
173 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
H A Dvega10_powertune.c758 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); in vega10_program_didt_config_registers()
764 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); in vega10_program_didt_config_registers()
770 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); in vega10_program_didt_config_registers()
841 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); in vega10_didt_set_mask()
848 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); in vega10_didt_set_mask()
855 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); in vega10_didt_set_mask()
862 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); in vega10_didt_set_mask()
869 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); in vega10_didt_set_mask()
H A Dsmu8_hwmgr.c1578 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1590 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1713 uint32_t val = cgs_read_ind_register(hwmgr->device, in smu8_thermal_get_temperature()
1739 …uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGE… in smu8_read_sensor()
1741 …uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1743 …uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1764 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & in smu8_read_sensor()
1770 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & in smu8_read_sensor()
H A Dsmu7_hwmgr.c217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
454 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_display_gap()
581 tmp = (cgs_read_ind_register(hwmgr->device, in smu7_force_switch_to_arbf0()
1172 soft_register_value = cgs_read_ind_register(hwmgr->device, in smu7_disable_sclk_vce_handshake()
1188 soft_register_value = cgs_read_ind_register(hwmgr->device, in smu7_disable_handshake_uvd()
2544 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); in smu7_thermal_parameter_init()
3986 tmp = cgs_read_ind_register(hwmgr->device, in smu7_get_gpu_power()
4033 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); in smu7_read_sensor()
4582 …uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNT… in smu7_program_display_gap()
4798 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); in smu7_read_clock_registers()
[all …]
H A Dsmu7_powertune.c912 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset); in smu7_program_pt_config_registers()
916 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); in smu7_program_pt_config_registers()
920 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); in smu7_program_pt_config_registers()
/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h134 …cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~C…
168 #define cgs_read_ind_register(dev, space, index) \ macro
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c1678 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1680 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1737 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1810 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); in fiji_populate_clock_stretcher_data_table()
2380 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in fiji_update_uvd_smc_table()
2416 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in fiji_update_vce_smc_table()
2582 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2596 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2617 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2631 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
H A Dvegam_smumgr.c345 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in vegam_update_uvd_smc_table()
381 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in vegam_update_vce_smc_table()
1540 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); in vegam_populate_clock_stretcher_data_table()
1551 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in vegam_is_hw_avfs_present()
H A Dci_smumgr.c190 && (0x20100 <= cgs_read_ind_register(hwmgr->device, in ci_is_smc_ram_running()
2795 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2809 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2830 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2844 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
H A Diceland_smumgr.c211 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in iceland_smu_upload_firmware_image()