/linux/arch/loongarch/mm/ |
H A D | cache.c | 96 unsigned int cfg1; \ 98 cfg1 = read_cpucfg(LOONGARCH_CPUCFG17 + leaf); \ 109 cdesc->ways = ((cfg1 & CPUCFG_CACHE_WAYS_M) >> CPUCFG_CACHE_WAYS) + 1; \ 110 cdesc->sets = 1 << ((cfg1 & CPUCFG_CACHE_SETS_M) >> CPUCFG_CACHE_SETS); \ 111 cdesc->linesz = 1 << ((cfg1 & CPUCFG_CACHE_LSIZE_M) >> CPUCFG_CACHE_LSIZE); \
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/linux/drivers/clk/thead/ |
H A D | clk-th1520-ap.c | 40 u16 cfg1; member 245 unsigned int cfg0, cfg1; in th1520_pll_vco_recalc_rate() local 249 regmap_read(pll->common.map, pll->common.cfg1, &cfg1); in th1520_pll_vco_recalc_rate() 253 if (!(cfg1 & TH1520_PLL_DSMPD)) { in th1520_pll_vco_recalc_rate() 255 frac = FIELD_GET(TH1520_PLL_FRAC, cfg1); in th1520_pll_vco_recalc_rate() 269 unsigned int cfg0, cfg1; in th1520_pll_postdiv_recalc_rate() local 272 regmap_read(pll->common.map, pll->common.cfg1, &cfg1); in th1520_pll_postdiv_recalc_rate() 274 if (cfg1 & TH1520_PLL_BYPASS) in th1520_pll_postdiv_recalc_rate() 308 .cfg1 = 0x004, 320 .cfg1 = 0x014, [all …]
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/linux/drivers/comedi/drivers/ |
H A D | ni_at_ao.c | 106 unsigned short cfg1; member 118 devpriv->cfg1 |= ATAO_CFG1_GRP2WR; in atao_select_reg_group() 120 devpriv->cfg1 &= ~ATAO_CFG1_GRP2WR; in atao_select_reg_group() 121 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_select_reg_group() 269 devpriv->cfg1 = 0; in atao_reset() 270 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_reset()
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/linux/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_fimc.c | 419 u32 cfg1, cfg2; in fimc_src_set_transf() local 423 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_src_set_transf() 424 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf() 433 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf() 435 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf() 440 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf() 442 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf() 445 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf() 448 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf() 450 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf() [all …]
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/linux/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | arb.c | 202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb() local 225 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb() 226 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); in nv04_update_arb()
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/linux/drivers/media/platform/atmel/ |
H A D | atmel-isi.c | 360 u32 ctrl, cfg1; in start_dma() local 362 cfg1 = isi_readl(isi, ISI_CFG1); in start_dma() 387 cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; in start_dma() 389 cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR; in start_dma() 398 isi_writel(isi, ISI_CFG1, cfg1); in start_dma() 793 u32 cfg1 = 0; in isi_camera_set_bus_param() local 798 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param() 800 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param() 802 cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING; in isi_camera_set_bus_param() 804 cfg1 |= ISI_CFG1_EMB_SYNC; in isi_camera_set_bus_param() [all …]
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/linux/drivers/iio/adc/ |
H A D | imx7d_adc.c | 236 u32 cfg1 = 0; in imx7d_adc_channel_set() local 243 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | in imx7d_adc_channel_set() 253 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); in imx7d_adc_channel_set() 270 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); in imx7d_adc_channel_set()
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/linux/drivers/video/fbdev/nvidia/ |
H A D | nv_hw.c | 387 unsigned int MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local 391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings() 397 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings() 400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings() 626 unsigned int MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local 630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings() 637 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings() 640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
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/linux/drivers/net/ethernet/agere/ |
H A D | et131x.c | 819 ¯egs->cfg1); in et1310_config_mac_regs1() 861 writel(0, ¯egs->cfg1); in et1310_config_mac_regs1() 869 u32 cfg1; in et1310_config_mac_regs2() local 875 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2() 889 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | in et1310_config_mac_regs2() 892 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); in et1310_config_mac_regs2() 894 cfg1 |= ET_MAC_CFG1_RX_FLOW; in et1310_config_mac_regs2() 895 writel(cfg1, &mac->cfg1); in et1310_config_mac_regs2() 921 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2() 922 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); in et1310_config_mac_regs2() [all …]
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H A D | et131x.h | 1047 u32 cfg1; /* 0x5000 */ member
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/linux/arch/sparc/include/asm/ |
H A D | sbi.h | 21 /* 0x0014 */ u32 cfg1; /* Slot1 config reg */ member
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/linux/drivers/mtd/nand/raw/ |
H A D | qcom_nandc.c | 110 u32 cfg0, cfg1; member 261 __le32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local 277 cfg1 = cpu_to_le32(host->cfg1); in update_rw_regs() 283 cfg1 = cpu_to_le32(host->cfg1_raw); in update_rw_regs() 289 nandc->regs->cfg1 = cfg1; in update_rw_regs() 1506 host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_nand_attach_chip() 1545 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip() 1821 nandc->regs->cfg1 = cpu_to_le32(host->cfg1_raw); in qcom_misc_cmd_type_exec() 1889 nandc->regs->cfg1 = cpu_to_le32(FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_param_page_type_exec()
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/linux/sound/pci/ |
H A D | als4000.c | 691 u32 cfg1 = 0; in snd_als4000_set_addr() local 699 cfg1 |= (game_io | 1) << 16; in snd_als4000_set_addr() 701 cfg1 |= (opl_io | 1); in snd_als4000_set_addr() 702 snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1); in snd_als4000_set_addr()
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/linux/drivers/video/fbdev/riva/ |
H A D | riva_hw.c | 802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local 810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings() 816 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings() 818 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings() 1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local 1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings() 1067 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings() 1069 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
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/linux/include/linux/ |
H A D | switchtec.h | 232 struct partition_info cfg1; member 259 struct partition_info cfg1; member
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/linux/sound/pci/au88x0/ |
H A D | au88x0_core.c | 1097 dma->cfg1 = 0; in vortex_adbdma_setbuffers() 1102 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1); in vortex_adbdma_setbuffers() 1110 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); in vortex_adbdma_setbuffers() 1135 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1); in vortex_adbdma_setbuffers() 1376 dma->cfg1 = 0; in vortex_wtdma_setbuffers() 1381 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1); in vortex_wtdma_setbuffers() 1388 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); in vortex_wtdma_setbuffers() 1406 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); in vortex_wtdma_setbuffers()
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H A D | au88x0.h | 112 int cfg1; member
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/linux/drivers/scsi/ |
H A D | qla1280.c | 2179 uint16_t hwrev, cfg1, cdma_conf; in qla1280_nvram_config() local 2183 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config() 2188 cfg1 |= nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config() 2190 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config() 2191 WRT_REG_WORD(®->cfg_1, cfg1); in qla1280_nvram_config() 2196 uint16_t cfg1, term; in qla1280_nvram_config() local 2199 cfg1 = nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config() 2200 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config() 2203 cfg1 |= BIT_13; in qla1280_nvram_config() 2204 WRT_REG_WORD(®->cfg_1, cfg1); in qla1280_nvram_config()
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/linux/drivers/net/ethernet/atheros/ |
H A D | ag71xx.c | 1022 u32 cfg1, cfg2; in ag71xx_mac_link_up() local 1056 cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1); in ag71xx_mac_link_up() 1057 cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC); in ag71xx_mac_link_up() 1059 cfg1 |= MAC_CFG1_TFC; in ag71xx_mac_link_up() 1062 cfg1 |= MAC_CFG1_RFC; in ag71xx_mac_link_up() 1063 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1); in ag71xx_mac_link_up()
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/linux/sound/soc/stm/ |
H A D | stm32_i2s.c | 860 u32 cfgr, cfgr_mask, cfg1; in stm32_i2s_configure() local 896 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1); in stm32_i2s_configure() 899 I2S_CFG1_FTHVL_MASK, cfg1); in stm32_i2s_configure()
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/linux/drivers/net/ethernet/smsc/ |
H A D | smc91x.c | 907 int bmcr, cfg1; in smc_phy_fixed() local 912 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); in smc_phy_fixed() 913 cfg1 |= PHY_CFG1_LNKDIS; in smc_phy_fixed() 914 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); in smc_phy_fixed()
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/linux/drivers/pinctrl/intel/ |
H A D | pinctrl-intel.c | 344 u32 cfg0, cfg1, mode; in intel_pin_dbg_show() local 354 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); in intel_pin_dbg_show() 362 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); in intel_pin_dbg_show()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | ramgk104.c | 1553 u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); in gk104_ram_new_() local 1554 if (tmp && tmp != cfg1) { in gk104_ram_new_() 1558 tmp = cfg1; in gk104_ram_new_()
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/linux/arch/mips/kernel/ |
H A D | cpu-probe.c | 1655 u32 cfg1 = read_cpucfg(LOONGSON_CFG1); in decode_cpucfg() local 1659 if (cfg1 & LOONGSON_CFG1_MMI) in decode_cpucfg()
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/linux/drivers/net/ethernet/realtek/ |
H A D | r8169_main.c | 3574 u8 cfg1; in rtl_hw_start_8102e_1() local 3584 cfg1 = RTL_R8(tp, Config1); in rtl_hw_start_8102e_1() 3585 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) in rtl_hw_start_8102e_1() 3586 RTL_W8(tp, Config1, cfg1 & ~LEDS0); in rtl_hw_start_8102e_1()
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