1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 131 #define E1000_DEV_ID_PCH2_LV_V 0x1503 132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 150 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 151 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 152 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 153 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 154 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 155 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 156 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 157 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 158 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 159 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 160 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 161 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 162 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 163 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 164 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 165 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 166 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 167 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 168 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 169 #define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 170 #define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 171 #define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 172 #define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 173 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 174 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 175 #define E1000_DEV_ID_PCH_ADL_I219_LM19 0x550C 176 #define E1000_DEV_ID_PCH_ADL_I219_V19 0x550D 177 #define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E 178 #define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F 179 #define E1000_DEV_ID_PCH_LNL_I219_LM21 0x5510 180 #define E1000_DEV_ID_PCH_LNL_I219_V21 0x5511 181 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 182 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 183 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 184 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 185 #define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0 186 #define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1 187 #define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3 188 #define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4 189 #define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5 190 #define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6 191 #define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7 192 #define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8 193 #define E1000_DEV_ID_PCH_NVL_I219_LM29 0x57B9 194 #define E1000_DEV_ID_PCH_NVL_I219_V29 0x57BA 195 #define E1000_DEV_ID_82576 0x10C9 196 #define E1000_DEV_ID_82576_FIBER 0x10E6 197 #define E1000_DEV_ID_82576_SERDES 0x10E7 198 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 199 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 200 #define E1000_DEV_ID_82576_NS 0x150A 201 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 202 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 203 #define E1000_DEV_ID_82576_VF 0x10CA 204 #define E1000_DEV_ID_82576_VF_HV 0x152D 205 #define E1000_DEV_ID_I350_VF 0x1520 206 #define E1000_DEV_ID_I350_VF_HV 0x152F 207 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 208 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 209 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 210 #define E1000_DEV_ID_82580_COPPER 0x150E 211 #define E1000_DEV_ID_82580_FIBER 0x150F 212 #define E1000_DEV_ID_82580_SERDES 0x1510 213 #define E1000_DEV_ID_82580_SGMII 0x1511 214 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 215 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 216 #define E1000_DEV_ID_I350_COPPER 0x1521 217 #define E1000_DEV_ID_I350_FIBER 0x1522 218 #define E1000_DEV_ID_I350_SERDES 0x1523 219 #define E1000_DEV_ID_I350_SGMII 0x1524 220 #define E1000_DEV_ID_I350_DA4 0x1546 221 #define E1000_DEV_ID_I210_COPPER 0x1533 222 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 223 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 224 #define E1000_DEV_ID_I210_FIBER 0x1536 225 #define E1000_DEV_ID_I210_SERDES 0x1537 226 #define E1000_DEV_ID_I210_SGMII 0x1538 227 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 228 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 229 #define E1000_DEV_ID_I210_SGMII_FLASHLESS 0x15F6 230 #define E1000_DEV_ID_I211_COPPER 0x1539 231 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 232 #define E1000_DEV_ID_I354_SGMII 0x1F41 233 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 234 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 235 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 236 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 237 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 238 239 #define E1000_REVISION_0 0 240 #define E1000_REVISION_1 1 241 #define E1000_REVISION_2 2 242 #define E1000_REVISION_3 3 243 #define E1000_REVISION_4 4 244 245 #define E1000_FUNC_0 0 246 #define E1000_FUNC_1 1 247 #define E1000_FUNC_2 2 248 #define E1000_FUNC_3 3 249 250 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 251 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 252 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 253 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 254 255 enum e1000_mac_type { 256 e1000_undefined = 0, 257 e1000_82542, 258 e1000_82543, 259 e1000_82544, 260 e1000_82540, 261 e1000_82545, 262 e1000_82545_rev_3, 263 e1000_82546, 264 e1000_82546_rev_3, 265 e1000_82541, 266 e1000_82541_rev_2, 267 e1000_82547, 268 e1000_82547_rev_2, 269 e1000_82571, 270 e1000_82572, 271 e1000_82573, 272 e1000_82574, 273 e1000_82583, 274 e1000_80003es2lan, 275 e1000_ich8lan, 276 e1000_ich9lan, 277 e1000_ich10lan, 278 e1000_pchlan, 279 e1000_pch2lan, 280 e1000_pch_lpt, 281 e1000_pch_spt, 282 e1000_pch_cnp, 283 e1000_pch_tgp, 284 e1000_pch_adp, 285 e1000_pch_mtp, 286 e1000_pch_ptp, 287 e1000_pch_nvp, 288 e1000_82575, 289 e1000_82576, 290 e1000_82580, 291 e1000_i350, 292 e1000_i354, 293 e1000_i210, 294 e1000_i211, 295 e1000_vfadapt, 296 e1000_vfadapt_i350, 297 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 298 }; 299 300 enum e1000_media_type { 301 e1000_media_type_unknown = 0, 302 e1000_media_type_copper = 1, 303 e1000_media_type_fiber = 2, 304 e1000_media_type_internal_serdes = 3, 305 e1000_num_media_types 306 }; 307 308 enum e1000_nvm_type { 309 e1000_nvm_unknown = 0, 310 e1000_nvm_none, 311 e1000_nvm_eeprom_spi, 312 e1000_nvm_eeprom_microwire, 313 e1000_nvm_flash_hw, 314 e1000_nvm_invm, 315 e1000_nvm_flash_sw 316 }; 317 318 enum e1000_nvm_override { 319 e1000_nvm_override_none = 0, 320 e1000_nvm_override_spi_small, 321 e1000_nvm_override_spi_large, 322 e1000_nvm_override_microwire_small, 323 e1000_nvm_override_microwire_large 324 }; 325 326 enum e1000_phy_type { 327 e1000_phy_unknown = 0, 328 e1000_phy_none, 329 e1000_phy_m88, 330 e1000_phy_igp, 331 e1000_phy_igp_2, 332 e1000_phy_gg82563, 333 e1000_phy_igp_3, 334 e1000_phy_ife, 335 e1000_phy_bm, 336 e1000_phy_82578, 337 e1000_phy_82577, 338 e1000_phy_82579, 339 e1000_phy_i217, 340 e1000_phy_82580, 341 e1000_phy_vf, 342 e1000_phy_i210, 343 }; 344 345 enum e1000_bus_type { 346 e1000_bus_type_unknown = 0, 347 e1000_bus_type_pci, 348 e1000_bus_type_pcix, 349 e1000_bus_type_pci_express, 350 e1000_bus_type_reserved 351 }; 352 353 enum e1000_bus_speed { 354 e1000_bus_speed_unknown = 0, 355 e1000_bus_speed_33, 356 e1000_bus_speed_66, 357 e1000_bus_speed_100, 358 e1000_bus_speed_120, 359 e1000_bus_speed_133, 360 e1000_bus_speed_2500, 361 e1000_bus_speed_5000, 362 e1000_bus_speed_reserved 363 }; 364 365 enum e1000_bus_width { 366 e1000_bus_width_unknown = 0, 367 e1000_bus_width_pcie_x1, 368 e1000_bus_width_pcie_x2, 369 e1000_bus_width_pcie_x4 = 4, 370 e1000_bus_width_pcie_x8 = 8, 371 e1000_bus_width_32, 372 e1000_bus_width_64, 373 e1000_bus_width_reserved 374 }; 375 376 enum e1000_1000t_rx_status { 377 e1000_1000t_rx_status_not_ok = 0, 378 e1000_1000t_rx_status_ok, 379 e1000_1000t_rx_status_undefined = 0xFF 380 }; 381 382 enum e1000_rev_polarity { 383 e1000_rev_polarity_normal = 0, 384 e1000_rev_polarity_reversed, 385 e1000_rev_polarity_undefined = 0xFF 386 }; 387 388 enum e1000_fc_mode { 389 e1000_fc_none = 0, 390 e1000_fc_rx_pause, 391 e1000_fc_tx_pause, 392 e1000_fc_full, 393 e1000_fc_default = 0xFF 394 }; 395 396 enum e1000_ffe_config { 397 e1000_ffe_config_enabled = 0, 398 e1000_ffe_config_active, 399 e1000_ffe_config_blocked 400 }; 401 402 enum e1000_dsp_config { 403 e1000_dsp_config_disabled = 0, 404 e1000_dsp_config_enabled, 405 e1000_dsp_config_activated, 406 e1000_dsp_config_undefined = 0xFF 407 }; 408 409 enum e1000_ms_type { 410 e1000_ms_hw_default = 0, 411 e1000_ms_force_master, 412 e1000_ms_force_slave, 413 e1000_ms_auto 414 }; 415 416 enum e1000_smart_speed { 417 e1000_smart_speed_default = 0, 418 e1000_smart_speed_on, 419 e1000_smart_speed_off 420 }; 421 422 enum e1000_serdes_link_state { 423 e1000_serdes_link_down = 0, 424 e1000_serdes_link_autoneg_progress, 425 e1000_serdes_link_autoneg_complete, 426 e1000_serdes_link_forced_up 427 }; 428 429 #define __le16 u16 430 #define __le32 u32 431 #define __le64 u64 432 /* Receive Descriptor */ 433 struct e1000_rx_desc { 434 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 435 __le16 length; /* Length of data DMAed into data buffer */ 436 __le16 csum; /* Packet checksum */ 437 u8 status; /* Descriptor status */ 438 u8 errors; /* Descriptor Errors */ 439 __le16 special; 440 }; 441 442 /* Receive Descriptor - Extended */ 443 union e1000_rx_desc_extended { 444 struct { 445 __le64 buffer_addr; 446 __le64 reserved; 447 } read; 448 struct { 449 struct { 450 __le32 mrq; /* Multiple Rx Queues */ 451 union { 452 __le32 rss; /* RSS Hash */ 453 struct { 454 __le16 ip_id; /* IP id */ 455 __le16 csum; /* Packet Checksum */ 456 } csum_ip; 457 } hi_dword; 458 } lower; 459 struct { 460 __le32 status_error; /* ext status/error */ 461 __le16 length; 462 __le16 vlan; /* VLAN tag */ 463 } upper; 464 } wb; /* writeback */ 465 }; 466 467 #define MAX_PS_BUFFERS 4 468 469 /* Number of packet split data buffers (not including the header buffer) */ 470 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 471 472 /* Receive Descriptor - Packet Split */ 473 union e1000_rx_desc_packet_split { 474 struct { 475 /* one buffer for protocol header(s), three data buffers */ 476 __le64 buffer_addr[MAX_PS_BUFFERS]; 477 } read; 478 struct { 479 struct { 480 __le32 mrq; /* Multiple Rx Queues */ 481 union { 482 __le32 rss; /* RSS Hash */ 483 struct { 484 __le16 ip_id; /* IP id */ 485 __le16 csum; /* Packet Checksum */ 486 } csum_ip; 487 } hi_dword; 488 } lower; 489 struct { 490 __le32 status_error; /* ext status/error */ 491 __le16 length0; /* length of buffer 0 */ 492 __le16 vlan; /* VLAN tag */ 493 } middle; 494 struct { 495 __le16 header_status; 496 /* length of buffers 1-3 */ 497 __le16 length[PS_PAGE_BUFFERS]; 498 } upper; 499 __le64 reserved; 500 } wb; /* writeback */ 501 }; 502 503 /* Transmit Descriptor */ 504 struct e1000_tx_desc { 505 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 506 union { 507 __le32 data; 508 struct { 509 __le16 length; /* Data buffer length */ 510 u8 cso; /* Checksum offset */ 511 u8 cmd; /* Descriptor control */ 512 } flags; 513 } lower; 514 union { 515 __le32 data; 516 struct { 517 u8 status; /* Descriptor status */ 518 u8 css; /* Checksum start */ 519 __le16 special; 520 } fields; 521 } upper; 522 }; 523 524 /* Offload Context Descriptor */ 525 struct e1000_context_desc { 526 union { 527 __le32 ip_config; 528 struct { 529 u8 ipcss; /* IP checksum start */ 530 u8 ipcso; /* IP checksum offset */ 531 __le16 ipcse; /* IP checksum end */ 532 } ip_fields; 533 } lower_setup; 534 union { 535 __le32 tcp_config; 536 struct { 537 u8 tucss; /* TCP checksum start */ 538 u8 tucso; /* TCP checksum offset */ 539 __le16 tucse; /* TCP checksum end */ 540 } tcp_fields; 541 } upper_setup; 542 __le32 cmd_and_length; 543 union { 544 __le32 data; 545 struct { 546 u8 status; /* Descriptor status */ 547 u8 hdr_len; /* Header length */ 548 __le16 mss; /* Maximum segment size */ 549 } fields; 550 } tcp_seg_setup; 551 }; 552 553 /* Offload data descriptor */ 554 struct e1000_data_desc { 555 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 556 union { 557 __le32 data; 558 struct { 559 __le16 length; /* Data buffer length */ 560 u8 typ_len_ext; 561 u8 cmd; 562 } flags; 563 } lower; 564 union { 565 __le32 data; 566 struct { 567 u8 status; /* Descriptor status */ 568 u8 popts; /* Packet Options */ 569 __le16 special; 570 } fields; 571 } upper; 572 }; 573 574 /* Statistics counters collected by the MAC */ 575 struct e1000_hw_stats { 576 u64 crcerrs; 577 u64 algnerrc; 578 u64 symerrs; 579 u64 rxerrc; 580 u64 mpc; 581 u64 scc; 582 u64 ecol; 583 u64 mcc; 584 u64 latecol; 585 u64 colc; 586 u64 dc; 587 u64 tncrs; 588 u64 sec; 589 u64 cexterr; 590 u64 rlec; 591 u64 xonrxc; 592 u64 xontxc; 593 u64 xoffrxc; 594 u64 xofftxc; 595 u64 fcruc; 596 u64 prc64; 597 u64 prc127; 598 u64 prc255; 599 u64 prc511; 600 u64 prc1023; 601 u64 prc1522; 602 u64 gprc; 603 u64 bprc; 604 u64 mprc; 605 u64 gptc; 606 u64 gorc; 607 u64 gotc; 608 u64 rnbc; 609 u64 ruc; 610 u64 rfc; 611 u64 roc; 612 u64 rjc; 613 u64 mgprc; 614 u64 mgpdc; 615 u64 mgptc; 616 u64 tor; 617 u64 tot; 618 u64 tpr; 619 u64 tpt; 620 u64 ptc64; 621 u64 ptc127; 622 u64 ptc255; 623 u64 ptc511; 624 u64 ptc1023; 625 u64 ptc1522; 626 u64 mptc; 627 u64 bptc; 628 u64 tsctc; 629 u64 tsctfc; 630 u64 iac; 631 u64 icrxptc; 632 u64 icrxatc; 633 u64 ictxptc; 634 u64 ictxatc; 635 u64 ictxqec; 636 u64 ictxqmtc; 637 u64 icrxdmtc; 638 u64 icrxoc; 639 u64 cbtmpc; 640 u64 htdpmc; 641 u64 cbrdpc; 642 u64 cbrmpc; 643 u64 rpthc; 644 u64 hgptc; 645 u64 htcbdpc; 646 u64 hgorc; 647 u64 hgotc; 648 u64 lenerrs; 649 u64 scvpc; 650 u64 hrmpc; 651 u64 doosync; 652 u64 o2bgptc; 653 u64 o2bspc; 654 u64 b2ospc; 655 u64 b2ogprc; 656 u64 tlpic; 657 u64 rlpic; 658 }; 659 660 struct e1000_vf_stats { 661 u64 base_gprc; 662 u64 base_gptc; 663 u64 base_gorc; 664 u64 base_gotc; 665 u64 base_mprc; 666 u64 base_gotlbc; 667 u64 base_gptlbc; 668 u64 base_gorlbc; 669 u64 base_gprlbc; 670 671 u32 last_gprc; 672 u32 last_gptc; 673 u32 last_gorc; 674 u32 last_gotc; 675 u32 last_mprc; 676 u32 last_gotlbc; 677 u32 last_gptlbc; 678 u32 last_gorlbc; 679 u32 last_gprlbc; 680 681 u64 gprc; 682 u64 gptc; 683 u64 gorc; 684 u64 gotc; 685 u64 mprc; 686 u64 gotlbc; 687 u64 gptlbc; 688 u64 gorlbc; 689 u64 gprlbc; 690 }; 691 692 struct e1000_phy_stats { 693 u32 idle_errors; 694 u32 receive_errors; 695 }; 696 697 struct e1000_host_mng_dhcp_cookie { 698 u32 signature; 699 u8 status; 700 u8 reserved0; 701 u16 vlan_id; 702 u32 reserved1; 703 u16 reserved2; 704 u8 reserved3; 705 u8 checksum; 706 }; 707 708 /* Host Interface "Rev 1" */ 709 struct e1000_host_command_header { 710 u8 command_id; 711 u8 command_length; 712 u8 command_options; 713 u8 checksum; 714 }; 715 716 #define E1000_HI_MAX_DATA_LENGTH 252 717 struct e1000_host_command_info { 718 struct e1000_host_command_header command_header; 719 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 720 }; 721 722 /* Host Interface "Rev 2" */ 723 struct e1000_host_mng_command_header { 724 u8 command_id; 725 u8 checksum; 726 u16 reserved1; 727 u16 reserved2; 728 u16 command_length; 729 }; 730 731 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 732 struct e1000_host_mng_command_info { 733 struct e1000_host_mng_command_header command_header; 734 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 735 }; 736 737 #include "e1000_mac.h" 738 #include "e1000_phy.h" 739 #include "e1000_nvm.h" 740 #include "e1000_manage.h" 741 #include "e1000_mbx.h" 742 743 /* Function pointers for the MAC. */ 744 struct e1000_mac_operations { 745 s32 (*init_params)(struct e1000_hw *); 746 s32 (*id_led_init)(struct e1000_hw *); 747 s32 (*blink_led)(struct e1000_hw *); 748 bool (*check_mng_mode)(struct e1000_hw *); 749 s32 (*check_for_link)(struct e1000_hw *); 750 s32 (*cleanup_led)(struct e1000_hw *); 751 void (*clear_hw_cntrs)(struct e1000_hw *); 752 void (*clear_vfta)(struct e1000_hw *); 753 s32 (*get_bus_info)(struct e1000_hw *); 754 void (*set_lan_id)(struct e1000_hw *); 755 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 756 s32 (*led_on)(struct e1000_hw *); 757 s32 (*led_off)(struct e1000_hw *); 758 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 759 s32 (*reset_hw)(struct e1000_hw *); 760 s32 (*init_hw)(struct e1000_hw *); 761 void (*shutdown_serdes)(struct e1000_hw *); 762 void (*power_up_serdes)(struct e1000_hw *); 763 s32 (*setup_link)(struct e1000_hw *); 764 s32 (*setup_physical_interface)(struct e1000_hw *); 765 s32 (*setup_led)(struct e1000_hw *); 766 void (*write_vfta)(struct e1000_hw *, u32, u32); 767 void (*config_collision_dist)(struct e1000_hw *); 768 int (*rar_set)(struct e1000_hw *, u8*, u32); 769 s32 (*read_mac_addr)(struct e1000_hw *); 770 s32 (*validate_mdi_setting)(struct e1000_hw *); 771 s32 (*set_obff_timer)(struct e1000_hw *, u32); 772 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 773 void (*release_swfw_sync)(struct e1000_hw *, u16); 774 }; 775 776 /* When to use various PHY register access functions: 777 * 778 * Func Caller 779 * Function Does Does When to use 780 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 781 * X_reg L,P,A n/a for simple PHY reg accesses 782 * X_reg_locked P,A L for multiple accesses of different regs 783 * on different pages 784 * X_reg_page A L,P for multiple accesses of different regs 785 * on the same page 786 * 787 * Where X=[read|write], L=locking, P=sets page, A=register access 788 * 789 */ 790 struct e1000_phy_operations { 791 s32 (*init_params)(struct e1000_hw *); 792 s32 (*acquire)(struct e1000_hw *); 793 s32 (*cfg_on_link_up)(struct e1000_hw *); 794 s32 (*check_polarity)(struct e1000_hw *); 795 s32 (*check_reset_block)(struct e1000_hw *); 796 s32 (*commit)(struct e1000_hw *); 797 s32 (*force_speed_duplex)(struct e1000_hw *); 798 s32 (*get_cfg_done)(struct e1000_hw *hw); 799 s32 (*get_cable_length)(struct e1000_hw *); 800 s32 (*get_info)(struct e1000_hw *); 801 s32 (*set_page)(struct e1000_hw *, u16); 802 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 803 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 804 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 805 void (*release)(struct e1000_hw *); 806 s32 (*reset)(struct e1000_hw *); 807 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 808 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 809 s32 (*write_reg)(struct e1000_hw *, u32, u16); 810 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 811 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 812 void (*power_up)(struct e1000_hw *); 813 void (*power_down)(struct e1000_hw *); 814 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 815 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 816 }; 817 818 /* Function pointers for the NVM. */ 819 struct e1000_nvm_operations { 820 s32 (*init_params)(struct e1000_hw *); 821 s32 (*acquire)(struct e1000_hw *); 822 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 823 void (*release)(struct e1000_hw *); 824 void (*reload)(struct e1000_hw *); 825 s32 (*update)(struct e1000_hw *); 826 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 827 s32 (*validate)(struct e1000_hw *); 828 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 829 }; 830 831 struct e1000_mac_info { 832 struct e1000_mac_operations ops; 833 u8 addr[ETHER_ADDR_LEN]; 834 u8 perm_addr[ETHER_ADDR_LEN]; 835 836 enum e1000_mac_type type; 837 838 u32 collision_delta; 839 u32 ledctl_default; 840 u32 ledctl_mode1; 841 u32 ledctl_mode2; 842 u32 mc_filter_type; 843 u32 tx_packet_delta; 844 u32 txcw; 845 846 u16 current_ifs_val; 847 u16 ifs_max_val; 848 u16 ifs_min_val; 849 u16 ifs_ratio; 850 u16 ifs_step_size; 851 u16 mta_reg_count; 852 u16 uta_reg_count; 853 854 /* Maximum size of the MTA register table in all supported adapters */ 855 #define MAX_MTA_REG 128 856 u32 mta_shadow[MAX_MTA_REG]; 857 u16 rar_entry_count; 858 859 u8 forced_speed_duplex; 860 861 bool adaptive_ifs; 862 bool has_fwsm; 863 bool arc_subsystem_valid; 864 bool asf_firmware_present; 865 bool autoneg; 866 bool autoneg_failed; 867 bool get_link_status; 868 bool in_ifs_mode; 869 bool report_tx_early; 870 enum e1000_serdes_link_state serdes_link_state; 871 bool serdes_has_link; 872 bool tx_pkt_filtering; 873 u32 max_frame_size; 874 }; 875 876 struct e1000_phy_info { 877 struct e1000_phy_operations ops; 878 enum e1000_phy_type type; 879 880 enum e1000_1000t_rx_status local_rx; 881 enum e1000_1000t_rx_status remote_rx; 882 enum e1000_ms_type ms_type; 883 enum e1000_ms_type original_ms_type; 884 enum e1000_rev_polarity cable_polarity; 885 enum e1000_smart_speed smart_speed; 886 887 u32 addr; 888 u32 id; 889 u32 reset_delay_us; /* in usec */ 890 u32 revision; 891 u32 current_retry_counter; 892 893 enum e1000_media_type media_type; 894 895 u16 autoneg_advertised; 896 u16 autoneg_mask; 897 u16 cable_length; 898 u16 max_cable_length; 899 u16 min_cable_length; 900 901 u8 mdix; 902 903 bool disable_polarity_correction; 904 bool is_mdix; 905 bool polarity_correction; 906 bool speed_downgraded; 907 bool autoneg_wait_to_complete; 908 }; 909 910 struct e1000_nvm_info { 911 struct e1000_nvm_operations ops; 912 enum e1000_nvm_type type; 913 enum e1000_nvm_override override; 914 915 u32 flash_bank_size; 916 u32 flash_base_addr; 917 918 u16 word_size; 919 u16 delay_usec; 920 u16 address_bits; 921 u16 opcode_bits; 922 u16 page_size; 923 }; 924 925 struct e1000_bus_info { 926 enum e1000_bus_type type; 927 enum e1000_bus_speed speed; 928 enum e1000_bus_width width; 929 930 u16 func; 931 u16 pci_cmd_word; 932 }; 933 934 struct e1000_fc_info { 935 u32 high_water; /* Flow control high-water mark */ 936 u32 low_water; /* Flow control low-water mark */ 937 u16 pause_time; /* Flow control pause timer */ 938 u16 refresh_time; /* Flow control refresh timer */ 939 bool send_xon; /* Flow control send XON */ 940 bool strict_ieee; /* Strict IEEE mode */ 941 enum e1000_fc_mode current_mode; /* FC mode in effect */ 942 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 943 }; 944 945 struct e1000_mbx_operations { 946 s32 (*init_params)(struct e1000_hw *hw); 947 s32 (*read)(struct e1000_hw *, u32 *, u16, u16, bool); 948 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 949 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 950 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 951 s32 (*check_for_msg)(struct e1000_hw *, u16); 952 s32 (*check_for_ack)(struct e1000_hw *, u16); 953 s32 (*check_for_rst)(struct e1000_hw *, u16); 954 s32 (*unlock)(struct e1000_hw *, u16); 955 }; 956 957 struct e1000_mbx_stats { 958 u32 msgs_tx; 959 u32 msgs_rx; 960 961 u32 acks; 962 u32 reqs; 963 u32 rsts; 964 }; 965 966 struct e1000_mbx_info { 967 struct e1000_mbx_operations ops; 968 struct e1000_mbx_stats stats; 969 u32 timeout; 970 u32 usec_delay; 971 u16 size; 972 }; 973 974 struct e1000_dev_spec_82541 { 975 enum e1000_dsp_config dsp_config; 976 enum e1000_ffe_config ffe_config; 977 u16 spd_default; 978 bool phy_init_script; 979 }; 980 981 struct e1000_dev_spec_82542 { 982 bool dma_fairness; 983 }; 984 985 struct e1000_dev_spec_82543 { 986 u32 tbi_compatibility; 987 bool dma_fairness; 988 bool init_phy_disabled; 989 }; 990 991 struct e1000_dev_spec_82571 { 992 bool laa_is_present; 993 u32 smb_counter; 994 }; 995 996 struct e1000_dev_spec_80003es2lan { 997 bool mdic_wa_enable; 998 }; 999 1000 struct e1000_shadow_ram { 1001 u16 value; 1002 bool modified; 1003 }; 1004 1005 #define E1000_SHADOW_RAM_WORDS 2048 1006 1007 /* I218 PHY Ultra Low Power (ULP) states */ 1008 enum e1000_ulp_state { 1009 e1000_ulp_state_unknown, 1010 e1000_ulp_state_off, 1011 e1000_ulp_state_on, 1012 }; 1013 1014 struct e1000_dev_spec_ich8lan { 1015 bool kmrn_lock_loss_workaround_enabled; 1016 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1017 bool nvm_k1_enabled; 1018 bool disable_k1_off; 1019 bool eee_disable; 1020 u16 eee_lp_ability; 1021 enum e1000_ulp_state ulp_state; 1022 bool ulp_capability_disabled; 1023 bool during_suspend_flow; 1024 bool smbus_disable; 1025 }; 1026 1027 struct e1000_dev_spec_82575 { 1028 bool sgmii_active; 1029 bool global_device_reset; 1030 bool eee_disable; 1031 bool module_plugged; 1032 bool clear_semaphore_once; 1033 u32 mtu; 1034 struct sfp_e1000_flags eth_flags; 1035 u8 media_port; 1036 bool media_changed; 1037 }; 1038 1039 struct e1000_dev_spec_vf { 1040 u32 vf_number; 1041 u32 v2p_mailbox; 1042 }; 1043 1044 struct e1000_hw { 1045 void *back; 1046 1047 u8 *hw_addr; 1048 u8 *flash_address; 1049 unsigned long io_base; 1050 1051 struct e1000_mac_info mac; 1052 struct e1000_fc_info fc; 1053 struct e1000_phy_info phy; 1054 struct e1000_nvm_info nvm; 1055 struct e1000_bus_info bus; 1056 struct e1000_mbx_info mbx; 1057 struct e1000_host_mng_dhcp_cookie mng_cookie; 1058 1059 union { 1060 struct e1000_dev_spec_82541 _82541; 1061 struct e1000_dev_spec_82542 _82542; 1062 struct e1000_dev_spec_82543 _82543; 1063 struct e1000_dev_spec_82571 _82571; 1064 struct e1000_dev_spec_80003es2lan _80003es2lan; 1065 struct e1000_dev_spec_ich8lan ich8lan; 1066 struct e1000_dev_spec_82575 _82575; 1067 struct e1000_dev_spec_vf vf; 1068 } dev_spec; 1069 1070 u16 device_id; 1071 u16 subsystem_vendor_id; 1072 u16 subsystem_device_id; 1073 u16 vendor_id; 1074 1075 u8 revision_id; 1076 }; 1077 1078 #include "e1000_82541.h" 1079 #include "e1000_82543.h" 1080 #include "e1000_82571.h" 1081 #include "e1000_80003es2lan.h" 1082 #include "e1000_ich8lan.h" 1083 #include "e1000_82575.h" 1084 #include "e1000_i210.h" 1085 #include "e1000_base.h" 1086 1087 /* These functions must be implemented by drivers */ 1088 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1089 void e1000_pci_set_mwi(struct e1000_hw *hw); 1090 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1091 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1092 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1093 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1094 1095 #endif 1096