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Searched refs:caches (Results 1 – 25 of 104) sorted by relevance

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/linux/kernel/bpf/
H A Dmemalloc.c566 ma->caches = pcc; in bpf_mem_alloc_init()
578 ma->caches = pcc; in bpf_mem_alloc_percpu_init()
600 pcc = ma->caches; in bpf_mem_alloc_percpu_unit_init()
663 if (ma->caches) { in check_leaked_objs()
665 cc = per_cpu_ptr(ma->caches, cpu); in check_leaked_objs()
681 free_percpu(ma->caches); in free_mem_alloc_no_barrier()
683 ma->caches = NULL; in free_mem_alloc_no_barrier()
755 if (ma->caches) { in bpf_mem_alloc_destroy()
758 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy()
897 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc()
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/linux/tools/cgroup/
H A Dmemcg_slabinfo.py183 caches = {}
202 caches[addr] = cache
214 for addr in caches:
216 cache_show(caches[addr], cfg, stats[addr])
/linux/arch/arm/boot/compressed/
H A Dhead-xscale.S28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
H A Dhead-sa1100.S38 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
40 @ disabling MMU and caches
/linux/arch/arm/mm/
H A Dproc-arm720.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
145 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
H A Dproc-sa110.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
H A Dproc-fa526.S41 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm926.S55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
426 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
434 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-sa1100.S59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-mohawk.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
367 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
H A Dproc-arm920.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
410 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm925.S86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
444 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
451 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-arm740.S51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
H A Dproc-arm1022.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm922.S65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1026.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1020e.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-xsc3.S94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
439 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
459 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
H A Dproc-arm1020.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
442 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
/linux/Documentation/block/
H A Dwriteback_cache_control.rst9 write back caches. That means the devices signal I/O completion to the
52 For devices that do not support volatile write caches there is no driver
57 For devices with volatile write caches the driver needs to tell the block layer
58 that it supports flushing caches by setting the
/linux/tools/perf/
H A Dbuiltin-stat.c1322 struct cpu_cache_level caches[MAX_CACHE_LVL]; in cpu__get_cache_details()
1328 ret = build_caches_for_cpu(cpu.cpu, caches, &caches_cnt); in cpu__get_cache_details()
1352 if (caches[i].level > caches[max_level_index].level) in cpu__get_cache_details()
1356 cache->cache_lvl = caches[max_level_index].level; in cpu__get_cache_details()
1357 cache->cache = cpu__get_cache_id_from_map(cpu, caches[max_level_index].map); in cpu__get_cache_details()
1359 /* Reset i to 0 to free entire caches[] */ in cpu__get_cache_details()
1365 if (caches[i].level == cache_level) {
1367 cache->cache = cpu__get_cache_id_from_map(cpu, caches[i].map);
1370 cpu_cache_level__free(&caches[ in aggr_cpu_id__cache()
1302 struct cpu_cache_level caches[MAX_CACHE_LVL]; cpu__get_cache_details() local
1655 struct cpu_cache_level *caches = env->caches; perf_env__get_cache_id_for_cpu() local
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/linux/drivers/acpi/numa/
H A Dhmat.c73 struct list_head caches; member
131 list_for_each_entry(tcache, &target->caches, node) { in hmat_get_extended_linear_cache_size()
232 INIT_LIST_HEAD(&target->caches); in alloc_target()
545 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
849 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
1013 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
/linux/include/linux/
H A Dbpf_mem_alloc.h12 struct bpf_mem_caches __percpu *caches; member
/linux/Documentation/filesystems/nfs/
H A Drpc-cache.rst13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
/linux/tools/perf/util/
H A Dheader.c1296 * Build caches levels for a particular CPU from the data in in write_cache()
1298 * The cache level data is stored in caches[] from index at in write_cache()
1301 int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cntp) in write_cache()
1318 if (cpu_cache_level__cmp(&c, &caches[i])) in write_sample_time()
1323 caches[*cntp] = c; in write_sample_time()
1332 static int build_caches(struct cpu_cache_level caches[], u32 *cntp) in memory_node__read()
1339 int ret = build_caches_for_cpu(cpu, caches, &cnt); in memory_node__read()
1352 struct cpu_cache_level caches[max_caches]; in memory_node__read()
1356 ret = build_caches(caches, &cnt); in memory_node__read()
1360 qsort(&caches, cn in memory_node__read()
1207 build_caches_for_cpu(u32 cpu,struct cpu_cache_level caches[],u32 * cntp) build_caches_for_cpu() argument
1238 build_caches(struct cpu_cache_level caches[],u32 * cntp) build_caches() argument
1258 struct cpu_cache_level caches[max_caches]; write_cache() local
3104 struct cpu_cache_level *caches; process_cache() local
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