Searched refs:cachelines (Results 1 – 6 of 6) sorted by relevance
37 for cachelines with highest contention - highest number of HITM accesses.216 - sort all cachelines based on user settings220 1) most expensive cachelines list245 - sum of all cachelines accesses355 - overall statistics on shared cachelines358 - list of most expensive cachelines366 through cachelines list and to display offset details.371 than cachelines. Levels 1 and 2 normally show function names, while level 3385 Level 3: the specific cachelines shared by the reader/writer pair396 shown in the function view into the cachelines tha[all...]
21 multi-CPU system these may be on cachelines that keep bouncing56 multi-CPU system these may be on cachelines that keep bouncing
67 struct radix_tree_root cachelines; member83 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()111 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()161 INIT_RADIX_TREE(&state.cachelines, GFP_KERNEL); in mock_hwsp_freelist()
14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines221 invalidate the affected cachelines. The CXL Region driver attempts
40 be full sized. Variables that straddle cachelines or pages void
290 objects are aligned on cachelines.