Home
last modified time | relevance | path

Searched refs:c8 (Results 1 – 25 of 67) sorted by relevance

123

/linux/arch/arm/include/asm/hardware/
H A Dcp14.h65 #define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
81 #define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
97 #define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
113 #define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
130 #define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
145 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
170 #define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
186 #define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
202 #define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
218 #define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
[all …]
/linux/arch/arm/mm/
H A Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
H A Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
H A Dtlb-v4wb.S39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dtlb-v4wbi.S41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dproc-arm720.S75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
147 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
H A Dproc-sa1100.S79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
192 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-sa110.S71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
H A Dtlb-fa.S44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
H A Dproc-fa526.S64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-mohawk.S67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
328 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
388 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
H A Dproc-arm920.S83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
360 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
413 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm926.S75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
412 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
429 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-xscale.S151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
457 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
529 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
546 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
H A Dproc-arm1022.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm922.S85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
363 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm1026.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
382 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
410 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dtlb-v4.S39 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
H A Dproc-arm1020e.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
400 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
428 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/linux/arch/arm/include/asm/
H A Darm_pmuv3.h31 #define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0)
32 #define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
33 #define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2)
34 #define PMEVCNTR3 __ACCESS_CP15(c14, 0, c8, 3)
35 #define PMEVCNTR4 __ACCESS_CP15(c14, 0, c8, 4)
36 #define PMEVCNTR5 __ACCESS_CP15(c14, 0, c8, 5)
37 #define PMEVCNTR6 __ACCESS_CP15(c14, 0, c8, 6)
38 #define PMEVCNTR7 __ACCESS_CP15(c14, 0, c8, 7)
/linux/arch/alpha/include/asm/
H A Dstring.h39 unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; in __memset() local
40 return __constant_c_memset(s, c8, n); in __memset()
/linux/Documentation/iio/
H A Dadxl313.rst216 000000e0 c8 ff 03 fc 32 00 c5 ff ff fc 32 00 c7 ff 0a fc |....2.....2.....|
217 000000f0 30 00 c8 ff 06 fc 33 00 c7 ff 01 fc 2f 00 c8 ff |0.....3...../...|
218 00000100 02 fc 32 00 c6 ff 04 fc 33 00 c8 ff 05 fc 33 00 |..2.....3.....3.|
220 00000120 35 00 c9 ff 08 fc 35 00 c8 ff 02 fc 31 00 c5 ff |5.....5.....1...|
223 00000150 31 00 c5 ff 04 fc 31 00 c8 ff 03 fc 32 00 c8 ff |1.....1.....2...|
/linux/drivers/gpu/drm/ci/xfails/
H A Dmsm-apq8096-flakes.txt2 # Bug Report: https://lore.kernel.org/linux-arm-msm/661483c8-ad82-400d-bcd8-e94986d20d7d@collabora.…
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp453.dts15 compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
/linux/arch/arm/kernel/
H A Dhead-nommu.S350 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
364 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
365 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1

123