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/linux/arch/arm/mm/
H A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
100 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
140 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
H A Dproc-arm946.S63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
337 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
152 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
H A Dcache-v4wt.S49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
93 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
H A Dproc-xsc3.S153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
206 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
208 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
240 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
262 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
H A Dproc-arm940.S56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
126 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
179 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
284 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
290 mcr p15, 0, r0, c6, c5, 0
296 mcr p15, 0, r0, c6, c5, 1
328 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
329 mcr p15, 0, r0, c5, c0, 1
H A Dproc-fa526.S112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
115 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
154 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
156 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
H A Dproc-arm925.S147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
178 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
250 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
409 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-arm926.S113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
371 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-mohawk.S96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
324 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
369 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
H A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
H A Dproc-xscale.S151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
241 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
248 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
273 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
291 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
296 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
318 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
454 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
H A Dtlb-v6.S51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
88 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm922.S113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dproc-v6.S66 mcr p15, 0, r1, c7, c5, 4 @ ISB
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
163 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
179 mcr p15, 0, ip, c7, c5, 4 @ ISB
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
H A Dproc-arm920.S111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
357 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dtlb-v4wb.S39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
H A Dproc-feroceon.S131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
189 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
270 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
466 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
H A Dtlb-v4wbi.S41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
H A Dproc-arm1022.S122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
388 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
H A Dproc-arm1026.S122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
378 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
H A Dproc-arm1020e.S122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
226 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
396 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
/linux/arch/arm/include/asm/hardware/
H A Dcp14.h47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
/linux/arch/arm/include/asm/vdso/
H A Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
898 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c7, c5, 4 @ ISB
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1200 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
[all …]

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