| /linux/drivers/regulator/ |
| H A D | anatop-regulator.c | 30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
|
| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-ip.c | 311 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_round_rate()
338 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_recalc_rate()
349 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_set_rate()
359 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_get_parent()
370 return cv1800_clk_clearbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
372 return cv1800_clk_setbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
522 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_round_rate()
549 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_recalc_rate()
560 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_set_rate()
570 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_get_parent()
[all …]
|
| H A D | clk-cv18xx-ip.h | 32 struct cv1800_clk_regbit bypass; member
44 struct cv1800_clk_regbit bypass; member
52 struct cv1800_clk_regbit bypass; member
123 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
143 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
186 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
218 .bypass = CV1800_CLK_BIT(_bypass_reg, \
|
| /linux/include/trace/events/ |
| H A D | bcache.h | 124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
179 __entry->nr_sector, __entry->writeback, __entry->bypass)
|
| /linux/arch/arm/mach-omap2/ |
| H A D | sram.h | 12 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
25 int bypass);
38 int bypass);
|
| H A D | clkt2xxx_dpllcore.c | 114 u32 bypass = 0; in omap2_reprogram_dpllcore() local
162 bypass = 1; in omap2_reprogram_dpllcore()
169 bypass); in omap2_reprogram_dpllcore()
|
| H A D | sram.c | 242 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
244 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) in omap2_set_prcm() argument
247 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); in omap2_set_prcm()
|
| /linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
|
| /linux/drivers/md/bcache/ |
| H A D | stats.c | 184 bool hit, bool bypass) in mark_cache_stats() argument
186 if (!bypass) in mark_cache_stats()
199 bool hit, bool bypass) in bch_mark_cache_accounting() argument
203 mark_cache_stats(&dc->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
204 mark_cache_stats(&c->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
|
| H A D | request.c | 192 if (op->bypass) in CLOSURE_CALLBACK()
271 op->bypass = true; in CLOSURE_CALLBACK()
313 op->writeback, op->bypass); in CLOSURE_CALLBACK()
881 !s->cache_missed, s->iop.bypass); in CLOSURE_CALLBACK()
882 trace_bcache_read(s->orig_bio, !s->cache_missed, s->iop.bypass); in CLOSURE_CALLBACK()
902 if (s->cache_miss || s->iop.bypass) { in cached_dev_cache_miss()
996 s->iop.bypass = false; in cached_dev_write()
1008 s->iop.bypass = true; in cached_dev_write()
1012 s->iop.bypass)) { in cached_dev_write()
1013 s->iop.bypass = false; in cached_dev_write()
[all …]
|
| /linux/drivers/clk/socfpga/ |
| H A D | clk-pll.c | 44 u32 bypass; in clk_pll_recalc_rate() local
47 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); in clk_pll_recalc_rate()
48 if (bypass & MAINPLL_BYPASS) in clk_pll_recalc_rate()
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-i2c-devices-bq32k | 5 Description: Attribute for enable/disable the trickle charge bypass
7 enable/disable the Trickle charge FET bypass.
|
| H A D | sysfs-bus-iio-filter-admv8818 | 10 - bypass -> bypass low pass filter, high pass filter and disable/unregister
|
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 5 (reference clock and bypass clock), with digital phase locked
36 and second entry bypass clock
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
79 ti,low-power-bypass;
|
| H A D | fapll.txt | 5 (reference clock and bypass clock), and one or more child
13 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-asxx-defs.h | 200 uint64_t bypass:1; member
202 uint64_t bypass:1;
469 uint64_t bypass:1; member
475 uint64_t bypass:1;
493 uint64_t bypass:1; member
503 uint64_t bypass:1;
|
| /linux/drivers/power/supply/ |
| H A D | bq25980_charger.c | 31 bool bypass; member
306 if (bq->state.bypass) in bq25980_set_input_curr_lim()
328 if (bq->state.bypass) { in bq25980_get_input_volt_lim()
350 if (bq->state.bypass) { in bq25980_set_input_volt_lim()
454 bq->state.bypass = en_bypass; in bq25980_set_bypass()
456 return bq->state.bypass; in bq25980_set_bypass()
604 state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS; in bq25980_get_state()
766 else if (state.bypass) in bq25980_get_charger_property()
768 else if (!state.bypass) in bq25980_get_charger_property()
828 old_state.bypass != new_state->bypass); in bq25980_state_changed()
[all …]
|
| /linux/drivers/pwm/ |
| H A D | pwm-sun4i.c | 170 bool *bypass) in sun4i_pwm_calculate() argument
177 *bypass = sun4ichip->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
184 if (*bypass) in sun4i_pwm_calculate()
238 bool bypass; in sun4i_pwm_apply() local
251 &bypass); in sun4i_pwm_apply()
262 if (bypass) { in sun4i_pwm_apply()
|
| /linux/net/sched/ |
| H A D | sch_fifo.c | 103 bool bypass; in __fifo_init() local
123 bypass = sch->limit >= psched_mtu(qdisc_dev(sch)); in __fifo_init()
125 bypass = sch->limit >= 1; in __fifo_init()
127 if (bypass) in __fifo_init()
|
| /linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-helper-jtag.c | 66 jtgc.s.bypass = 0x3; in cvmx_helper_qlm_jtag_init()
68 jtgc.s.bypass = 0xf; in cvmx_helper_qlm_jtag_init()
|
| /linux/drivers/clk/at91/ |
| H A D | at91rm9200.c | 86 bool bypass; in at91rm9200_pmc_setup() local
109 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91rm9200_pmc_setup()
112 bypass); in at91rm9200_pmc_setup()
|
| H A D | at91sam9g45.c | 101 bool bypass; in at91sam9g45_pmc_setup() local
124 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9g45_pmc_setup()
127 bypass); in at91sam9g45_pmc_setup()
|
| H A D | at91sam9n12.c | 121 bool bypass; in at91sam9n12_pmc_setup() local
148 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9n12_pmc_setup()
151 bypass); in at91sam9n12_pmc_setup()
|
| H A D | sama5d4.c | 138 bool bypass; in sama5d4_pmc_setup() local
166 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d4_pmc_setup()
169 bypass); in sama5d4_pmc_setup()
|
| /linux/Documentation/networking/ |
| H A D | nf_flowtable.rst | 21 transmitted to the output netdevice via neigh_xmit(), hence, packets bypass the
38 forwarding path including the Netfilter hooks and the flowtable fastpath bypass.
68 |__yes_________________fastpath bypass ____________________________|
84 Enabling the flowtable bypass is relatively easy, you only need to create a
109 forwarding bypass.
137 allows the flowtable to define a fastpath bypass between the bridge ports
143 fastpath bypass
|