1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_COEX_H__
6 #define __RTW89_COEX_H__
7
8 #include "core.h"
9
10 #define BTC_H2C_MAXLEN 2020
11 #define BTC_TLV_SLOT_ID_LEN_V7 1
12 #define BTC_SLOT_REQ_TH 2
13
14 #define BTC_FREQ_W2G 2412
15 #define BTC_FREQ_W5G 5005
16 #define BTC_FREQ_W6G 5955
17
18 #define BTC_FREQ_B2G 2402
19 #define BTC_FREQ_B6G 5125
20
21 #define BTC_FREQ_W2G_CH14 2484
22
23 #define BTC_LO_2G_DNM 125 /* LO Coefficient Denominator */
24 #define BTC_LO_5G_DNM 125
25 #define BTC_LO_6G_DNM 150
26
27 #define BTC_LO_2G_NMR 400 /* LO Coefficient Numerator */
28 #define BTC_LO_5G_NMR 200
29 #define BTC_LO_6G_NMR 200
30
31 #define BTC_CH_W2G_MIN 1 /* start from 2412MHz */
32 #define BTC_CH_W2G_MAX 14
33 #define BTC_CH_W5G_MIN 1 /* start from 5005MHz */
34 #define BTC_CH_W5G_MAX 165
35 #define BTC_CH_W6G_MIN 1 /* start from 5955MHz */
36 #define BTC_CH_W6G_MAX 233
37
38 #define BTC_CH_B2G_MIN 0 /* start from 2402MHz */
39 #define BTC_CH_B2G_MAX 78
40
41 #define BTC_CH_B5G_MIN 600 /* start from 5725MHz */
42 #define BTC_CH_B5G_MAX 1300
43
44 #define BTC_VCO_GUARD_W2W 10 /* WiFi to WiFi VCO freq forbiddened range (MHZ) */
45 #define BTC_VCO_GUARD_W2B 25 /* WiFi to WiFi VCO freq forbiddened range (MHZ) */
46 #define BTC_VCO_GUARD_B2B 10 /* WiFi to WiFi VCO freq forbiddened range (MHZ) */
47
48 enum btc_mode {
49 BTC_MODE_NORMAL,
50 BTC_MODE_WL,
51 BTC_MODE_BT,
52 BTC_MODE_WLOFF,
53 BTC_MODE_COTX,
54 BTC_MODE_MECHANISM_INIT,
55 BTC_MODE_MAX
56 };
57
58 enum btc_wl_rfk_type {
59 BTC_WRFKT_IQK = 0,
60 BTC_WRFKT_LCK = 1,
61 BTC_WRFKT_DPK = 2,
62 BTC_WRFKT_TXGAPK = 3,
63 BTC_WRFKT_DACK = 4,
64 BTC_WRFKT_RXDCK = 5,
65 BTC_WRFKT_TSSI = 6,
66 BTC_WRFKT_CHLK = 7,
67 };
68
69 #define NM_EXEC false
70 #define FC_EXEC true
71
72 #define RTW89_COEX_ACT1_WORK_PERIOD round_jiffies_relative(HZ)
73 #define RTW89_COEX_BT_DEVINFO_WORK_PERIOD round_jiffies_relative(HZ * 16)
74 #define RTW89_COEX_RFK_CHK_WORK_PERIOD msecs_to_jiffies(300)
75 #define BTC_RFK_PATH_MAP GENMASK(3, 0)
76 #define BTC_RFK_PHY_MAP GENMASK(5, 4)
77 #define BTC_RFK_BAND_MAP GENMASK(7, 6)
78
79 enum btc_wl_rfk_state {
80 BTC_WRFK_STOP = 0,
81 BTC_WRFK_START = 1,
82 BTC_WRFK_ONESHOT_START = 2,
83 BTC_WRFK_ONESHOT_STOP = 3,
84 };
85
86 enum btc_pri {
87 BTC_PRI_MASK_RX_RESP = 0,
88 BTC_PRI_MASK_TX_RESP,
89 BTC_PRI_MASK_BEACON,
90 BTC_PRI_MASK_RX_CCK,
91 BTC_PRI_MASK_TX_MNGQ,
92 BTC_PRI_MASK_MAX,
93 };
94
95 enum btc_bt_trs {
96 BTC_BT_SS_GROUP = 0x0,
97 BTC_BT_TX_GROUP = 0x2,
98 BTC_BT_RX_GROUP = 0x3,
99 BTC_BT_MAX_GROUP,
100 };
101
102 enum btc_rssi_st {
103 BTC_RSSI_ST_LOW = 0x0,
104 BTC_RSSI_ST_HIGH,
105 BTC_RSSI_ST_STAY_LOW,
106 BTC_RSSI_ST_STAY_HIGH,
107 BTC_RSSI_ST_MAX
108 };
109
110 enum btc_fddt_en {
111 BTC_FDDT_DISABLE,
112 BTC_FDDT_ENABLE,
113 };
114
115 #define BTC_RSSI_HIGH(_rssi_) \
116 ({typeof(_rssi_) __rssi = (_rssi_); \
117 ((__rssi == BTC_RSSI_ST_HIGH || \
118 __rssi == BTC_RSSI_ST_STAY_HIGH) ? 1 : 0); })
119
120 #define BTC_RSSI_LOW(_rssi_) \
121 ({typeof(_rssi_) __rssi = (_rssi_); \
122 ((__rssi == BTC_RSSI_ST_LOW || \
123 __rssi == BTC_RSSI_ST_STAY_LOW) ? 1 : 0); })
124
125 #define BTC_RSSI_CHANGE(_rssi_) \
126 ({typeof(_rssi_) __rssi = (_rssi_); \
127 ((__rssi == BTC_RSSI_ST_LOW || \
128 __rssi == BTC_RSSI_ST_HIGH) ? 1 : 0); })
129
130 /* Antenna TX/RX path position masks and helpers */
131 #define BTC_ANT_TX_MASK 0xf0
132 #define BTC_ANT_RX_MASK 0x0f
133 #define BTC_ANT_SHIFT 4
134
135 enum btc_ant {
136 BTC_ANT_SHARED = 0,
137 BTC_ANT_DEDICATED,
138 BTC_ANTTYPE_MAX
139 };
140
141 enum btc_bt_btg {
142 BTC_BT_ALONE = 0,
143 BTC_BT_BTG
144 };
145
146 enum btc_switch {
147 BTC_SWITCH_INTERNAL = 0,
148 BTC_SWITCH_EXTERNAL
149 };
150
151 enum btc_ant_switch_type {
152 BTC_SWITCH_V1_NONE = 0, /* independent antenna */
153 BTC_SWITCH_V1_INTERNAL, /* internal-switch: BTGA structure */
154 };
155
156 enum btc_pkt_type {
157 PACKET_DHCP,
158 PACKET_ARP,
159 PACKET_EAPOL,
160 PACKET_EAPOL_END,
161 PACKET_ICMP,
162 PACKET_MAX
163 };
164
165 enum btc_bt_mailbox_id {
166 BTC_BTINFO_REPLY = 0x23,
167 BTC_BTINFO_AUTO = 0x27
168 };
169
170 enum btc_role_state {
171 BTC_ROLE_START,
172 BTC_ROLE_STOP,
173 BTC_ROLE_CHG_TYPE,
174 BTC_ROLE_MSTS_STA_CONN_START,
175 BTC_ROLE_MSTS_STA_CONN_END,
176 BTC_ROLE_MSTS_STA_DIS_CONN,
177 BTC_ROLE_MSTS_AP_START,
178 BTC_ROLE_MSTS_AP_STOP,
179 BTC_ROLE_STATE_UNKNOWN
180 };
181
182 enum btc_rfctrl {
183 BTC_RFCTRL_WL_OFF,
184 BTC_RFCTRL_WL_ON,
185 BTC_RFCTRL_LPS_WL_ON,
186 BTC_RFCTRL_FW_CTRL,
187 BTC_RFCTRL_MAX
188 };
189
190 enum btc_lps_state {
191 BTC_LPS_OFF = 0,
192 BTC_LPS_RF_OFF = 1,
193 BTC_LPS_RF_ON = 2
194 };
195
196 #define R_BTC_BB_BTG_RX 0x980
197 #define R_BTC_BB_PRE_AGC_S1 0x476C
198 #define R_BTC_BB_PRE_AGC_S0 0x4688
199
200 #define B_BTC_BB_GNT_MUX GENMASK(20, 17)
201 #define B_BTC_BB_PRE_AGC_MASK GENMASK(31, 24)
202 #define B_BTC_BB_PRE_AGC_VAL BIT(31)
203
204 #define BTC_REG_NOTFOUND 0xff
205
206 #define R_BTC_ZB_COEX_TBL_0 0xE328
207 #define R_BTC_ZB_COEX_TBL_1 0xE32c
208 #define R_BTC_ZB_BREAK_TBL 0xE350
209
210 enum btc_ant_div_pos {
211 BTC_ANT_DIV_MAIN = 0,
212 BTC_ANT_DIV_AUX = 1,
213 };
214
215 enum btc_get_reg_status {
216 BTC_CSTATUS_TXDIV_POS = 0,
217 BTC_CSTATUS_RXDIV_POS = 1,
218 BTC_CSTATUS_BB_GNT_MUX = 2,
219 BTC_CSTATUS_BB_GNT_MUX_MON = 3,
220 BTC_CSTATUS_BB_PRE_AGC = 4,
221 BTC_CSTATUS_BB_PRE_AGC_MON = 5,
222 };
223
224 enum btc_preagc_type {
225 BTC_PREAGC_DISABLE,
226 BTC_PREAGC_ENABLE,
227 BTC_PREAGC_BB_FWCTRL,
228 BTC_PREAGC_NOTFOUND,
229 };
230
231 enum btc_btgctrl_type {
232 BTC_BTGCTRL_DISABLE,
233 BTC_BTGCTRL_ENABLE,
234 BTC_BTGCTRL_BB_GNT_FWCTRL,
235 BTC_BTGCTRL_BB_GNT_NOTFOUND,
236 };
237
238 enum btc_wa_type {
239 BTC_WA_5G_HI_CH_RX = BIT(0),
240 BTC_WA_NULL_AP = BIT(1),
241 BTC_WA_HFP_ZB = BIT(2), /* HFP PTA req bit4 define issue */
242 BTC_WA_HFP_LAG = BIT(3), /* 52BT WL break BT Rx lag issue */
243 BTC_WA_INIT_SCAN = BIT(4) /* 52A/C/D init scan move to wl slot WA */
244 };
245
246 enum btc_3cx_type {
247 BTC_3CX_NONE = 0,
248 BTC_3CX_BT2 = BIT(0),
249 BTC_3CX_ZB = BIT(1),
250 BTC_3CX_LTE = BIT(2),
251 BTC_3CX_MAX,
252 };
253
254 enum btc_fddt_type {
255 BTC_FDDT_TYPE_STOP,
256 BTC_FDDT_TYPE_AUTO,
257 BTC_FDDT_TYPE_FIX_TDD,
258 BTC_FDDT_TYPE_FIX_FULL_FDD,
259 BTC_FDDT_MAX,
260 };
261
262 enum btc_chip_feature {
263 BTC_FEAT_PTA_ONOFF_CTRL = BIT(0), /* on/off ctrl by HW (not 0x73[2]) */
264 BTC_FEAT_NONBTG_GWL_THRU = BIT(1), /* non-BTG GNT_WL!=0 if GNT_BT = 1 */
265 BTC_FEAT_WLAN_ACT_MUX = BIT(2), /* separate wlan_act/gnt mux */
266 BTC_FEAT_NEW_BBAPI_FLOW = BIT(3), /* new btg_ctrl/pre_agc_ctrl */
267 BTC_FEAT_MLO_SUPPORT = BIT(4),
268 BTC_FEAT_H2C_MACRO = BIT(5),
269 BTC_FEAT_DUAL_BT = BIT(6),
270 BTC_FEAT_BT_6G = BIT(7),
271 BTC_FEAT_MULTI_PTA = BIT(8),
272 BTC_FEAT_DUAL_BTGA = BIT(9) /* the future A-Die */
273 };
274
275 enum btc_efuse_ant_function_map {
276 BTC_EFMAP_NONE = 0,
277 BTC_EFMAP_BT0 = BIT(0),
278 BTC_EFMAP_BT1 = BIT(1),
279 BTC_EFMAP_ZB = BIT(2), /* ZB or thread */
280 BTC_EFMAP_24GP = BIT(3),
281 BTC_EFMAP_ULL = BIT(4),
282 };
283
284 enum btc_extsoc_interface { /* cx->other.hw_coex */
285 BTC_EXTSOC_INTF_NONE = 0,
286 BTC_EXTSOC_INTF_PTA = BIT(0),
287 BTC_EXTSOC_INTF_MBX = BIT(1),
288 BTC_EXTSOC_INTF_SWIO = BIT(2),
289 BTC_EXTSOC_INTF_MAX,
290 };
291
292 enum btc_esoc_type {
293 BTC_ESOC_NONE,
294 BTC_ESOC_8761,
295 BTC_ESOC_8771,
296 BTC_ESOC_SILAB_MG21,
297 BTC_ESOC_NORDI_NRF52840,
298 BTC_ESOC_MAX,
299 };
300
301 enum btc_wl_mode {
302 BTC_WL_MODE_11B = 0,
303 BTC_WL_MODE_11A = 1,
304 BTC_WL_MODE_11G = 2,
305 BTC_WL_MODE_HT = 3,
306 BTC_WL_MODE_VHT = 4,
307 BTC_WL_MODE_HE = 5,
308 BTC_WL_MODE_NUM,
309 };
310
311 enum btc_mlo_rf_combin {
312 BTC_MLO_RF_2_PLUS_0 = 0,
313 BTC_MLO_RF_0_PLUS_2 = 1,
314 BTC_MLO_RF_1_PLUS_1 = 2,
315 BTC_MLO_RF_2_PLUS_2 = 3,
316 };
317
318 void rtw89_btc_init(struct rtw89_dev *rtwdev);
319 void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev);
320 void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev);
321 void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode);
322 void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band);
323 void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx);
324 void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band);
325 void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev,
326 enum btc_pkt_type pkt_type);
327 void rtw89_btc_ntfy_eapol_packet_work(struct wiphy *wiphy, struct wiphy_work *work);
328 void rtw89_btc_ntfy_arp_packet_work(struct wiphy *wiphy, struct wiphy_work *work);
329 void rtw89_btc_ntfy_dhcp_packet_work(struct wiphy *wiphy, struct wiphy_work *work);
330 void rtw89_btc_ntfy_icmp_packet_work(struct wiphy *wiphy, struct wiphy_work *work);
331 void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev,
332 struct rtw89_vif_link *rtwvif_link,
333 struct rtw89_sta_link *rtwsta_link,
334 enum btc_role_state state);
335 void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state);
336 void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map,
337 enum btc_wl_rfk_type type,
338 enum btc_wl_rfk_state state);
339 void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev);
340 void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
341 u32 len, u8 class, u8 func);
342 ssize_t rtw89_btc_dump_info(struct rtw89_dev *rtwdev, char *buf, size_t bufsz);
343 void rtw89_coex_act1_work(struct wiphy *wiphy, struct wiphy_work *work);
344 void rtw89_coex_bt_devinfo_work(struct wiphy *wiphy, struct wiphy_work *work);
345 void rtw89_coex_rfk_chk_work(struct wiphy *wiphy, struct wiphy_work *work);
346 void rtw89_coex_power_on(struct rtw89_dev *rtwdev);
347 void rtw89_btc_set_policy(struct rtw89_dev *rtwdev, u16 policy_type);
348 void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type);
349 void rtw89_coex_recognize_ver(struct rtw89_dev *rtwdev);
350 void rtw89_btc_ntfy_preserve_bt_time(struct rtw89_dev *rtwdev, u32 ms);
351 void rtw89_btc_ntfy_conn_rfk(struct rtw89_dev *rtwdev, bool state);
352
rtw89_btc_phymap(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_rf_path_bit paths,enum rtw89_chanctx_idx chanctx_idx)353 static inline u8 rtw89_btc_phymap(struct rtw89_dev *rtwdev,
354 enum rtw89_phy_idx phy_idx,
355 enum rtw89_rf_path_bit paths,
356 enum rtw89_chanctx_idx chanctx_idx)
357 {
358 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
359 u8 phy_map;
360
361 phy_map = FIELD_PREP(BTC_RFK_PATH_MAP, paths) |
362 FIELD_PREP(BTC_RFK_PHY_MAP, BIT(phy_idx)) |
363 FIELD_PREP(BTC_RFK_BAND_MAP, chan->band_type);
364
365 return phy_map;
366 }
367
rtw89_btc_path_phymap(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)368 static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev,
369 enum rtw89_phy_idx phy_idx,
370 enum rtw89_rf_path path,
371 enum rtw89_chanctx_idx chanctx_idx)
372 {
373 return rtw89_btc_phymap(rtwdev, phy_idx, BIT(path), chanctx_idx);
374 }
375
376 /* return bt req len in TU */
rtw89_coex_query_bt_req_len(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)377 static inline u16 rtw89_coex_query_bt_req_len(struct rtw89_dev *rtwdev,
378 enum rtw89_phy_idx phy_idx)
379 {
380 struct rtw89_btc *btc = &rtwdev->btc;
381
382 return btc->bt_req_len[phy_idx];
383 }
384
rtw89_get_antpath_type(u8 phy_map,u8 type)385 static inline u32 rtw89_get_antpath_type(u8 phy_map, u8 type)
386 {
387 return ((phy_map << 8) + type);
388 }
389
390 static inline
_slot_set_le(struct rtw89_btc * btc,u8 sid,__le16 dura,__le32 tbl,__le16 type)391 void _slot_set_le(struct rtw89_btc *btc, u8 sid, __le16 dura, __le32 tbl, __le16 type)
392 {
393 if (btc->ver->fcxslots == 1) {
394 btc->dm.slot.v1[sid].dur = dura;
395 btc->dm.slot.v1[sid].cxtbl = tbl;
396 btc->dm.slot.v1[sid].cxtype = type;
397 } else if (btc->ver->fcxslots == 2 || btc->ver->fcxslots == 7) {
398 btc->dm.slot.v7[sid].dur = dura;
399 btc->dm.slot.v7[sid].cxtype = type;
400 btc->dm.slot.v7[sid].cxtbl = tbl;
401 }
402 }
403
404 static inline
_slot_set(struct rtw89_btc * btc,u8 sid,u16 dura,u32 tbl,u16 type)405 void _slot_set(struct rtw89_btc *btc, u8 sid, u16 dura, u32 tbl, u16 type)
406 {
407 _slot_set_le(btc, sid, cpu_to_le16(dura), cpu_to_le32(tbl), cpu_to_le16(type));
408 }
409
410 static inline
_slot_set_dur(struct rtw89_btc * btc,u8 sid,u16 dura)411 void _slot_set_dur(struct rtw89_btc *btc, u8 sid, u16 dura)
412 {
413 if (btc->ver->fcxslots == 1)
414 btc->dm.slot.v1[sid].dur = cpu_to_le16(dura);
415 else if (btc->ver->fcxslots == 2 || btc->ver->fcxslots == 7)
416 btc->dm.slot.v7[sid].dur = cpu_to_le16(dura);
417 }
418
419 static inline
_slot_set_type(struct rtw89_btc * btc,u8 sid,u16 type)420 void _slot_set_type(struct rtw89_btc *btc, u8 sid, u16 type)
421 {
422 if (btc->ver->fcxslots == 1)
423 btc->dm.slot.v1[sid].cxtype = cpu_to_le16(type);
424 else if (btc->ver->fcxslots == 2 || btc->ver->fcxslots == 7)
425 btc->dm.slot.v7[sid].cxtype = cpu_to_le16(type);
426 }
427
428 static inline
_slot_set_tbl(struct rtw89_btc * btc,u8 sid,u32 tbl)429 void _slot_set_tbl(struct rtw89_btc *btc, u8 sid, u32 tbl)
430 {
431 if (btc->ver->fcxslots == 1)
432 btc->dm.slot.v1[sid].cxtbl = cpu_to_le32(tbl);
433 else if (btc->ver->fcxslots == 2 || btc->ver->fcxslots == 7)
434 btc->dm.slot.v7[sid].cxtbl = cpu_to_le32(tbl);
435 }
436
437 static inline
btc_dw2b(u8 * buf,size_t idx,u32 val)438 void btc_dw2b(u8 *buf, size_t idx, u32 val)
439 {
440 buf[idx] = u32_get_bits(val, MASKBYTE0);
441 buf[idx + 1] = u32_get_bits(val, MASKBYTE1);
442 buf[idx + 2] = u32_get_bits(val, MASKBYTE2);
443 buf[idx + 3] = u32_get_bits(val, MASKBYTE3);
444 }
445
446 static inline
_btc_get_rf_path_from_ant_num(struct rtw89_btc * btc,u8 antnum)447 u8 _btc_get_rf_path_from_ant_num(struct rtw89_btc *btc, u8 antnum)
448 {
449 switch (antnum) {
450 default:
451 case 1:
452 return btc->mdinfo.ant.single_pos;
453 case 2:
454 return RF_PATH_AB;
455 case 3:
456 return RF_PATH_ABC;
457 }
458 }
459
460 #endif
461